arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/platform_data/at24.h>
  22 #include <linux/leds.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/slab.h>
  26 #include <linux/mtd/rawnand.h>
  27 #include <linux/input.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/eeprom.h>
  30 #include <linux/v4l2-dv-timings.h>
  31
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/arch.h>
  34
  35 #include <mach/mux.h>
  36 #include <mach/common.h>
  37 #include <linux/platform_data/i2c-davinci.h>
  38 #include <mach/serial.h>
  39 #include <linux/platform_data/mmc-davinci.h>
  40 #include <linux/platform_data/mtd-davinci.h>
  41 #include <linux/platform_data/keyscan-davinci.h>
  42
  43 #include <media/i2c/ths7303.h>
  44 #include <media/i2c/tvp514x.h>
  45
  46 #include "davinci.h"
  47
  48 static inline int have_imager(void)
  49 {
  50         /* REVISIT when it's supported, trigger via Kconfig */
  51         return 0;
  52 }
  53
  54 static inline int have_tvp7002(void)
  55 {
  56         /* REVISIT when it's supported, trigger via Kconfig */
  57         return 0;
  58 }
  59
  60 #define DM365_EVM_PHY_ID                "davinci_mdio-0:01"
  61 /*
  62  * A MAX-II CPLD is used for various board control functions.
  63  */
  64 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  65
  66 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  67 #define CPLD_TEST       CPLD_OFFSET(0,1)
  68 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  69 #define CPLD_MUX        CPLD_OFFSET(0,3)
  70 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  71 #define CPLD_POWER      CPLD_OFFSET(1,1)
  72 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  73 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  74
  75 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  76 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  77
  78 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  79 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  80 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  81 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  82 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  83 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  84 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  85 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  86 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  87
  88 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  89
  90 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  91 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  92 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  93 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  94 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  95 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
  96
  97 static void __iomem *cpld;
  98
  99
 100 /* NOTE:  this is geared for the standard config, with a socketed
 101  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 102  * swap chips with a different block size, partitioning will
 103  * need to be changed. This NAND chip MT29F16G08FAA is the default
 104  * NAND shipped with the Spectrum Digital DM365 EVM
 105  */
 106 #define NAND_BLOCK_SIZE         SZ_128K
 107
 108 static struct mtd_partition davinci_nand_partitions[] = {
 109         {
 110                 /* UBL (a few copies) plus U-Boot */
 111                 .name           = "bootloader",
 112                 .offset         = 0,
 113                 .size           = 30 * NAND_BLOCK_SIZE,
 114                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 115         }, {
 116                 /* U-Boot environment */
 117                 .name           = "params",
 118                 .offset         = MTDPART_OFS_APPEND,
 119                 .size           = 2 * NAND_BLOCK_SIZE,
 120                 .mask_flags     = 0,
 121         }, {
 122                 .name           = "kernel",
 123                 .offset         = MTDPART_OFS_APPEND,
 124                 .size           = SZ_4M,
 125                 .mask_flags     = 0,
 126         }, {
 127                 .name           = "filesystem1",
 128                 .offset         = MTDPART_OFS_APPEND,
 129                 .size           = SZ_512M,
 130                 .mask_flags     = 0,
 131         }, {
 132                 .name           = "filesystem2",
 133                 .offset         = MTDPART_OFS_APPEND,
 134                 .size           = MTDPART_SIZ_FULL,
 135                 .mask_flags     = 0,
 136         }
 137         /* two blocks with bad block table (and mirror) at the end */
 138 };
 139
 140 static struct davinci_nand_pdata davinci_nand_data = {
 141         .core_chipsel           = 0,
 142         .mask_chipsel           = BIT(14),
 143         .parts                  = davinci_nand_partitions,
 144         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 145         .ecc_mode               = NAND_ECC_HW,
 146         .bbt_options            = NAND_BBT_USE_FLASH,
 147         .ecc_bits               = 4,
 148 };
 149
 150 static struct resource davinci_nand_resources[] = {
 151         {
 152                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 153                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 154                 .flags          = IORESOURCE_MEM,
 155         }, {
 156                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 157                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 158                 .flags          = IORESOURCE_MEM,
 159         },
 160 };
 161
 162 static struct platform_device davinci_nand_device = {
 163         .name                   = "davinci_nand",
 164         .id                     = 0,
 165         .num_resources          = ARRAY_SIZE(davinci_nand_resources),
 166         .resource               = davinci_nand_resources,
 167         .dev                    = {
 168                 .platform_data  = &davinci_nand_data,
 169         },
 170 };
 171
 172 static struct at24_platform_data eeprom_info = {
 173         .byte_len       = (256*1024) / 8,
 174         .page_size      = 64,
 175         .flags          = AT24_FLAG_ADDR16,
 176         .setup          = davinci_get_mac_addr,
 177         .context        = (void *)0x7f00,
 178 };
 179
 180 static struct i2c_board_info i2c_info[] = {
 181         {
 182                 I2C_BOARD_INFO("24c256", 0x50),
 183                 .platform_data  = &eeprom_info,
 184         },
 185         {
 186                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 187         },
 188 };
 189
 190 static struct davinci_i2c_platform_data i2c_pdata = {
 191         .bus_freq       = 400   /* kHz */,
 192         .bus_delay      = 0     /* usec */,
 193 };
 194
 195 static int dm365evm_keyscan_enable(struct device *dev)
 196 {
 197         return davinci_cfg_reg(DM365_KEYSCAN);
 198 }
 199
 200 static unsigned short dm365evm_keymap[] = {
 201         KEY_KP2,
 202         KEY_LEFT,
 203         KEY_EXIT,
 204         KEY_DOWN,
 205         KEY_ENTER,
 206         KEY_UP,
 207         KEY_KP1,
 208         KEY_RIGHT,
 209         KEY_MENU,
 210         KEY_RECORD,
 211         KEY_REWIND,
 212         KEY_KPMINUS,
 213         KEY_STOP,
 214         KEY_FASTFORWARD,
 215         KEY_KPPLUS,
 216         KEY_PLAYPAUSE,
 217         0
 218 };
 219
 220 static struct davinci_ks_platform_data dm365evm_ks_data = {
 221         .device_enable  = dm365evm_keyscan_enable,
 222         .keymap         = dm365evm_keymap,
 223         .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
 224         .rep            = 1,
 225         /* Scan period = strobe + interval */
 226         .strobe         = 0x5,
 227         .interval       = 0x2,
 228         .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
 229 };
 230
 231 static int cpld_mmc_get_cd(int module)
 232 {
 233         if (!cpld)
 234                 return -ENXIO;
 235
 236         /* low == card present */
 237         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 238 }
 239
 240 static int cpld_mmc_get_ro(int module)
 241 {
 242         if (!cpld)
 243                 return -ENXIO;
 244
 245         /* high == card's write protect switch active */
 246         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 247 }
 248
 249 static struct davinci_mmc_config dm365evm_mmc_config = {
 250         .get_cd         = cpld_mmc_get_cd,
 251         .get_ro         = cpld_mmc_get_ro,
 252         .wires          = 4,
 253         .max_freq       = 50000000,
 254         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 255 };
 256
 257 static void dm365evm_emac_configure(void)
 258 {
 259         /*
 260          * EMAC pins are multiplexed with GPIO and UART
 261          * Further details are available at the DM365 ARM
 262          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 263          */
 264         davinci_cfg_reg(DM365_EMAC_TX_EN);
 265         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 266         davinci_cfg_reg(DM365_EMAC_COL);
 267         davinci_cfg_reg(DM365_EMAC_TXD3);
 268         davinci_cfg_reg(DM365_EMAC_TXD2);
 269         davinci_cfg_reg(DM365_EMAC_TXD1);
 270         davinci_cfg_reg(DM365_EMAC_TXD0);
 271         davinci_cfg_reg(DM365_EMAC_RXD3);
 272         davinci_cfg_reg(DM365_EMAC_RXD2);
 273         davinci_cfg_reg(DM365_EMAC_RXD1);
 274         davinci_cfg_reg(DM365_EMAC_RXD0);
 275         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 276         davinci_cfg_reg(DM365_EMAC_RX_DV);
 277         davinci_cfg_reg(DM365_EMAC_RX_ER);
 278         davinci_cfg_reg(DM365_EMAC_CRS);
 279         davinci_cfg_reg(DM365_EMAC_MDIO);
 280         davinci_cfg_reg(DM365_EMAC_MDCLK);
 281
 282         /*
 283          * EMAC interrupts are multiplexed with GPIO interrupts
 284          * Details are available at the DM365 ARM
 285          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 286          */
 287         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 288         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 289         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 290         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 291 }
 292
 293 static void dm365evm_mmc_configure(void)
 294 {
 295         /*
 296          * MMC/SD pins are multiplexed with GPIO and EMIF
 297          * Further details are available at the DM365 ARM
 298          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 299          */
 300         davinci_cfg_reg(DM365_SD1_CLK);
 301         davinci_cfg_reg(DM365_SD1_CMD);
 302         davinci_cfg_reg(DM365_SD1_DATA3);
 303         davinci_cfg_reg(DM365_SD1_DATA2);
 304         davinci_cfg_reg(DM365_SD1_DATA1);
 305         davinci_cfg_reg(DM365_SD1_DATA0);
 306 }
 307
 308 static struct tvp514x_platform_data tvp5146_pdata = {
 309         .clk_polarity = 0,
 310         .hs_polarity = 1,
 311         .vs_polarity = 1
 312 };
 313
 314 #define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
 315 /* Inputs available at the TVP5146 */
 316 static struct v4l2_input tvp5146_inputs[] = {
 317         {
 318                 .index = 0,
 319                 .name = "Composite",
 320                 .type = V4L2_INPUT_TYPE_CAMERA,
 321                 .std = TVP514X_STD_ALL,
 322         },
 323         {
 324                 .index = 1,
 325                 .name = "S-Video",
 326                 .type = V4L2_INPUT_TYPE_CAMERA,
 327                 .std = TVP514X_STD_ALL,
 328         },
 329 };
 330
 331 /*
 332  * this is the route info for connecting each input to decoder
 333  * ouput that goes to vpfe. There is a one to one correspondence
 334  * with tvp5146_inputs
 335  */
 336 static struct vpfe_route tvp5146_routes[] = {
 337         {
 338                 .input = INPUT_CVBS_VI2B,
 339                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 340         },
 341 {
 342                 .input = INPUT_SVIDEO_VI2C_VI1C,
 343                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 344         },
 345 };
 346
 347 static struct vpfe_subdev_info vpfe_sub_devs[] = {
 348         {
 349                 .name = "tvp5146",
 350                 .grp_id = 0,
 351                 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
 352                 .inputs = tvp5146_inputs,
 353                 .routes = tvp5146_routes,
 354                 .can_route = 1,
 355                 .ccdc_if_params = {
 356                         .if_type = VPFE_BT656,
 357                         .hdpol = VPFE_PINPOL_POSITIVE,
 358                         .vdpol = VPFE_PINPOL_POSITIVE,
 359                 },
 360                 .board_info = {
 361                         I2C_BOARD_INFO("tvp5146", 0x5d),
 362                         .platform_data = &tvp5146_pdata,
 363                 },
 364         },
 365 };
 366
 367 static struct vpfe_config vpfe_cfg = {
 368         .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
 369         .sub_devs = vpfe_sub_devs,
 370         .i2c_adapter_id = 1,
 371         .card_name = "DM365 EVM",
 372         .ccdc = "ISIF",
 373 };
 374
 375 /* venc standards timings */
 376 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
 377         {
 378                 .name           = "ntsc",
 379                 .timings_type   = VPBE_ENC_STD,
 380                 .std_id         = V4L2_STD_NTSC,
 381                 .interlaced     = 1,
 382                 .xres           = 720,
 383                 .yres           = 480,
 384                 .aspect         = {11, 10},
 385                 .fps            = {30000, 1001},
 386                 .left_margin    = 0x79,
 387                 .upper_margin   = 0x10,
 388         },
 389         {
 390                 .name           = "pal",
 391                 .timings_type   = VPBE_ENC_STD,
 392                 .std_id         = V4L2_STD_PAL,
 393                 .interlaced     = 1,
 394                 .xres           = 720,
 395                 .yres           = 576,
 396                 .aspect         = {54, 59},
 397                 .fps            = {25, 1},
 398                 .left_margin    = 0x7E,
 399                 .upper_margin   = 0x16,
 400         },
 401 };
 402
 403 /* venc dv timings */
 404 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
 405         {
 406                 .name           = "480p59_94",
 407                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 408                 .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
 409                 .interlaced     = 0,
 410                 .xres           = 720,
 411                 .yres           = 480,
 412                 .aspect         = {1, 1},
 413                 .fps            = {5994, 100},
 414                 .left_margin    = 0x8F,
 415                 .upper_margin   = 0x2D,
 416         },
 417         {
 418                 .name           = "576p50",
 419                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 420                 .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
 421                 .interlaced     = 0,
 422                 .xres           = 720,
 423                 .yres           = 576,
 424                 .aspect         = {1, 1},
 425                 .fps            = {50, 1},
 426                 .left_margin    = 0x8C,
 427                 .upper_margin   = 0x36,
 428         },
 429         {
 430                 .name           = "720p60",
 431                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 432                 .dv_timings     = V4L2_DV_BT_CEA_1280X720P60,
 433                 .interlaced     = 0,
 434                 .xres           = 1280,
 435                 .yres           = 720,
 436                 .aspect         = {1, 1},
 437                 .fps            = {60, 1},
 438                 .left_margin    = 0x117,
 439                 .right_margin   = 70,
 440                 .upper_margin   = 38,
 441                 .lower_margin   = 3,
 442                 .hsync_len      = 80,
 443                 .vsync_len      = 5,
 444         },
 445         {
 446                 .name           = "1080i60",
 447                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 448                 .dv_timings     = V4L2_DV_BT_CEA_1920X1080I60,
 449                 .interlaced     = 1,
 450                 .xres           = 1920,
 451                 .yres           = 1080,
 452                 .aspect         = {1, 1},
 453                 .fps            = {30, 1},
 454                 .left_margin    = 0xc9,
 455                 .right_margin   = 80,
 456                 .upper_margin   = 30,
 457                 .lower_margin   = 3,
 458                 .hsync_len      = 88,
 459                 .vsync_len      = 5,
 460         },
 461 };
 462
 463 #define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
 464
 465 /*
 466  * The outputs available from VPBE + ecnoders. Keep the
 467  * the order same as that of encoders. First those from venc followed by that
 468  * from encoders. Index in the output refers to index on a particular
 469  * encoder.Driver uses this index to pass it to encoder when it supports more
 470  * than one output. Application uses index of the array to set an output.
 471  */
 472 static struct vpbe_output dm365evm_vpbe_outputs[] = {
 473         {
 474                 .output         = {
 475                         .index          = 0,
 476                         .name           = "Composite",
 477                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
 478                         .std            = VENC_STD_ALL,
 479                         .capabilities   = V4L2_OUT_CAP_STD,
 480                 },
 481                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 482                 .default_mode   = "ntsc",
 483                 .num_modes      = ARRAY_SIZE(dm365evm_enc_std_timing),
 484                 .modes          = dm365evm_enc_std_timing,
 485                 .if_params      = MEDIA_BUS_FMT_FIXED,
 486         },
 487         {
 488                 .output         = {
 489                         .index          = 1,
 490                         .name           = "Component",
 491                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
 492                         .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
 493                 },
 494                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 495                 .default_mode   = "480p59_94",
 496                 .num_modes      = ARRAY_SIZE(dm365evm_enc_preset_timing),
 497                 .modes          = dm365evm_enc_preset_timing,
 498                 .if_params      = MEDIA_BUS_FMT_FIXED,
 499         },
 500 };
 501
 502 /*
 503  * Amplifiers on the board
 504  */
 505 static struct ths7303_platform_data ths7303_pdata = {
 506         .ch_1 = 3,
 507         .ch_2 = 3,
 508         .ch_3 = 3,
 509 };
 510
 511 static struct amp_config_info vpbe_amp = {
 512         .module_name    = "ths7303",
 513         .is_i2c         = 1,
 514         .board_info     = {
 515                 I2C_BOARD_INFO("ths7303", 0x2c),
 516                 .platform_data = &ths7303_pdata,
 517         }
 518 };
 519
 520 static struct vpbe_config dm365evm_display_cfg = {
 521         .module_name    = "dm365-vpbe-display",
 522         .i2c_adapter_id = 1,
 523         .amp            = &vpbe_amp,
 524         .osd            = {
 525                 .module_name    = DM365_VPBE_OSD_SUBDEV_NAME,
 526         },
 527         .venc           = {
 528                 .module_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 529         },
 530         .num_outputs    = ARRAY_SIZE(dm365evm_vpbe_outputs),
 531         .outputs        = dm365evm_vpbe_outputs,
 532 };
 533
 534 static void __init evm_init_i2c(void)
 535 {
 536         davinci_init_i2c(&i2c_pdata);
 537         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 538 }
 539
 540 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
 541         &davinci_nand_device,
 542 };
 543
 544 static inline int have_leds(void)
 545 {
 546 #ifdef CONFIG_LEDS_CLASS
 547         return 1;
 548 #else
 549         return 0;
 550 #endif
 551 }
 552
 553 struct cpld_led {
 554         struct led_classdev     cdev;
 555         u8                      mask;
 556 };
 557
 558 static const struct {
 559         const char *name;
 560         const char *trigger;
 561 } cpld_leds[] = {
 562         { "dm365evm::ds2", },
 563         { "dm365evm::ds3", },
 564         { "dm365evm::ds4", },
 565         { "dm365evm::ds5", },
 566         { "dm365evm::ds6", "nand-disk", },
 567         { "dm365evm::ds7", "mmc1", },
 568         { "dm365evm::ds8", "mmc0", },
 569         { "dm365evm::ds9", "heartbeat", },
 570 };
 571
 572 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 573 {
 574         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 575         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 576
 577         if (b != LED_OFF)
 578                 reg &= ~led->mask;
 579         else
 580                 reg |= led->mask;
 581         __raw_writeb(reg, cpld + CPLD_LEDS);
 582 }
 583
 584 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 585 {
 586         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 587         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 588
 589         return (reg & led->mask) ? LED_OFF : LED_FULL;
 590 }
 591
 592 static int __init cpld_leds_init(void)
 593 {
 594         int     i;
 595
 596         if (!have_leds() ||  !cpld)
 597                 return 0;
 598
 599         /* setup LEDs */
 600         __raw_writeb(0xff, cpld + CPLD_LEDS);
 601         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 602                 struct cpld_led *led;
 603
 604                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 605                 if (!led)
 606                         break;
 607
 608                 led->cdev.name = cpld_leds[i].name;
 609                 led->cdev.brightness_set = cpld_led_set;
 610                 led->cdev.brightness_get = cpld_led_get;
 611                 led->cdev.default_trigger = cpld_leds[i].trigger;
 612                 led->mask = BIT(i);
 613
 614                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 615                         kfree(led);
 616                         break;
 617                 }
 618         }
 619
 620         return 0;
 621 }
 622 /* run after subsys_initcall() for LEDs */
 623 fs_initcall(cpld_leds_init);
 624
 625
 626 static void __init evm_init_cpld(void)
 627 {
 628         u8 mux, resets;
 629         const char *label;
 630         struct clk *aemif_clk;
 631
 632         /* Make sure we can configure the CPLD through CS1.  Then
 633          * leave it on for later access to MMC and LED registers.
 634          */
 635         aemif_clk = clk_get(NULL, "aemif");
 636         if (IS_ERR(aemif_clk))
 637                 return;
 638         clk_prepare_enable(aemif_clk);
 639
 640         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 641                         "cpld") == NULL)
 642                 goto fail;
 643         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 644         if (!cpld) {
 645                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 646                                 SECTION_SIZE);
 647 fail:
 648                 pr_err("ERROR: can't map CPLD\n");
 649                 clk_disable_unprepare(aemif_clk);
 650                 return;
 651         }
 652
 653         /* External muxing for some signals */
 654         mux = 0;
 655
 656         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 657          * NOTE:  SW4 bus width setting must match!
 658          */
 659         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 660                 /* external keypad mux */
 661                 mux |= BIT(7);
 662
 663                 platform_add_devices(dm365_evm_nand_devices,
 664                                 ARRAY_SIZE(dm365_evm_nand_devices));
 665         } else {
 666                 /* no OneNAND support yet */
 667         }
 668
 669         /* Leave external chips in reset when unused. */
 670         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 671
 672         /* Static video input config with SN74CBT16214 1-of-3 mux:
 673          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 674          *  - port b2 == imager (mux lowbits == 2 or 7)
 675          *  - port b3 == tvp5146 (mux lowbits == 5)
 676          *
 677          * Runtime switching could work too, with limitations.
 678          */
 679         if (have_imager()) {
 680                 label = "HD imager";
 681                 mux |= 2;
 682
 683                 /* externally mux MMC1/ENET/AIC33 to imager */
 684                 mux |= BIT(6) | BIT(5) | BIT(3);
 685         } else {
 686                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 687
 688                 /* we can use MMC1 ... */
 689                 dm365evm_mmc_configure();
 690                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 691
 692                 /* ... and ENET ... */
 693                 dm365evm_emac_configure();
 694                 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
 695                 resets &= ~BIT(3);
 696
 697                 /* ... and AIC33 */
 698                 resets &= ~BIT(1);
 699
 700                 if (have_tvp7002()) {
 701                         mux |= 1;
 702                         resets &= ~BIT(2);
 703                         label = "tvp7002 HD";
 704                 } else {
 705                         /* default to tvp5146 */
 706                         mux |= 5;
 707                         resets &= ~BIT(0);
 708                         label = "tvp5146 SD";
 709                 }
 710         }
 711         __raw_writeb(mux, cpld + CPLD_MUX);
 712         __raw_writeb(resets, cpld + CPLD_RESETS);
 713         pr_info("EVM: %s video input\n", label);
 714
 715         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 716 }
 717
 718 static void __init dm365_evm_map_io(void)
 719 {
 720         dm365_init();
 721 }
 722
 723 static struct spi_eeprom at25640 = {
 724         .byte_len       = SZ_64K / 8,
 725         .name           = "at25640",
 726         .page_size      = 32,
 727         .flags          = EE_ADDR2,
 728 };
 729
 730 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
 731         {
 732                 .modalias       = "at25",
 733                 .platform_data  = &at25640,
 734                 .max_speed_hz   = 10 * 1000 * 1000,
 735                 .bus_num        = 0,
 736                 .chip_select    = 0,
 737                 .mode           = SPI_MODE_0,
 738         },
 739 };
 740
 741 static __init void dm365_evm_init(void)
 742 {
 743         int ret;
 744
 745         ret = dm365_gpio_register();
 746         if (ret)
 747                 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
 748
 749         evm_init_i2c();
 750         davinci_serial_init(dm365_serial_device);
 751
 752         dm365evm_emac_configure();
 753         dm365evm_mmc_configure();
 754
 755         davinci_setup_mmc(0, &dm365evm_mmc_config);
 756
 757         dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
 758
 759         /* maybe setup mmc1/etc ... _after_ mmc0 */
 760         evm_init_cpld();
 761
 762 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
 763         dm365_init_asp();
 764 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
 765         dm365_init_vc();
 766 #endif
 767         dm365_init_rtc();
 768         dm365_init_ks(&dm365evm_ks_data);
 769
 770         dm365_init_spi0(BIT(0), dm365_evm_spi_info,
 771                         ARRAY_SIZE(dm365_evm_spi_info));
 772 }
 773
 774 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 775         .atag_offset    = 0x100,
 776         .map_io         = dm365_evm_map_io,
 777         .init_irq       = davinci_irq_init,
 778         .init_time      = dm365_init_time,
 779         .init_machine   = dm365_evm_init,
 780         .init_late      = davinci_init_late,
 781         .dma_zone_size  = SZ_128M,
 782 MACHINE_END
 783