arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/platform_data/at24.h>
  22 #include <linux/leds.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/slab.h>
  26 #include <linux/mtd/rawnand.h>
  27 #include <linux/input.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/eeprom.h>
  30 #include <linux/v4l2-dv-timings.h>
  31 #include <linux/platform_data/ti-aemif.h>
  32
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/arch.h>
  35
  36 #include <mach/mux.h>
  37 #include <mach/common.h>
  38 #include <linux/platform_data/i2c-davinci.h>
  39 #include <mach/serial.h>
  40 #include <linux/platform_data/mmc-davinci.h>
  41 #include <linux/platform_data/mtd-davinci.h>
  42 #include <linux/platform_data/keyscan-davinci.h>
  43
  44 #include <media/i2c/ths7303.h>
  45 #include <media/i2c/tvp514x.h>
  46
  47 #include "davinci.h"
  48
  49 static inline int have_imager(void)
  50 {
  51         /* REVISIT when it's supported, trigger via Kconfig */
  52         return 0;
  53 }
  54
  55 static inline int have_tvp7002(void)
  56 {
  57         /* REVISIT when it's supported, trigger via Kconfig */
  58         return 0;
  59 }
  60
  61 #define DM365_EVM_PHY_ID                "davinci_mdio-0:01"
  62 /*
  63  * A MAX-II CPLD is used for various board control functions.
  64  */
  65 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  66
  67 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  68 #define CPLD_TEST       CPLD_OFFSET(0,1)
  69 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  70 #define CPLD_MUX        CPLD_OFFSET(0,3)
  71 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  72 #define CPLD_POWER      CPLD_OFFSET(1,1)
  73 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  74 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  75
  76 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  77 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  78
  79 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  80 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  81 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  82 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  83 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  84 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  85 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  86 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  87 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  88
  89 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  90
  91 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  92 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  93 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  94 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  95 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  96 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
  97
  98 static void __iomem *cpld;
  99
 100
 101 /* NOTE:  this is geared for the standard config, with a socketed
 102  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 103  * swap chips with a different block size, partitioning will
 104  * need to be changed. This NAND chip MT29F16G08FAA is the default
 105  * NAND shipped with the Spectrum Digital DM365 EVM
 106  */
 107 #define NAND_BLOCK_SIZE         SZ_128K
 108
 109 static struct mtd_partition davinci_nand_partitions[] = {
 110         {
 111                 /* UBL (a few copies) plus U-Boot */
 112                 .name           = "bootloader",
 113                 .offset         = 0,
 114                 .size           = 30 * NAND_BLOCK_SIZE,
 115                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 116         }, {
 117                 /* U-Boot environment */
 118                 .name           = "params",
 119                 .offset         = MTDPART_OFS_APPEND,
 120                 .size           = 2 * NAND_BLOCK_SIZE,
 121                 .mask_flags     = 0,
 122         }, {
 123                 .name           = "kernel",
 124                 .offset         = MTDPART_OFS_APPEND,
 125                 .size           = SZ_4M,
 126                 .mask_flags     = 0,
 127         }, {
 128                 .name           = "filesystem1",
 129                 .offset         = MTDPART_OFS_APPEND,
 130                 .size           = SZ_512M,
 131                 .mask_flags     = 0,
 132         }, {
 133                 .name           = "filesystem2",
 134                 .offset         = MTDPART_OFS_APPEND,
 135                 .size           = MTDPART_SIZ_FULL,
 136                 .mask_flags     = 0,
 137         }
 138         /* two blocks with bad block table (and mirror) at the end */
 139 };
 140
 141 static struct davinci_nand_pdata davinci_nand_data = {
 142         .core_chipsel           = 0,
 143         .mask_chipsel           = BIT(14),
 144         .parts                  = davinci_nand_partitions,
 145         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 146         .ecc_mode               = NAND_ECC_HW,
 147         .bbt_options            = NAND_BBT_USE_FLASH,
 148         .ecc_bits               = 4,
 149 };
 150
 151 static struct resource davinci_nand_resources[] = {
 152         {
 153                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 154                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 155                 .flags          = IORESOURCE_MEM,
 156         }, {
 157                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 158                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 159                 .flags          = IORESOURCE_MEM,
 160         },
 161 };
 162
 163 static struct platform_device davinci_aemif_devices[] = {
 164         {
 165                 .name           = "davinci_nand",
 166                 .id             = 0,
 167                 .num_resources  = ARRAY_SIZE(davinci_nand_resources),
 168                 .resource       = davinci_nand_resources,
 169                 .dev            = {
 170                         .platform_data  = &davinci_nand_data,
 171                 },
 172         }
 173 };
 174
 175 static struct resource davinci_aemif_resources[] = {
 176         {
 177                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 178                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 179                 .flags          = IORESOURCE_MEM,
 180         },
 181 };
 182
 183 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
 184         {
 185                 .cs             = 1,
 186         },
 187 };
 188
 189 static struct aemif_platform_data davinci_aemif_pdata = {
 190         .abus_data              = da850_evm_aemif_abus_data,
 191         .num_abus_data          = ARRAY_SIZE(da850_evm_aemif_abus_data),
 192         .sub_devices            = davinci_aemif_devices,
 193         .num_sub_devices        = ARRAY_SIZE(davinci_aemif_devices),
 194 };
 195
 196 static struct platform_device davinci_aemif_device = {
 197         .name                   = "ti-aemif",
 198         .id                     = -1,
 199         .dev = {
 200                 .platform_data  = &davinci_aemif_pdata,
 201         },
 202         .resource               = davinci_aemif_resources,
 203         .num_resources          = ARRAY_SIZE(davinci_aemif_resources),
 204 };
 205
 206 static struct at24_platform_data eeprom_info = {
 207         .byte_len       = (256*1024) / 8,
 208         .page_size      = 64,
 209         .flags          = AT24_FLAG_ADDR16,
 210         .setup          = davinci_get_mac_addr,
 211         .context        = (void *)0x7f00,
 212 };
 213
 214 static struct i2c_board_info i2c_info[] = {
 215         {
 216                 I2C_BOARD_INFO("24c256", 0x50),
 217                 .platform_data  = &eeprom_info,
 218         },
 219         {
 220                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 221         },
 222 };
 223
 224 static struct davinci_i2c_platform_data i2c_pdata = {
 225         .bus_freq       = 400   /* kHz */,
 226         .bus_delay      = 0     /* usec */,
 227 };
 228
 229 static int dm365evm_keyscan_enable(struct device *dev)
 230 {
 231         return davinci_cfg_reg(DM365_KEYSCAN);
 232 }
 233
 234 static unsigned short dm365evm_keymap[] = {
 235         KEY_KP2,
 236         KEY_LEFT,
 237         KEY_EXIT,
 238         KEY_DOWN,
 239         KEY_ENTER,
 240         KEY_UP,
 241         KEY_KP1,
 242         KEY_RIGHT,
 243         KEY_MENU,
 244         KEY_RECORD,
 245         KEY_REWIND,
 246         KEY_KPMINUS,
 247         KEY_STOP,
 248         KEY_FASTFORWARD,
 249         KEY_KPPLUS,
 250         KEY_PLAYPAUSE,
 251         0
 252 };
 253
 254 static struct davinci_ks_platform_data dm365evm_ks_data = {
 255         .device_enable  = dm365evm_keyscan_enable,
 256         .keymap         = dm365evm_keymap,
 257         .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
 258         .rep            = 1,
 259         /* Scan period = strobe + interval */
 260         .strobe         = 0x5,
 261         .interval       = 0x2,
 262         .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
 263 };
 264
 265 static int cpld_mmc_get_cd(int module)
 266 {
 267         if (!cpld)
 268                 return -ENXIO;
 269
 270         /* low == card present */
 271         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 272 }
 273
 274 static int cpld_mmc_get_ro(int module)
 275 {
 276         if (!cpld)
 277                 return -ENXIO;
 278
 279         /* high == card's write protect switch active */
 280         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 281 }
 282
 283 static struct davinci_mmc_config dm365evm_mmc_config = {
 284         .get_cd         = cpld_mmc_get_cd,
 285         .get_ro         = cpld_mmc_get_ro,
 286         .wires          = 4,
 287         .max_freq       = 50000000,
 288         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 289 };
 290
 291 static void dm365evm_emac_configure(void)
 292 {
 293         /*
 294          * EMAC pins are multiplexed with GPIO and UART
 295          * Further details are available at the DM365 ARM
 296          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 297          */
 298         davinci_cfg_reg(DM365_EMAC_TX_EN);
 299         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 300         davinci_cfg_reg(DM365_EMAC_COL);
 301         davinci_cfg_reg(DM365_EMAC_TXD3);
 302         davinci_cfg_reg(DM365_EMAC_TXD2);
 303         davinci_cfg_reg(DM365_EMAC_TXD1);
 304         davinci_cfg_reg(DM365_EMAC_TXD0);
 305         davinci_cfg_reg(DM365_EMAC_RXD3);
 306         davinci_cfg_reg(DM365_EMAC_RXD2);
 307         davinci_cfg_reg(DM365_EMAC_RXD1);
 308         davinci_cfg_reg(DM365_EMAC_RXD0);
 309         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 310         davinci_cfg_reg(DM365_EMAC_RX_DV);
 311         davinci_cfg_reg(DM365_EMAC_RX_ER);
 312         davinci_cfg_reg(DM365_EMAC_CRS);
 313         davinci_cfg_reg(DM365_EMAC_MDIO);
 314         davinci_cfg_reg(DM365_EMAC_MDCLK);
 315
 316         /*
 317          * EMAC interrupts are multiplexed with GPIO interrupts
 318          * Details are available at the DM365 ARM
 319          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 320          */
 321         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 322         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 323         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 324         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 325 }
 326
 327 static void dm365evm_mmc_configure(void)
 328 {
 329         /*
 330          * MMC/SD pins are multiplexed with GPIO and EMIF
 331          * Further details are available at the DM365 ARM
 332          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 333          */
 334         davinci_cfg_reg(DM365_SD1_CLK);
 335         davinci_cfg_reg(DM365_SD1_CMD);
 336         davinci_cfg_reg(DM365_SD1_DATA3);
 337         davinci_cfg_reg(DM365_SD1_DATA2);
 338         davinci_cfg_reg(DM365_SD1_DATA1);
 339         davinci_cfg_reg(DM365_SD1_DATA0);
 340 }
 341
 342 static struct tvp514x_platform_data tvp5146_pdata = {
 343         .clk_polarity = 0,
 344         .hs_polarity = 1,
 345         .vs_polarity = 1
 346 };
 347
 348 #define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
 349 /* Inputs available at the TVP5146 */
 350 static struct v4l2_input tvp5146_inputs[] = {
 351         {
 352                 .index = 0,
 353                 .name = "Composite",
 354                 .type = V4L2_INPUT_TYPE_CAMERA,
 355                 .std = TVP514X_STD_ALL,
 356         },
 357         {
 358                 .index = 1,
 359                 .name = "S-Video",
 360                 .type = V4L2_INPUT_TYPE_CAMERA,
 361                 .std = TVP514X_STD_ALL,
 362         },
 363 };
 364
 365 /*
 366  * this is the route info for connecting each input to decoder
 367  * ouput that goes to vpfe. There is a one to one correspondence
 368  * with tvp5146_inputs
 369  */
 370 static struct vpfe_route tvp5146_routes[] = {
 371         {
 372                 .input = INPUT_CVBS_VI2B,
 373                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 374         },
 375 {
 376                 .input = INPUT_SVIDEO_VI2C_VI1C,
 377                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 378         },
 379 };
 380
 381 static struct vpfe_subdev_info vpfe_sub_devs[] = {
 382         {
 383                 .name = "tvp5146",
 384                 .grp_id = 0,
 385                 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
 386                 .inputs = tvp5146_inputs,
 387                 .routes = tvp5146_routes,
 388                 .can_route = 1,
 389                 .ccdc_if_params = {
 390                         .if_type = VPFE_BT656,
 391                         .hdpol = VPFE_PINPOL_POSITIVE,
 392                         .vdpol = VPFE_PINPOL_POSITIVE,
 393                 },
 394                 .board_info = {
 395                         I2C_BOARD_INFO("tvp5146", 0x5d),
 396                         .platform_data = &tvp5146_pdata,
 397                 },
 398         },
 399 };
 400
 401 static struct vpfe_config vpfe_cfg = {
 402         .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
 403         .sub_devs = vpfe_sub_devs,
 404         .i2c_adapter_id = 1,
 405         .card_name = "DM365 EVM",
 406         .ccdc = "ISIF",
 407 };
 408
 409 /* venc standards timings */
 410 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
 411         {
 412                 .name           = "ntsc",
 413                 .timings_type   = VPBE_ENC_STD,
 414                 .std_id         = V4L2_STD_NTSC,
 415                 .interlaced     = 1,
 416                 .xres           = 720,
 417                 .yres           = 480,
 418                 .aspect         = {11, 10},
 419                 .fps            = {30000, 1001},
 420                 .left_margin    = 0x79,
 421                 .upper_margin   = 0x10,
 422         },
 423         {
 424                 .name           = "pal",
 425                 .timings_type   = VPBE_ENC_STD,
 426                 .std_id         = V4L2_STD_PAL,
 427                 .interlaced     = 1,
 428                 .xres           = 720,
 429                 .yres           = 576,
 430                 .aspect         = {54, 59},
 431                 .fps            = {25, 1},
 432                 .left_margin    = 0x7E,
 433                 .upper_margin   = 0x16,
 434         },
 435 };
 436
 437 /* venc dv timings */
 438 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
 439         {
 440                 .name           = "480p59_94",
 441                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 442                 .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
 443                 .interlaced     = 0,
 444                 .xres           = 720,
 445                 .yres           = 480,
 446                 .aspect         = {1, 1},
 447                 .fps            = {5994, 100},
 448                 .left_margin    = 0x8F,
 449                 .upper_margin   = 0x2D,
 450         },
 451         {
 452                 .name           = "576p50",
 453                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 454                 .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
 455                 .interlaced     = 0,
 456                 .xres           = 720,
 457                 .yres           = 576,
 458                 .aspect         = {1, 1},
 459                 .fps            = {50, 1},
 460                 .left_margin    = 0x8C,
 461                 .upper_margin   = 0x36,
 462         },
 463         {
 464                 .name           = "720p60",
 465                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 466                 .dv_timings     = V4L2_DV_BT_CEA_1280X720P60,
 467                 .interlaced     = 0,
 468                 .xres           = 1280,
 469                 .yres           = 720,
 470                 .aspect         = {1, 1},
 471                 .fps            = {60, 1},
 472                 .left_margin    = 0x117,
 473                 .right_margin   = 70,
 474                 .upper_margin   = 38,
 475                 .lower_margin   = 3,
 476                 .hsync_len      = 80,
 477                 .vsync_len      = 5,
 478         },
 479         {
 480                 .name           = "1080i60",
 481                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 482                 .dv_timings     = V4L2_DV_BT_CEA_1920X1080I60,
 483                 .interlaced     = 1,
 484                 .xres           = 1920,
 485                 .yres           = 1080,
 486                 .aspect         = {1, 1},
 487                 .fps            = {30, 1},
 488                 .left_margin    = 0xc9,
 489                 .right_margin   = 80,
 490                 .upper_margin   = 30,
 491                 .lower_margin   = 3,
 492                 .hsync_len      = 88,
 493                 .vsync_len      = 5,
 494         },
 495 };
 496
 497 #define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
 498
 499 /*
 500  * The outputs available from VPBE + ecnoders. Keep the
 501  * the order same as that of encoders. First those from venc followed by that
 502  * from encoders. Index in the output refers to index on a particular
 503  * encoder.Driver uses this index to pass it to encoder when it supports more
 504  * than one output. Application uses index of the array to set an output.
 505  */
 506 static struct vpbe_output dm365evm_vpbe_outputs[] = {
 507         {
 508                 .output         = {
 509                         .index          = 0,
 510                         .name           = "Composite",
 511                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
 512                         .std            = VENC_STD_ALL,
 513                         .capabilities   = V4L2_OUT_CAP_STD,
 514                 },
 515                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 516                 .default_mode   = "ntsc",
 517                 .num_modes      = ARRAY_SIZE(dm365evm_enc_std_timing),
 518                 .modes          = dm365evm_enc_std_timing,
 519                 .if_params      = MEDIA_BUS_FMT_FIXED,
 520         },
 521         {
 522                 .output         = {
 523                         .index          = 1,
 524                         .name           = "Component",
 525                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
 526                         .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
 527                 },
 528                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 529                 .default_mode   = "480p59_94",
 530                 .num_modes      = ARRAY_SIZE(dm365evm_enc_preset_timing),
 531                 .modes          = dm365evm_enc_preset_timing,
 532                 .if_params      = MEDIA_BUS_FMT_FIXED,
 533         },
 534 };
 535
 536 /*
 537  * Amplifiers on the board
 538  */
 539 static struct ths7303_platform_data ths7303_pdata = {
 540         .ch_1 = 3,
 541         .ch_2 = 3,
 542         .ch_3 = 3,
 543 };
 544
 545 static struct amp_config_info vpbe_amp = {
 546         .module_name    = "ths7303",
 547         .is_i2c         = 1,
 548         .board_info     = {
 549                 I2C_BOARD_INFO("ths7303", 0x2c),
 550                 .platform_data = &ths7303_pdata,
 551         }
 552 };
 553
 554 static struct vpbe_config dm365evm_display_cfg = {
 555         .module_name    = "dm365-vpbe-display",
 556         .i2c_adapter_id = 1,
 557         .amp            = &vpbe_amp,
 558         .osd            = {
 559                 .module_name    = DM365_VPBE_OSD_SUBDEV_NAME,
 560         },
 561         .venc           = {
 562                 .module_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 563         },
 564         .num_outputs    = ARRAY_SIZE(dm365evm_vpbe_outputs),
 565         .outputs        = dm365evm_vpbe_outputs,
 566 };
 567
 568 static void __init evm_init_i2c(void)
 569 {
 570         davinci_init_i2c(&i2c_pdata);
 571         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 572 }
 573
 574 static inline int have_leds(void)
 575 {
 576 #ifdef CONFIG_LEDS_CLASS
 577         return 1;
 578 #else
 579         return 0;
 580 #endif
 581 }
 582
 583 struct cpld_led {
 584         struct led_classdev     cdev;
 585         u8                      mask;
 586 };
 587
 588 static const struct {
 589         const char *name;
 590         const char *trigger;
 591 } cpld_leds[] = {
 592         { "dm365evm::ds2", },
 593         { "dm365evm::ds3", },
 594         { "dm365evm::ds4", },
 595         { "dm365evm::ds5", },
 596         { "dm365evm::ds6", "nand-disk", },
 597         { "dm365evm::ds7", "mmc1", },
 598         { "dm365evm::ds8", "mmc0", },
 599         { "dm365evm::ds9", "heartbeat", },
 600 };
 601
 602 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 603 {
 604         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 605         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 606
 607         if (b != LED_OFF)
 608                 reg &= ~led->mask;
 609         else
 610                 reg |= led->mask;
 611         __raw_writeb(reg, cpld + CPLD_LEDS);
 612 }
 613
 614 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 615 {
 616         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 617         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 618
 619         return (reg & led->mask) ? LED_OFF : LED_FULL;
 620 }
 621
 622 static int __init cpld_leds_init(void)
 623 {
 624         int     i;
 625
 626         if (!have_leds() ||  !cpld)
 627                 return 0;
 628
 629         /* setup LEDs */
 630         __raw_writeb(0xff, cpld + CPLD_LEDS);
 631         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 632                 struct cpld_led *led;
 633
 634                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 635                 if (!led)
 636                         break;
 637
 638                 led->cdev.name = cpld_leds[i].name;
 639                 led->cdev.brightness_set = cpld_led_set;
 640                 led->cdev.brightness_get = cpld_led_get;
 641                 led->cdev.default_trigger = cpld_leds[i].trigger;
 642                 led->mask = BIT(i);
 643
 644                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 645                         kfree(led);
 646                         break;
 647                 }
 648         }
 649
 650         return 0;
 651 }
 652 /* run after subsys_initcall() for LEDs */
 653 fs_initcall(cpld_leds_init);
 654
 655
 656 static void __init evm_init_cpld(void)
 657 {
 658         u8 mux, resets;
 659         const char *label;
 660         struct clk *aemif_clk;
 661         int rc;
 662
 663         /* Make sure we can configure the CPLD through CS1.  Then
 664          * leave it on for later access to MMC and LED registers.
 665          */
 666         aemif_clk = clk_get(NULL, "aemif");
 667         if (IS_ERR(aemif_clk))
 668                 return;
 669         clk_prepare_enable(aemif_clk);
 670
 671         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 672                         "cpld") == NULL)
 673                 goto fail;
 674         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 675         if (!cpld) {
 676                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 677                                 SECTION_SIZE);
 678 fail:
 679                 pr_err("ERROR: can't map CPLD\n");
 680                 clk_disable_unprepare(aemif_clk);
 681                 return;
 682         }
 683
 684         /* External muxing for some signals */
 685         mux = 0;
 686
 687         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 688          * NOTE:  SW4 bus width setting must match!
 689          */
 690         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 691                 /* external keypad mux */
 692                 mux |= BIT(7);
 693
 694                 rc = platform_device_register(&davinci_aemif_device);
 695                 if (rc)
 696                         pr_warn("%s(): error registering the aemif device: %d\n",
 697                                 __func__, rc);
 698         } else {
 699                 /* no OneNAND support yet */
 700         }
 701
 702         /* Leave external chips in reset when unused. */
 703         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 704
 705         /* Static video input config with SN74CBT16214 1-of-3 mux:
 706          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 707          *  - port b2 == imager (mux lowbits == 2 or 7)
 708          *  - port b3 == tvp5146 (mux lowbits == 5)
 709          *
 710          * Runtime switching could work too, with limitations.
 711          */
 712         if (have_imager()) {
 713                 label = "HD imager";
 714                 mux |= 2;
 715
 716                 /* externally mux MMC1/ENET/AIC33 to imager */
 717                 mux |= BIT(6) | BIT(5) | BIT(3);
 718         } else {
 719                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 720
 721                 /* we can use MMC1 ... */
 722                 dm365evm_mmc_configure();
 723                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 724
 725                 /* ... and ENET ... */
 726                 dm365evm_emac_configure();
 727                 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
 728                 resets &= ~BIT(3);
 729
 730                 /* ... and AIC33 */
 731                 resets &= ~BIT(1);
 732
 733                 if (have_tvp7002()) {
 734                         mux |= 1;
 735                         resets &= ~BIT(2);
 736                         label = "tvp7002 HD";
 737                 } else {
 738                         /* default to tvp5146 */
 739                         mux |= 5;
 740                         resets &= ~BIT(0);
 741                         label = "tvp5146 SD";
 742                 }
 743         }
 744         __raw_writeb(mux, cpld + CPLD_MUX);
 745         __raw_writeb(resets, cpld + CPLD_RESETS);
 746         pr_info("EVM: %s video input\n", label);
 747
 748         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 749 }
 750
 751 static void __init dm365_evm_map_io(void)
 752 {
 753         dm365_init();
 754 }
 755
 756 static struct spi_eeprom at25640 = {
 757         .byte_len       = SZ_64K / 8,
 758         .name           = "at25640",
 759         .page_size      = 32,
 760         .flags          = EE_ADDR2,
 761 };
 762
 763 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
 764         {
 765                 .modalias       = "at25",
 766                 .platform_data  = &at25640,
 767                 .max_speed_hz   = 10 * 1000 * 1000,
 768                 .bus_num        = 0,
 769                 .chip_select    = 0,
 770                 .mode           = SPI_MODE_0,
 771         },
 772 };
 773
 774 static __init void dm365_evm_init(void)
 775 {
 776         int ret;
 777
 778         dm365_register_clocks();
 779
 780         ret = dm365_gpio_register();
 781         if (ret)
 782                 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
 783
 784         evm_init_i2c();
 785         davinci_serial_init(dm365_serial_device);
 786
 787         dm365evm_emac_configure();
 788         dm365evm_mmc_configure();
 789
 790         davinci_setup_mmc(0, &dm365evm_mmc_config);
 791
 792         dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
 793
 794         /* maybe setup mmc1/etc ... _after_ mmc0 */
 795         evm_init_cpld();
 796
 797 #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
 798         dm365_init_asp();
 799 #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
 800         dm365_init_vc();
 801 #endif
 802         dm365_init_rtc();
 803         dm365_init_ks(&dm365evm_ks_data);
 804
 805         dm365_init_spi0(BIT(0), dm365_evm_spi_info,
 806                         ARRAY_SIZE(dm365_evm_spi_info));
 807 }
 808
 809 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 810         .atag_offset    = 0x100,
 811         .map_io         = dm365_evm_map_io,
 812         .init_irq       = davinci_irq_init,
 813         .init_time      = dm365_init_time,
 814         .init_machine   = dm365_evm_init,
 815         .init_late      = davinci_init_late,
 816         .dma_zone_size  = SZ_128M,
 817 MACHINE_END
 818