arch/arm/mach-cns3xxx/core.c

   1 /*
   2  * Copyright 1999 - 2003 ARM Limited
   3  * Copyright 2000 Deep Blue Solutions Ltd
   4  * Copyright 2008 Cavium Networks
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, Version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/clockchips.h>
  14 #include <linux/io.h>
  15 #include <linux/irqchip/arm-gic.h>
  16 #include <asm/mach/map.h>
  17 #include <asm/mach/time.h>
  18 #include <asm/mach/irq.h>
  19 #include <asm/hardware/cache-l2x0.h>
  20 #include <mach/cns3xxx.h>
  21 #include "core.h"
  22
  23 static struct map_desc cns3xxx_io_desc[] __initdata = {
  24         {
  25                 .virtual        = CNS3XXX_TC11MP_TWD_BASE_VIRT,
  26                 .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
  27                 .length         = SZ_4K,
  28                 .type           = MT_DEVICE,
  29         }, {
  30                 .virtual        = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
  31                 .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
  32                 .length         = SZ_4K,
  33                 .type           = MT_DEVICE,
  34         }, {
  35                 .virtual        = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
  36                 .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
  37                 .length         = SZ_4K,
  38                 .type           = MT_DEVICE,
  39         }, {
  40                 .virtual        = CNS3XXX_TIMER1_2_3_BASE_VIRT,
  41                 .pfn            = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
  42                 .length         = SZ_4K,
  43                 .type           = MT_DEVICE,
  44         }, {
  45                 .virtual        = CNS3XXX_GPIOA_BASE_VIRT,
  46                 .pfn            = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
  47                 .length         = SZ_4K,
  48                 .type           = MT_DEVICE,
  49         }, {
  50                 .virtual        = CNS3XXX_GPIOB_BASE_VIRT,
  51                 .pfn            = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
  52                 .length         = SZ_4K,
  53                 .type           = MT_DEVICE,
  54         }, {
  55                 .virtual        = CNS3XXX_MISC_BASE_VIRT,
  56                 .pfn            = __phys_to_pfn(CNS3XXX_MISC_BASE),
  57                 .length         = SZ_4K,
  58                 .type           = MT_DEVICE,
  59         }, {
  60                 .virtual        = CNS3XXX_PM_BASE_VIRT,
  61                 .pfn            = __phys_to_pfn(CNS3XXX_PM_BASE),
  62                 .length         = SZ_4K,
  63                 .type           = MT_DEVICE,
  64         },
  65 };
  66
  67 void __init cns3xxx_map_io(void)
  68 {
  69         iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
  70 }
  71
  72 /* used by entry-macro.S */
  73 void __init cns3xxx_init_irq(void)
  74 {
  75         gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
  76                  IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
  77 }
  78
  79 void cns3xxx_power_off(void)
  80 {
  81         u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
  82         u32 clkctrl;
  83
  84         printk(KERN_INFO "powering system down...\n");
  85
  86         clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
  87         clkctrl &= 0xfffff1ff;
  88         clkctrl |= (0x5 << 9);          /* Hibernate */
  89         writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
  90
  91 }
  92
  93 /*
  94  * Timer
  95  */
  96 static void __iomem *cns3xxx_tmr1;
  97
  98 static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
  99                                    struct clock_event_device *clk)
 100 {
 101         unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 102         int pclk = cns3xxx_cpu_clock() / 8;
 103         int reload;
 104
 105         switch (mode) {
 106         case CLOCK_EVT_MODE_PERIODIC:
 107                 reload = pclk * 20 / (3 * HZ) * 0x25000;
 108                 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
 109                 ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
 110                 break;
 111         case CLOCK_EVT_MODE_ONESHOT:
 112                 /* period set, and timer enabled in 'next_event' hook */
 113                 ctrl |= (1 << 2) | (1 << 9);
 114                 break;
 115         case CLOCK_EVT_MODE_UNUSED:
 116         case CLOCK_EVT_MODE_SHUTDOWN:
 117         default:
 118                 ctrl = 0;
 119         }
 120
 121         writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 122 }
 123
 124 static int cns3xxx_timer_set_next_event(unsigned long evt,
 125                                         struct clock_event_device *unused)
 126 {
 127         unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 128
 129         writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
 130         writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 131
 132         return 0;
 133 }
 134
 135 static struct clock_event_device cns3xxx_tmr1_clockevent = {
 136         .name           = "cns3xxx timer1",
 137         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 138         .set_mode       = cns3xxx_timer_set_mode,
 139         .set_next_event = cns3xxx_timer_set_next_event,
 140         .rating         = 350,
 141         .cpumask        = cpu_all_mask,
 142 };
 143
 144 static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
 145 {
 146         cns3xxx_tmr1_clockevent.irq = timer_irq;
 147         clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
 148                                         (cns3xxx_cpu_clock() >> 3) * 1000000,
 149                                         0xf, 0xffffffff);
 150 }
 151
 152 /*
 153  * IRQ handler for the timer
 154  */
 155 static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
 156 {
 157         struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
 158         u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
 159         u32 val;
 160
 161         /* Clear the interrupt */
 162         val = readl(stat);
 163         writel(val & ~(1 << 2), stat);
 164
 165         evt->event_handler(evt);
 166
 167         return IRQ_HANDLED;
 168 }
 169
 170 static struct irqaction cns3xxx_timer_irq = {
 171         .name           = "timer",
 172         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 173         .handler        = cns3xxx_timer_interrupt,
 174 };
 175
 176 /*
 177  * Set up the clock source and clock events devices
 178  */
 179 static void __init __cns3xxx_timer_init(unsigned int timer_irq)
 180 {
 181         u32 val;
 182         u32 irq_mask;
 183
 184         /*
 185          * Initialise to a known state (all timers off)
 186          */
 187
 188         /* disable timer1 and timer2 */
 189         writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 190         /* stop free running timer3 */
 191         writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
 192
 193         /* timer1 */
 194         writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
 195         writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
 196
 197         writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
 198         writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
 199
 200         /* mask irq, non-mask timer1 overflow */
 201         irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
 202         irq_mask &= ~(1 << 2);
 203         irq_mask |= 0x03;
 204         writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
 205
 206         /* down counter */
 207         val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 208         val |= (1 << 9);
 209         writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 210
 211         /* timer2 */
 212         writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
 213         writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
 214
 215         /* mask irq */
 216         irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
 217         irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
 218         writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
 219
 220         /* down counter */
 221         val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 222         val |= (1 << 10);
 223         writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
 224
 225         /* Make irqs happen for the system timer */
 226         setup_irq(timer_irq, &cns3xxx_timer_irq);
 227
 228         cns3xxx_clockevents_init(timer_irq);
 229 }
 230
 231 void __init cns3xxx_timer_init(void)
 232 {
 233         cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
 234
 235         __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
 236 }
 237
 238 #ifdef CONFIG_CACHE_L2X0
 239
 240 void __init cns3xxx_l2x0_init(void)
 241 {
 242         void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
 243         u32 val;
 244
 245         if (WARN_ON(!base))
 246                 return;
 247
 248         /*
 249          * Tag RAM Control register
 250          *
 251          * bit[10:8]    - 1 cycle of write accesses latency
 252          * bit[6:4]     - 1 cycle of read accesses latency
 253          * bit[3:0]     - 1 cycle of setup latency
 254          *
 255          * 1 cycle of latency for setup, read and write accesses
 256          */
 257         val = readl(base + L2X0_TAG_LATENCY_CTRL);
 258         val &= 0xfffff888;
 259         writel(val, base + L2X0_TAG_LATENCY_CTRL);
 260
 261         /*
 262          * Data RAM Control register
 263          *
 264          * bit[10:8]    - 1 cycles of write accesses latency
 265          * bit[6:4]     - 1 cycles of read accesses latency
 266          * bit[3:0]     - 1 cycle of setup latency
 267          *
 268          * 1 cycle of latency for setup, read and write accesses
 269          */
 270         val = readl(base + L2X0_DATA_LATENCY_CTRL);
 271         val &= 0xfffff888;
 272         writel(val, base + L2X0_DATA_LATENCY_CTRL);
 273
 274         /* 32 KiB, 8-way, parity disable */
 275         l2x0_init(base, 0x00540000, 0xfe000fff);
 276 }
 277
 278 #endif /* CONFIG_CACHE_L2X0 */