2 * Cavium Networks CNS3420 Validation Board
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
11 * This file is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License, Version 2, as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/compiler.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
23 #include <linux/platform_device.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/usb/ehci_pdriver.h>
28 #include <linux/usb/ohci_pdriver.h>
29 #include <asm/setup.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware/gic.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/time.h>
35 #include <mach/cns3xxx.h>
36 #include <mach/irqs.h>
44 static struct mtd_partition cns3420_nor_partitions[] = {
49 .mask_flags = MTD_WRITEABLE,
53 .offset = MTDPART_OFS_APPEND,
57 .offset = MTDPART_OFS_APPEND,
59 .name = "filesystem2",
61 .offset = MTDPART_OFS_APPEND,
64 .size = MTDPART_SIZ_FULL,
65 .offset = MTDPART_OFS_APPEND,
69 static struct physmap_flash_data cns3420_nor_pdata = {
71 .parts = cns3420_nor_partitions,
72 .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
75 static struct resource cns3420_nor_res = {
76 .start = CNS3XXX_FLASH_BASE,
77 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
78 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
81 static struct platform_device cns3420_nor_pdev = {
82 .name = "physmap-flash",
84 .resource = &cns3420_nor_res,
87 .platform_data = &cns3420_nor_pdata,
94 static void __init cns3420_early_serial_setup(void)
96 #ifdef CONFIG_SERIAL_8250_CONSOLE
97 static struct uart_port cns3420_serial_port = {
98 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
99 .mapbase = CNS3XXX_UART0_BASE,
100 .irq = IRQ_CNS3XXX_UART0,
102 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
110 early_serial_setup(&cns3420_serial_port);
117 static struct resource cns3xxx_usb_ehci_resources[] = {
119 .start = CNS3XXX_USB_BASE,
120 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
121 .flags = IORESOURCE_MEM,
124 .start = IRQ_CNS3XXX_USB_EHCI,
125 .flags = IORESOURCE_IRQ,
129 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
131 static int csn3xxx_usb_power_on(struct platform_device *pdev)
134 * EHCI and OHCI share the same clock and power,
135 * resetting twice would cause the 1st controller been reset.
136 * Therefore only do power up at the first up device, and
137 * power down at the last down device.
139 * Set USB AHB INCR length to 16
141 if (atomic_inc_return(&usb_pwr_ref) == 1) {
142 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
143 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
144 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
145 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
146 MISC_CHIP_CONFIG_REG);
152 static void csn3xxx_usb_power_off(struct platform_device *pdev)
155 * EHCI and OHCI share the same clock and power,
156 * resetting twice would cause the 1st controller been reset.
157 * Therefore only do power up at the first up device, and
158 * power down at the last down device.
160 if (atomic_dec_return(&usb_pwr_ref) == 0)
161 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
164 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
165 .power_on = csn3xxx_usb_power_on,
166 .power_off = csn3xxx_usb_power_off,
169 static struct platform_device cns3xxx_usb_ehci_device = {
170 .name = "ehci-platform",
171 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
172 .resource = cns3xxx_usb_ehci_resources,
174 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
175 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .platform_data = &cns3xxx_usb_ehci_pdata,
180 static struct resource cns3xxx_usb_ohci_resources[] = {
182 .start = CNS3XXX_USB_OHCI_BASE,
183 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
184 .flags = IORESOURCE_MEM,
187 .start = IRQ_CNS3XXX_USB_OHCI,
188 .flags = IORESOURCE_IRQ,
192 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
194 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
196 .power_on = csn3xxx_usb_power_on,
197 .power_off = csn3xxx_usb_power_off,
200 static struct platform_device cns3xxx_usb_ohci_device = {
201 .name = "ohci-platform",
202 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
203 .resource = cns3xxx_usb_ohci_resources,
205 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
206 .coherent_dma_mask = DMA_BIT_MASK(32),
207 .platform_data = &cns3xxx_usb_ohci_pdata,
214 static struct platform_device *cns3420_pdevs[] __initdata = {
216 &cns3xxx_usb_ehci_device,
217 &cns3xxx_usb_ohci_device,
220 static void __init cns3420_init(void)
224 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
227 cns3xxx_sdhci_init();
229 pm_power_off = cns3xxx_power_off;
232 static struct map_desc cns3420_io_desc[] __initdata = {
234 .virtual = CNS3XXX_UART0_BASE_VIRT,
235 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
241 static void __init cns3420_map_io(void)
244 iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
246 cns3420_early_serial_setup();
249 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
250 .atag_offset = 0x100,
251 .map_io = cns3420_map_io,
252 .init_irq = cns3xxx_init_irq,
253 .timer = &cns3xxx_timer,
254 .handle_irq = gic_handle_irq,
255 .init_machine = cns3420_init,
256 .restart = cns3xxx_restart,