arch/arm/mach-clps711x/board-autcpu12.c

   1 /*
   2  *  linux/arch/arm/mach-clps711x/autcpu12.c
   3  *
   4  * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/types.h>
  23 #include <linux/string.h>
  24 #include <linux/mm.h>
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <linux/ioport.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <linux/mtd/nand-gpio.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/basic_mmio_gpio.h>
  33
  34 #include <mach/hardware.h>
  35 #include <asm/sizes.h>
  36 #include <asm/setup.h>
  37 #include <asm/mach-types.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41
  42 #include <asm/mach/map.h>
  43 #include <mach/autcpu12.h>
  44
  45 #include "common.h"
  46
  47 #define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
  48 #define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
  49
  50 #define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
  51 #define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
  52
  53 #define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
  54 #define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
  55 #define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
  56 #define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
  57 #define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
  58
  59 static struct resource autcpu12_cs8900_resource[] __initdata = {
  60         DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
  61         DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
  62 };
  63
  64 static struct resource autcpu12_nvram_resource[] __initdata = {
  65         DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
  66 };
  67
  68 static struct platform_device autcpu12_nvram_pdev __initdata = {
  69         .name           = "autcpu12_nvram",
  70         .id             = -1,
  71         .resource       = autcpu12_nvram_resource,
  72         .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
  73 };
  74
  75 static struct resource autcpu12_nand_resource[] __initdata = {
  76         DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
  77 };
  78
  79 static struct mtd_partition autcpu12_nand_parts[] __initdata = {
  80         {
  81                 .name   = "Flash partition 1",
  82                 .offset = 0,
  83                 .size   = SZ_8M,
  84         },
  85         {
  86                 .name   = "Flash partition 2",
  87                 .offset = MTDPART_OFS_APPEND,
  88                 .size   = MTDPART_SIZ_FULL,
  89         },
  90 };
  91
  92 static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
  93                                          size_t sz)
  94 {
  95         switch (sz) {
  96         case SZ_16M:
  97         case SZ_32M:
  98                 break;
  99         case SZ_64M:
 100         case SZ_128M:
 101                 pdata->parts[0].size = SZ_16M;
 102                 break;
 103         default:
 104                 pr_warn("Unsupported SmartMedia device size %u\n", sz);
 105                 break;
 106         }
 107 }
 108
 109 static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
 110         .gpio_rdy       = AUTCPU12_SMC_RDY,
 111         .gpio_nce       = AUTCPU12_SMC_NCE,
 112         .gpio_ale       = AUTCPU12_SMC_ALE,
 113         .gpio_cle       = AUTCPU12_SMC_CLE,
 114         .gpio_nwp       = -1,
 115         .chip_delay     = 20,
 116         .parts          = autcpu12_nand_parts,
 117         .num_parts      = ARRAY_SIZE(autcpu12_nand_parts),
 118         .adjust_parts   = autcpu12_adjust_parts,
 119 };
 120
 121 static struct platform_device autcpu12_nand_pdev __initdata = {
 122         .name           = "gpio-nand",
 123         .id             = -1,
 124         .resource       = autcpu12_nand_resource,
 125         .num_resources  = ARRAY_SIZE(autcpu12_nand_resource),
 126         .dev            = {
 127                 .platform_data = &autcpu12_nand_pdata,
 128         },
 129 };
 130
 131 static struct resource autcpu12_mmgpio_resource[] __initdata = {
 132         DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
 133 };
 134
 135 static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
 136         .base   = AUTCPU12_MMGPIO_BASE,
 137         .ngpio  = 8,
 138 };
 139
 140 static struct platform_device autcpu12_mmgpio_pdev __initdata = {
 141         .name           = "basic-mmio-gpio",
 142         .id             = -1,
 143         .resource       = autcpu12_mmgpio_resource,
 144         .num_resources  = ARRAY_SIZE(autcpu12_mmgpio_resource),
 145         .dev            = {
 146                 .platform_data = &autcpu12_mmgpio_pdata,
 147         },
 148 };
 149
 150 static void __init autcpu12_init(void)
 151 {
 152         platform_device_register_simple("video-clps711x", 0, NULL, 0);
 153         platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
 154                                         ARRAY_SIZE(autcpu12_cs8900_resource));
 155         platform_device_register(&autcpu12_mmgpio_pdev);
 156         platform_device_register(&autcpu12_nvram_pdev);
 157 }
 158
 159 static void __init autcpu12_init_late(void)
 160 {
 161         if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
 162                 /* We are need both drivers to handle NAND */
 163                 platform_device_register(&autcpu12_nand_pdev);
 164         }
 165 }
 166
 167 MACHINE_START(AUTCPU12, "autronix autcpu12")
 168         /* Maintainer: Thomas Gleixner */
 169         .atag_offset    = 0x20000,
 170         .nr_irqs        = CLPS711X_NR_IRQS,
 171         .map_io         = clps711x_map_io,
 172         .init_irq       = clps711x_init_irq,
 173         .timer          = &clps711x_timer,
 174         .init_machine   = autcpu12_init,
 175         .init_late      = autcpu12_init_late,
 176         .handle_irq     = clps711x_handle_irq,
 177         .restart        = clps711x_restart,
 178 MACHINE_END
 179