arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/of_address.h>
  27 #include <linux/clk/at91_pmc.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/cpu.h>
  31
  32 #include <asm/proc-fns.h>
  33
  34 #include "clock.h"
  35 #include "generic.h"
  36
  37 void __iomem *at91_pmc_base;
  38 EXPORT_SYMBOL_GPL(at91_pmc_base);
  39
  40 /*
  41  * There's a lot more which can be done with clocks, including cpufreq
  42  * integration, slow clock mode support (for system suspend), letting
  43  * PLLB be used at other rates (on boards that don't need USB), etc.
  44  */
  45
  46 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  47 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  48 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  49 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  50
  51
  52 /*
  53  * Chips have some kind of clocks : group them by functionality
  54  */
  55 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
  56                                 || cpu_is_at91sam9g45() \
  57                                 || cpu_is_at91sam9x5() \
  58                                 || cpu_is_sama5d3())
  59
  60 #define cpu_has_1056M_plla()    (cpu_is_sama5d3())
  61
  62 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
  63                                 || cpu_is_at91sam9g45() \
  64                                 || cpu_is_at91sam9x5() \
  65                                 || cpu_is_at91sam9n12())
  66
  67 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
  68
  69 #define cpu_has_240M_plla()     (cpu_is_at91sam9261() \
  70                                 || cpu_is_at91sam9263() \
  71                                 || cpu_is_at91sam9rl())
  72
  73 #define cpu_has_210M_plla()     (cpu_is_at91sam9260())
  74
  75 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
  76                                 || cpu_is_at91sam9g45() \
  77                                 || cpu_is_at91sam9x5() \
  78                                 || cpu_is_sama5d3()))
  79
  80 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
  81                                 || cpu_is_at91sam9x5() \
  82                                 || cpu_is_sama5d3())
  83
  84 /* USB host HS & FS */
  85 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
  86
  87 /* USB device FS only */
  88 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
  89                                 || cpu_is_at91sam9g45() \
  90                                 || cpu_is_at91sam9x5() \
  91                                 || cpu_is_sama5d3()))
  92
  93 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
  94                                 || cpu_is_at91sam9x5() \
  95                                 || cpu_is_at91sam9n12() \
  96                                 || cpu_is_sama5d3())
  97
  98 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
  99                                 || cpu_is_at91sam9x5() \
 100                                 || cpu_is_at91sam9n12() \
 101                                 || cpu_is_sama5d3())
 102
 103 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
 104                                 || cpu_is_at91sam9n12() \
 105                                 || cpu_is_sama5d3())
 106
 107 static LIST_HEAD(clocks);
 108 static DEFINE_SPINLOCK(clk_lock);
 109
 110 static u32 at91_pllb_usb_init;
 111
 112 /*
 113  * Four primary clock sources:  two crystal oscillators (32K, main), and
 114  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
 115  * 48 MHz (unless no USB function clocks are needed).  The main clock and
 116  * both PLLs are turned off to run in "slow clock mode" (system suspend).
 117  */
 118 static struct clk clk32k = {
 119         .name           = "clk32k",
 120         .rate_hz        = AT91_SLOW_CLOCK,
 121         .users          = 1,            /* always on */
 122         .id             = 0,
 123         .type           = CLK_TYPE_PRIMARY,
 124 };
 125 static struct clk main_clk = {
 126         .name           = "main",
 127         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
 128         .id             = 1,
 129         .type           = CLK_TYPE_PRIMARY,
 130 };
 131 static struct clk plla = {
 132         .name           = "plla",
 133         .parent         = &main_clk,
 134         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
 135         .id             = 2,
 136         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 137 };
 138
 139 static void pllb_mode(struct clk *clk, int is_on)
 140 {
 141         u32     value;
 142
 143         if (is_on) {
 144                 is_on = AT91_PMC_LOCKB;
 145                 value = at91_pllb_usb_init;
 146         } else
 147                 value = 0;
 148
 149         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
 150         at91_pmc_write(AT91_CKGR_PLLBR, value);
 151
 152         do {
 153                 cpu_relax();
 154         } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 155 }
 156
 157 static struct clk pllb = {
 158         .name           = "pllb",
 159         .parent         = &main_clk,
 160         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 161         .mode           = pllb_mode,
 162         .id             = 3,
 163         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 164 };
 165
 166 static void pmc_sys_mode(struct clk *clk, int is_on)
 167 {
 168         if (is_on)
 169                 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
 170         else
 171                 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 172 }
 173
 174 static void pmc_uckr_mode(struct clk *clk, int is_on)
 175 {
 176         unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
 177
 178         if (is_on) {
 179                 is_on = AT91_PMC_LOCKU;
 180                 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
 181         } else
 182                 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 183
 184         do {
 185                 cpu_relax();
 186         } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 187 }
 188
 189 /* USB function clocks (PLLB must be 48 MHz) */
 190 static struct clk udpck = {
 191         .name           = "udpck",
 192         .parent         = &pllb,
 193         .mode           = pmc_sys_mode,
 194 };
 195 struct clk utmi_clk = {
 196         .name           = "utmi_clk",
 197         .parent         = &main_clk,
 198         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
 199         .mode           = pmc_uckr_mode,
 200         .type           = CLK_TYPE_PLL,
 201 };
 202 static struct clk uhpck = {
 203         .name           = "uhpck",
 204         /*.parent               = ... we choose parent at runtime */
 205         .mode           = pmc_sys_mode,
 206 };
 207
 208
 209 /*
 210  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 211  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 212  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 213  */
 214 struct clk mck = {
 215         .name           = "mck",
 216         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 217 };
 218
 219 static void pmc_periph_mode(struct clk *clk, int is_on)
 220 {
 221         u32 regval = 0;
 222
 223         /*
 224          * With sama5d3 devices, we are managing clock division so we have to
 225          * use the Peripheral Control Register introduced from at91sam9x5
 226          * devices.
 227          */
 228         if (cpu_is_sama5d3()) {
 229                 regval |= AT91_PMC_PCR_CMD; /* write command */
 230                 regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
 231                 regval |= AT91_PMC_PCR_DIV(clk->div);
 232                 if (is_on)
 233                         regval |= AT91_PMC_PCR_EN; /* enable clock */
 234                 at91_pmc_write(AT91_PMC_PCR, regval);
 235         } else {
 236                 if (is_on)
 237                         at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
 238                 else
 239                         at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 240         }
 241 }
 242
 243 static struct clk __init *at91_css_to_clk(unsigned long css)
 244 {
 245         switch (css) {
 246                 case AT91_PMC_CSS_SLOW:
 247                         return &clk32k;
 248                 case AT91_PMC_CSS_MAIN:
 249                         return &main_clk;
 250                 case AT91_PMC_CSS_PLLA:
 251                         return &plla;
 252                 case AT91_PMC_CSS_PLLB:
 253                         if (cpu_has_upll())
 254                                 /* CSS_PLLB == CSS_UPLL */
 255                                 return &utmi_clk;
 256                         else if (cpu_has_pllb())
 257                                 return &pllb;
 258                         break;
 259                 /* alternate PMC: can use master clock */
 260                 case AT91_PMC_CSS_MASTER:
 261                         return &mck;
 262         }
 263
 264         return NULL;
 265 }
 266
 267 static int pmc_prescaler_divider(u32 reg)
 268 {
 269         if (cpu_has_alt_prescaler()) {
 270                 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
 271         } else {
 272                 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
 273         }
 274 }
 275
 276 static void __clk_enable(struct clk *clk)
 277 {
 278         if (clk->parent)
 279                 __clk_enable(clk->parent);
 280         if (clk->users++ == 0 && clk->mode)
 281                 clk->mode(clk, 1);
 282 }
 283
 284 int clk_enable(struct clk *clk)
 285 {
 286         unsigned long   flags;
 287
 288         spin_lock_irqsave(&clk_lock, flags);
 289         __clk_enable(clk);
 290         spin_unlock_irqrestore(&clk_lock, flags);
 291         return 0;
 292 }
 293 EXPORT_SYMBOL(clk_enable);
 294
 295 static void __clk_disable(struct clk *clk)
 296 {
 297         BUG_ON(clk->users == 0);
 298         if (--clk->users == 0 && clk->mode)
 299                 clk->mode(clk, 0);
 300         if (clk->parent)
 301                 __clk_disable(clk->parent);
 302 }
 303
 304 void clk_disable(struct clk *clk)
 305 {
 306         unsigned long   flags;
 307
 308         spin_lock_irqsave(&clk_lock, flags);
 309         __clk_disable(clk);
 310         spin_unlock_irqrestore(&clk_lock, flags);
 311 }
 312 EXPORT_SYMBOL(clk_disable);
 313
 314 unsigned long clk_get_rate(struct clk *clk)
 315 {
 316         unsigned long   flags;
 317         unsigned long   rate;
 318
 319         spin_lock_irqsave(&clk_lock, flags);
 320         for (;;) {
 321                 rate = clk->rate_hz;
 322                 if (rate || !clk->parent)
 323                         break;
 324                 clk = clk->parent;
 325         }
 326         spin_unlock_irqrestore(&clk_lock, flags);
 327         return rate;
 328 }
 329 EXPORT_SYMBOL(clk_get_rate);
 330
 331 /*------------------------------------------------------------------------*/
 332
 333 /*
 334  * For now, only the programmable clocks support reparenting (MCK could
 335  * do this too, with care) or rate changing (the PLLs could do this too,
 336  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 337  * a better rate match; we don't.
 338  */
 339
 340 long clk_round_rate(struct clk *clk, unsigned long rate)
 341 {
 342         unsigned long   flags;
 343         unsigned        prescale;
 344         unsigned long   actual;
 345         unsigned long   prev = ULONG_MAX;
 346
 347         if (!clk_is_programmable(clk))
 348                 return -EINVAL;
 349         spin_lock_irqsave(&clk_lock, flags);
 350
 351         actual = clk->parent->rate_hz;
 352         for (prescale = 0; prescale < 7; prescale++) {
 353                 if (actual > rate)
 354                         prev = actual;
 355
 356                 if (actual && actual <= rate) {
 357                         if ((prev - rate) < (rate - actual)) {
 358                                 actual = prev;
 359                                 prescale--;
 360                         }
 361                         break;
 362                 }
 363                 actual >>= 1;
 364         }
 365
 366         spin_unlock_irqrestore(&clk_lock, flags);
 367         return (prescale < 7) ? actual : -ENOENT;
 368 }
 369 EXPORT_SYMBOL(clk_round_rate);
 370
 371 int clk_set_rate(struct clk *clk, unsigned long rate)
 372 {
 373         unsigned long   flags;
 374         unsigned        prescale;
 375         unsigned long   prescale_offset, css_mask;
 376         unsigned long   actual;
 377
 378         if (!clk_is_programmable(clk))
 379                 return -EINVAL;
 380         if (clk->users)
 381                 return -EBUSY;
 382
 383         if (cpu_has_alt_prescaler()) {
 384                 prescale_offset = PMC_ALT_PRES_OFFSET;
 385                 css_mask = AT91_PMC_ALT_PCKR_CSS;
 386         } else {
 387                 prescale_offset = PMC_PRES_OFFSET;
 388                 css_mask = AT91_PMC_CSS;
 389         }
 390
 391         spin_lock_irqsave(&clk_lock, flags);
 392
 393         actual = clk->parent->rate_hz;
 394         for (prescale = 0; prescale < 7; prescale++) {
 395                 if (actual && actual <= rate) {
 396                         u32     pckr;
 397
 398                         pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
 399                         pckr &= css_mask;       /* keep clock selection */
 400                         pckr |= prescale << prescale_offset;
 401                         at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
 402                         clk->rate_hz = actual;
 403                         break;
 404                 }
 405                 actual >>= 1;
 406         }
 407
 408         spin_unlock_irqrestore(&clk_lock, flags);
 409         return (prescale < 7) ? actual : -ENOENT;
 410 }
 411 EXPORT_SYMBOL(clk_set_rate);
 412
 413 struct clk *clk_get_parent(struct clk *clk)
 414 {
 415         return clk->parent;
 416 }
 417 EXPORT_SYMBOL(clk_get_parent);
 418
 419 int clk_set_parent(struct clk *clk, struct clk *parent)
 420 {
 421         unsigned long   flags;
 422
 423         if (clk->users)
 424                 return -EBUSY;
 425         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 426                 return -EINVAL;
 427
 428         if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
 429                 return -EINVAL;
 430
 431         spin_lock_irqsave(&clk_lock, flags);
 432
 433         clk->rate_hz = parent->rate_hz;
 434         clk->parent = parent;
 435         at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
 436
 437         spin_unlock_irqrestore(&clk_lock, flags);
 438         return 0;
 439 }
 440 EXPORT_SYMBOL(clk_set_parent);
 441
 442 /* establish PCK0..PCKN parentage and rate */
 443 static void __init init_programmable_clock(struct clk *clk)
 444 {
 445         struct clk      *parent;
 446         u32             pckr;
 447         unsigned int    css_mask;
 448
 449         if (cpu_has_alt_prescaler())
 450                 css_mask = AT91_PMC_ALT_PCKR_CSS;
 451         else
 452                 css_mask = AT91_PMC_CSS;
 453
 454         pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
 455         parent = at91_css_to_clk(pckr & css_mask);
 456         clk->parent = parent;
 457         clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
 458 }
 459
 460 /*------------------------------------------------------------------------*/
 461
 462 #ifdef CONFIG_DEBUG_FS
 463
 464 static int at91_clk_show(struct seq_file *s, void *unused)
 465 {
 466         u32             scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
 467         struct clk      *clk;
 468
 469         scsr = at91_pmc_read(AT91_PMC_SCSR);
 470         pcsr = at91_pmc_read(AT91_PMC_PCSR);
 471         if (cpu_is_sama5d3())
 472                 pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
 473         sr = at91_pmc_read(AT91_PMC_SR);
 474         seq_printf(s, "SCSR = %8x\n", scsr);
 475         seq_printf(s, "PCSR = %8x\n", pcsr);
 476         if (cpu_is_sama5d3())
 477                 seq_printf(s, "PCSR1 = %8x\n", pcsr1);
 478         seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
 479         seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
 480         seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
 481         if (cpu_has_pllb())
 482                 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
 483         if (cpu_has_utmi()) {
 484                 uckr = at91_pmc_read(AT91_CKGR_UCKR);
 485                 seq_printf(s, "UCKR = %8x\n", uckr);
 486         }
 487         seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
 488         if (cpu_has_upll() || cpu_is_at91sam9n12())
 489                 seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
 490         seq_printf(s, "SR   = %8x\n", sr);
 491
 492         seq_printf(s, "\n");
 493
 494         list_for_each_entry(clk, &clocks, node) {
 495                 char    *state;
 496
 497                 if (clk->mode == pmc_sys_mode) {
 498                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 499                 } else if (clk->mode == pmc_periph_mode) {
 500                         if (cpu_is_sama5d3()) {
 501                                 u32 pmc_mask = 1 << (clk->pid % 32);
 502
 503                                 if (clk->pid > 31)
 504                                         state = (pcsr1 & pmc_mask) ? "on" : "off";
 505                                 else
 506                                         state = (pcsr & pmc_mask) ? "on" : "off";
 507                         } else {
 508                                 state = (pcsr & clk->pmc_mask) ? "on" : "off";
 509                         }
 510                 } else if (clk->mode == pmc_uckr_mode) {
 511                         state = (uckr & clk->pmc_mask) ? "on" : "off";
 512                 } else if (clk->pmc_mask) {
 513                         state = (sr & clk->pmc_mask) ? "on" : "off";
 514                 } else if (clk == &clk32k || clk == &main_clk) {
 515                         state = "on";
 516                 } else {
 517                         state = "";
 518                 }
 519
 520                 seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
 521                         clk->name, clk->users, state, clk_get_rate(clk),
 522                         clk->parent ? clk->parent->name : "");
 523         }
 524         return 0;
 525 }
 526
 527 static int at91_clk_open(struct inode *inode, struct file *file)
 528 {
 529         return single_open(file, at91_clk_show, NULL);
 530 }
 531
 532 static const struct file_operations at91_clk_operations = {
 533         .open           = at91_clk_open,
 534         .read           = seq_read,
 535         .llseek         = seq_lseek,
 536         .release        = single_release,
 537 };
 538
 539 static int __init at91_clk_debugfs_init(void)
 540 {
 541         /* /sys/kernel/debug/at91_clk */
 542         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 543
 544         return 0;
 545 }
 546 postcore_initcall(at91_clk_debugfs_init);
 547
 548 #endif
 549
 550 /*------------------------------------------------------------------------*/
 551
 552 /* Register a new clock */
 553 static void __init at91_clk_add(struct clk *clk)
 554 {
 555         list_add_tail(&clk->node, &clocks);
 556
 557         clk->cl.con_id = clk->name;
 558         clk->cl.clk = clk;
 559         clkdev_add(&clk->cl);
 560 }
 561
 562 int __init clk_register(struct clk *clk)
 563 {
 564         if (clk_is_peripheral(clk)) {
 565                 if (!clk->parent)
 566                         clk->parent = &mck;
 567                 if (cpu_is_sama5d3())
 568                         clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
 569                                                     1 << clk->div);
 570                 clk->mode = pmc_periph_mode;
 571         }
 572         else if (clk_is_sys(clk)) {
 573                 clk->parent = &mck;
 574                 clk->mode = pmc_sys_mode;
 575         }
 576         else if (clk_is_programmable(clk)) {
 577                 clk->mode = pmc_sys_mode;
 578                 init_programmable_clock(clk);
 579         }
 580
 581         at91_clk_add(clk);
 582
 583         return 0;
 584 }
 585
 586 /*------------------------------------------------------------------------*/
 587
 588 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 589 {
 590         unsigned mul, div;
 591
 592         div = reg & 0xff;
 593         if (cpu_is_sama5d3())
 594                 mul = AT91_PMC3_MUL_GET(reg);
 595         else
 596                 mul = AT91_PMC_MUL_GET(reg);
 597
 598         if (div && mul) {
 599                 freq /= div;
 600                 freq *= mul + 1;
 601         } else
 602                 freq = 0;
 603
 604         return freq;
 605 }
 606
 607 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 608 {
 609         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 610                 return freq / 2;
 611         else if (pll == &utmi_clk || cpu_is_at91sam9n12())
 612                 return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
 613         else
 614                 return freq;
 615 }
 616
 617 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 618 {
 619         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 620         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 621
 622         /* PLL output max 240 MHz (or 180 MHz per errata) */
 623         if (out_freq > 240000000)
 624                 goto fail;
 625
 626         for (i = 1; i < 256; i++) {
 627                 int diff1;
 628                 unsigned input, mul1;
 629
 630                 /*
 631                  * PLL input between 1MHz and 32MHz per spec, but lower
 632                  * frequences seem necessary in some cases so allow 100K.
 633                  * Warning: some newer products need 2MHz min.
 634                  */
 635                 input = main_freq / i;
 636                 if (cpu_is_at91sam9g20() && input < 2000000)
 637                         continue;
 638                 if (input < 100000)
 639                         continue;
 640                 if (input > 32000000)
 641                         continue;
 642
 643                 mul1 = out_freq / input;
 644                 if (cpu_is_at91sam9g20() && mul > 63)
 645                         continue;
 646                 if (mul1 > 2048)
 647                         continue;
 648                 if (mul1 < 2)
 649                         goto fail;
 650
 651                 diff1 = out_freq - input * mul1;
 652                 if (diff1 < 0)
 653                         diff1 = -diff1;
 654                 if (diff > diff1) {
 655                         diff = diff1;
 656                         div = i;
 657                         mul = mul1;
 658                         if (diff == 0)
 659                                 break;
 660                 }
 661         }
 662         if (i == 256 && diff > (out_freq >> 5))
 663                 goto fail;
 664         return ret | ((mul - 1) << 16) | div;
 665 fail:
 666         return 0;
 667 }
 668
 669 static struct clk *const standard_pmc_clocks[] __initconst = {
 670         /* four primary clocks */
 671         &clk32k,
 672         &main_clk,
 673         &plla,
 674
 675         /* MCK */
 676         &mck
 677 };
 678
 679 /* PLLB generated USB full speed clock init */
 680 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
 681 {
 682         unsigned int reg;
 683
 684         /*
 685          * USB clock init:  choose 48 MHz PLLB value,
 686          * disable 48MHz clock during usb peripheral suspend.
 687          *
 688          * REVISIT:  assumes MCK doesn't derive from PLLB!
 689          */
 690         uhpck.parent = &pllb;
 691
 692         reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
 693         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 694         if (cpu_is_at91rm9200()) {
 695                 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
 696                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 697                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 698                 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 699         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
 700                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
 701                    cpu_is_at91sam9g10()) {
 702                 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
 703                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 704                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 705         } else if (cpu_is_at91sam9n12()) {
 706                 /* Divider for USB clock is in USB clock register for 9n12 */
 707                 reg = AT91_PMC_USBS_PLLB;
 708
 709                 /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
 710                 reg |= AT91_PMC_OHCIUSBDIV_2;
 711                 at91_pmc_write(AT91_PMC_USB, reg);
 712
 713                 /* Still setup masks */
 714                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 715                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 716         }
 717         at91_pmc_write(AT91_CKGR_PLLBR, 0);
 718
 719         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
 720         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
 721 }
 722
 723 /* UPLL generated USB full speed clock init */
 724 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 725 {
 726         /*
 727          * USB clock init: choose 480 MHz from UPLL,
 728          */
 729         unsigned int usbr = AT91_PMC_USBS_UPLL;
 730
 731         /* Setup divider by 10 to reach 48 MHz */
 732         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 733
 734         at91_pmc_write(AT91_PMC_USB, usbr);
 735
 736         /* Now set uhpck values */
 737         uhpck.parent = &utmi_clk;
 738         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 739         uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
 740 }
 741
 742 static int __init at91_pmc_init(unsigned long main_clock)
 743 {
 744         unsigned tmp, freq, mckr;
 745         int i;
 746         int pll_overclock = false;
 747
 748         /*
 749          * When the bootloader initialized the main oscillator correctly,
 750          * there's no problem using the cycle counter.  But if it didn't,
 751          * or when using oscillator bypass mode, we must be told the speed
 752          * of the main clock.
 753          */
 754         if (!main_clock) {
 755                 do {
 756                         tmp = at91_pmc_read(AT91_CKGR_MCFR);
 757                 } while (!(tmp & AT91_PMC_MAINRDY));
 758                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 759         }
 760         main_clk.rate_hz = main_clock;
 761
 762         /* report if PLLA is more than mildly overclocked */
 763         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
 764         if (cpu_has_1056M_plla()) {
 765                 if (plla.rate_hz > 1056000000)
 766                         pll_overclock = true;
 767         } else if (cpu_has_800M_plla()) {
 768                 if (plla.rate_hz > 800000000)
 769                         pll_overclock = true;
 770         } else if (cpu_has_300M_plla()) {
 771                 if (plla.rate_hz > 300000000)
 772                         pll_overclock = true;
 773         } else if (cpu_has_240M_plla()) {
 774                 if (plla.rate_hz > 240000000)
 775                         pll_overclock = true;
 776         } else if (cpu_has_210M_plla()) {
 777                 if (plla.rate_hz > 210000000)
 778                         pll_overclock = true;
 779         } else {
 780                 if (plla.rate_hz > 209000000)
 781                         pll_overclock = true;
 782         }
 783         if (pll_overclock)
 784                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 785
 786         if (cpu_has_plladiv2()) {
 787                 mckr = at91_pmc_read(AT91_PMC_MCKR);
 788                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
 789         }
 790
 791         if (!cpu_has_pllb() && cpu_has_upll()) {
 792                 /* setup UTMI clock as the fourth primary clock
 793                  * (instead of pllb) */
 794                 utmi_clk.type |= CLK_TYPE_PRIMARY;
 795                 utmi_clk.id = 3;
 796         }
 797
 798
 799         /*
 800          * USB HS clock init
 801          */
 802         if (cpu_has_utmi()) {
 803                 /*
 804                  * multiplier is hard-wired to 40
 805                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
 806                  */
 807                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
 808
 809                 /* UTMI bias and PLL are managed at the same time */
 810                 if (cpu_has_upll())
 811                         utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
 812         }
 813
 814         /*
 815          * USB FS clock init
 816          */
 817         if (cpu_has_pllb())
 818                 at91_pllb_usbfs_clock_init(main_clock);
 819         if (cpu_has_upll())
 820                 /* assumes that we choose UPLL for USB and not PLLA */
 821                 at91_upll_usbfs_clock_init(main_clock);
 822
 823         /*
 824          * MCK and CPU derive from one of those primary clocks.
 825          * For now, assume this parentage won't change.
 826          */
 827         mckr = at91_pmc_read(AT91_PMC_MCKR);
 828         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 829         freq = mck.parent->rate_hz;
 830         freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
 831         if (cpu_is_at91rm9200()) {
 832                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 833         } else if (cpu_is_at91sam9g20()) {
 834                 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
 835                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 836                 if (mckr & AT91_PMC_PDIV)
 837                         freq /= 2;              /* processor clock division */
 838         } else if (cpu_has_mdiv3()) {
 839                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
 840                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
 841         } else {
 842                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
 843         }
 844
 845         if (cpu_has_alt_prescaler()) {
 846                 /* Programmable clocks can use MCK */
 847                 mck.type |= CLK_TYPE_PRIMARY;
 848                 mck.id = 4;
 849         }
 850
 851         /* Register the PMC's standard clocks */
 852         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 853                 at91_clk_add(standard_pmc_clocks[i]);
 854
 855         if (cpu_has_pllb())
 856                 at91_clk_add(&pllb);
 857
 858         if (cpu_has_uhp())
 859                 at91_clk_add(&uhpck);
 860
 861         if (cpu_has_udpfs())
 862                 at91_clk_add(&udpck);
 863
 864         if (cpu_has_utmi())
 865                 at91_clk_add(&utmi_clk);
 866
 867         /* MCK and CPU clock are "always on" */
 868         clk_enable(&mck);
 869
 870         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 871                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 872                 (unsigned) main_clock / 1000000,
 873                 ((unsigned) main_clock % 1000000) / 1000);
 874
 875         return 0;
 876 }
 877
 878 #if defined(CONFIG_OF)
 879 static struct of_device_id pmc_ids[] = {
 880         { .compatible = "atmel,at91rm9200-pmc" },
 881         { .compatible = "atmel,at91sam9260-pmc" },
 882         { .compatible = "atmel,at91sam9g45-pmc" },
 883         { .compatible = "atmel,at91sam9n12-pmc" },
 884         { .compatible = "atmel,at91sam9x5-pmc" },
 885         { .compatible = "atmel,sama5d3-pmc" },
 886         { /*sentinel*/ }
 887 };
 888
 889 static struct of_device_id osc_ids[] = {
 890         { .compatible = "atmel,osc" },
 891         { /*sentinel*/ }
 892 };
 893
 894 int __init at91_dt_clock_init(void)
 895 {
 896         struct device_node *np;
 897         u32 main_clock = 0;
 898
 899         np = of_find_matching_node(NULL, pmc_ids);
 900         if (!np)
 901                 panic("unable to find compatible pmc node in dtb\n");
 902
 903         at91_pmc_base = of_iomap(np, 0);
 904         if (!at91_pmc_base)
 905                 panic("unable to map pmc cpu registers\n");
 906
 907         of_node_put(np);
 908
 909         /* retrieve the freqency of fixed clocks from device tree */
 910         np = of_find_matching_node(NULL, osc_ids);
 911         if (np) {
 912                 u32 rate;
 913                 if (!of_property_read_u32(np, "clock-frequency", &rate))
 914                         main_clock = rate;
 915         }
 916
 917         of_node_put(np);
 918
 919         return at91_pmc_init(main_clock);
 920 }
 921 #endif
 922
 923 int __init at91_clock_init(unsigned long main_clock)
 924 {
 925         at91_pmc_base = ioremap(AT91_PMC, 256);
 926         if (!at91_pmc_base)
 927                 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
 928
 929         return at91_pmc_init(main_clock);
 930 }
 931
 932 /*
 933  * Several unused clocks may be active.  Turn them off.
 934  */
 935 static int __init at91_clock_reset(void)
 936 {
 937         unsigned long pcdr = 0;
 938         unsigned long pcdr1 = 0;
 939         unsigned long scdr = 0;
 940         struct clk *clk;
 941
 942         list_for_each_entry(clk, &clocks, node) {
 943                 if (clk->users > 0)
 944                         continue;
 945
 946                 if (clk->mode == pmc_periph_mode) {
 947                         if (cpu_is_sama5d3()) {
 948                                 u32 pmc_mask = 1 << (clk->pid % 32);
 949
 950                                 if (clk->pid > 31)
 951                                         pcdr1 |= pmc_mask;
 952                                 else
 953                                         pcdr |= pmc_mask;
 954                         } else
 955                                 pcdr |= clk->pmc_mask;
 956                 }
 957
 958                 if (clk->mode == pmc_sys_mode)
 959                         scdr |= clk->pmc_mask;
 960
 961                 pr_debug("Clocks: disable unused %s\n", clk->name);
 962         }
 963
 964         at91_pmc_write(AT91_PMC_SCDR, scdr);
 965         at91_pmc_write(AT91_PMC_PCDR, pcdr);
 966         if (cpu_is_sama5d3())
 967                 at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
 968
 969         return 0;
 970 }
 971 late_initcall(at91_clock_reset);
 972
 973 void at91sam9_idle(void)
 974 {
 975         at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 976         cpu_do_idle();
 977 }