arch/arm/mach-at91/at91sam9n12.c

   1 /*
   2  * SoC specific setup code for the AT91SAM9N12
   3  *
   4  * Copyright (C) 2012 Atmel Corporation.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11
  12 #include <asm/irq.h>
  13 #include <asm/mach/arch.h>
  14 #include <asm/mach/map.h>
  15 #include <mach/at91sam9n12.h>
  16 #include <mach/at91_pmc.h>
  17 #include <mach/cpu.h>
  18 #include <mach/board.h>
  19
  20 #include "soc.h"
  21 #include "generic.h"
  22 #include "clock.h"
  23 #include "sam9_smc.h"
  24
  25 /* --------------------------------------------------------------------
  26  *  Clocks
  27  * -------------------------------------------------------------------- */
  28
  29 /*
  30  * The peripheral clocks.
  31  */
  32 static struct clk pioAB_clk = {
  33         .name           = "pioAB_clk",
  34         .pmc_mask       = 1 << AT91SAM9N12_ID_PIOAB,
  35         .type           = CLK_TYPE_PERIPHERAL,
  36 };
  37 static struct clk pioCD_clk = {
  38         .name           = "pioCD_clk",
  39         .pmc_mask       = 1 << AT91SAM9N12_ID_PIOCD,
  40         .type           = CLK_TYPE_PERIPHERAL,
  41 };
  42 static struct clk usart0_clk = {
  43         .name           = "usart0_clk",
  44         .pmc_mask       = 1 << AT91SAM9N12_ID_USART0,
  45         .type           = CLK_TYPE_PERIPHERAL,
  46 };
  47 static struct clk usart1_clk = {
  48         .name           = "usart1_clk",
  49         .pmc_mask       = 1 << AT91SAM9N12_ID_USART1,
  50         .type           = CLK_TYPE_PERIPHERAL,
  51 };
  52 static struct clk usart2_clk = {
  53         .name           = "usart2_clk",
  54         .pmc_mask       = 1 << AT91SAM9N12_ID_USART2,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk usart3_clk = {
  58         .name           = "usart3_clk",
  59         .pmc_mask       = 1 << AT91SAM9N12_ID_USART3,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62 static struct clk twi0_clk = {
  63         .name           = "twi0_clk",
  64         .pmc_mask       = 1 << AT91SAM9N12_ID_TWI0,
  65         .type           = CLK_TYPE_PERIPHERAL,
  66 };
  67 static struct clk twi1_clk = {
  68         .name           = "twi1_clk",
  69         .pmc_mask       = 1 << AT91SAM9N12_ID_TWI1,
  70         .type           = CLK_TYPE_PERIPHERAL,
  71 };
  72 static struct clk mmc_clk = {
  73         .name           = "mci_clk",
  74         .pmc_mask       = 1 << AT91SAM9N12_ID_MCI,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk spi0_clk = {
  78         .name           = "spi0_clk",
  79         .pmc_mask       = 1 << AT91SAM9N12_ID_SPI0,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk spi1_clk = {
  83         .name           = "spi1_clk",
  84         .pmc_mask       = 1 << AT91SAM9N12_ID_SPI1,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk uart0_clk = {
  88         .name           = "uart0_clk",
  89         .pmc_mask       = 1 << AT91SAM9N12_ID_UART0,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk uart1_clk = {
  93         .name           = "uart1_clk",
  94         .pmc_mask       = 1 << AT91SAM9N12_ID_UART1,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk tcb_clk = {
  98         .name           = "tcb_clk",
  99         .pmc_mask       = 1 << AT91SAM9N12_ID_TCB,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk pwm_clk = {
 103         .name           = "pwm_clk",
 104         .pmc_mask       = 1 << AT91SAM9N12_ID_PWM,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk adc_clk = {
 108         .name           = "adc_clk",
 109         .pmc_mask       = 1 << AT91SAM9N12_ID_ADC,
 110         .type   = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk dma_clk = {
 113         .name           = "dma_clk",
 114         .pmc_mask       = 1 << AT91SAM9N12_ID_DMA,
 115         .type   = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk uhp_clk = {
 118         .name           = "uhp",
 119         .pmc_mask       = 1 << AT91SAM9N12_ID_UHP,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk udp_clk = {
 123         .name           = "udp_clk",
 124         .pmc_mask       = 1 << AT91SAM9N12_ID_UDP,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk lcdc_clk = {
 128         .name           = "lcdc_clk",
 129         .pmc_mask       = 1 << AT91SAM9N12_ID_LCDC,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132 static struct clk ssc_clk = {
 133         .name           = "ssc_clk",
 134         .pmc_mask       = 1 << AT91SAM9N12_ID_SSC,
 135         .type           = CLK_TYPE_PERIPHERAL,
 136 };
 137
 138 static struct clk *periph_clocks[] __initdata = {
 139         &pioAB_clk,
 140         &pioCD_clk,
 141         &usart0_clk,
 142         &usart1_clk,
 143         &usart2_clk,
 144         &usart3_clk,
 145         &twi0_clk,
 146         &twi1_clk,
 147         &mmc_clk,
 148         &spi0_clk,
 149         &spi1_clk,
 150         &lcdc_clk,
 151         &uart0_clk,
 152         &uart1_clk,
 153         &tcb_clk,
 154         &pwm_clk,
 155         &adc_clk,
 156         &dma_clk,
 157         &uhp_clk,
 158         &udp_clk,
 159         &ssc_clk,
 160 };
 161
 162 static struct clk_lookup periph_clocks_lookups[] = {
 163         /* lookup table for DT entries */
 164         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 165         CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
 166         CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
 167         CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
 168         CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
 169         CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
 170         CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
 171         CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
 172         CLKDEV_CON_ID("pioA", &pioAB_clk),
 173         CLKDEV_CON_ID("pioB", &pioAB_clk),
 174         CLKDEV_CON_ID("pioC", &pioCD_clk),
 175         CLKDEV_CON_ID("pioD", &pioCD_clk),
 176         /* additional fake clock for macb_hclk */
 177         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
 178         CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
 179 };
 180
 181 /*
 182  * The two programmable clocks.
 183  * You must configure pin multiplexing to bring these signals out.
 184  */
 185 static struct clk pck0 = {
 186         .name           = "pck0",
 187         .pmc_mask       = AT91_PMC_PCK0,
 188         .type           = CLK_TYPE_PROGRAMMABLE,
 189         .id             = 0,
 190 };
 191 static struct clk pck1 = {
 192         .name           = "pck1",
 193         .pmc_mask       = AT91_PMC_PCK1,
 194         .type           = CLK_TYPE_PROGRAMMABLE,
 195         .id             = 1,
 196 };
 197
 198 static void __init at91sam9n12_register_clocks(void)
 199 {
 200         int i;
 201
 202         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 203                 clk_register(periph_clocks[i]);
 204         clk_register(&pck0);
 205         clk_register(&pck1);
 206
 207         clkdev_add_table(periph_clocks_lookups,
 208                          ARRAY_SIZE(periph_clocks_lookups));
 209
 210 }
 211
 212 /* --------------------------------------------------------------------
 213  *  AT91SAM9N12 processor initialization
 214  * -------------------------------------------------------------------- */
 215
 216 static void __init at91sam9n12_map_io(void)
 217 {
 218         at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
 219 }
 220
 221 void __init at91sam9n12_initialize(void)
 222 {
 223         at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
 224
 225         /* Register GPIO subsystem (using DT) */
 226         at91_gpio_init(NULL, 0);
 227 }
 228
 229 struct at91_init_soc __initdata at91sam9n12_soc = {
 230         .map_io = at91sam9n12_map_io,
 231         .register_clocks = at91sam9n12_register_clocks,
 232         .init = at91sam9n12_initialize,
 233 };