arch/arm/mach-at91/at91sam9g45.c

   1 /*
   2  *  Chip-specific setup code for the AT91SAM9G45 family
   3  *
   4  *  Copyright (C) 2009 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/clk/at91_pmc.h>
  16 #include <linux/platform_device.h>
  17
  18 #include <asm/irq.h>
  19 #include <asm/mach/arch.h>
  20 #include <asm/mach/map.h>
  21 #include <asm/system_misc.h>
  22 #include <mach/at91sam9g45.h>
  23 #include <mach/cpu.h>
  24 #include <mach/hardware.h>
  25
  26 #include "at91_aic.h"
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "sam9_smc.h"
  30 #include "pm.h"
  31
  32 #if defined(CONFIG_OLD_CLK_AT91)
  33 #include "clock.h"
  34 /* --------------------------------------------------------------------
  35  *  Clocks
  36  * -------------------------------------------------------------------- */
  37
  38 /*
  39  * The peripheral clocks.
  40  */
  41 static struct clk pioA_clk = {
  42         .name           = "pioA_clk",
  43         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOA,
  44         .type           = CLK_TYPE_PERIPHERAL,
  45 };
  46 static struct clk pioB_clk = {
  47         .name           = "pioB_clk",
  48         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOB,
  49         .type           = CLK_TYPE_PERIPHERAL,
  50 };
  51 static struct clk pioC_clk = {
  52         .name           = "pioC_clk",
  53         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOC,
  54         .type           = CLK_TYPE_PERIPHERAL,
  55 };
  56 static struct clk pioDE_clk = {
  57         .name           = "pioDE_clk",
  58         .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
  59         .type           = CLK_TYPE_PERIPHERAL,
  60 };
  61 static struct clk trng_clk = {
  62         .name           = "trng_clk",
  63         .pmc_mask       = 1 << AT91SAM9G45_ID_TRNG,
  64         .type           = CLK_TYPE_PERIPHERAL,
  65 };
  66 static struct clk usart0_clk = {
  67         .name           = "usart0_clk",
  68         .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
  69         .type           = CLK_TYPE_PERIPHERAL,
  70 };
  71 static struct clk usart1_clk = {
  72         .name           = "usart1_clk",
  73         .pmc_mask       = 1 << AT91SAM9G45_ID_US1,
  74         .type           = CLK_TYPE_PERIPHERAL,
  75 };
  76 static struct clk usart2_clk = {
  77         .name           = "usart2_clk",
  78         .pmc_mask       = 1 << AT91SAM9G45_ID_US2,
  79         .type           = CLK_TYPE_PERIPHERAL,
  80 };
  81 static struct clk usart3_clk = {
  82         .name           = "usart3_clk",
  83         .pmc_mask       = 1 << AT91SAM9G45_ID_US3,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk mmc0_clk = {
  87         .name           = "mci0_clk",
  88         .pmc_mask       = 1 << AT91SAM9G45_ID_MCI0,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk twi0_clk = {
  92         .name           = "twi0_clk",
  93         .pmc_mask       = 1 << AT91SAM9G45_ID_TWI0,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk twi1_clk = {
  97         .name           = "twi1_clk",
  98         .pmc_mask       = 1 << AT91SAM9G45_ID_TWI1,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk spi0_clk = {
 102         .name           = "spi0_clk",
 103         .pmc_mask       = 1 << AT91SAM9G45_ID_SPI0,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk spi1_clk = {
 107         .name           = "spi1_clk",
 108         .pmc_mask       = 1 << AT91SAM9G45_ID_SPI1,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk ssc0_clk = {
 112         .name           = "ssc0_clk",
 113         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC0,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk ssc1_clk = {
 117         .name           = "ssc1_clk",
 118         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk tcb0_clk = {
 122         .name           = "tcb0_clk",
 123         .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk pwm_clk = {
 127         .name           = "pwm_clk",
 128         .pmc_mask       = 1 << AT91SAM9G45_ID_PWMC,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131 static struct clk tsc_clk = {
 132         .name           = "tsc_clk",
 133         .pmc_mask       = 1 << AT91SAM9G45_ID_TSC,
 134         .type           = CLK_TYPE_PERIPHERAL,
 135 };
 136 static struct clk dma_clk = {
 137         .name           = "dma_clk",
 138         .pmc_mask       = 1 << AT91SAM9G45_ID_DMA,
 139         .type           = CLK_TYPE_PERIPHERAL,
 140 };
 141 static struct clk uhphs_clk = {
 142         .name           = "uhphs_clk",
 143         .pmc_mask       = 1 << AT91SAM9G45_ID_UHPHS,
 144         .type           = CLK_TYPE_PERIPHERAL,
 145 };
 146 static struct clk lcdc_clk = {
 147         .name           = "lcdc_clk",
 148         .pmc_mask       = 1 << AT91SAM9G45_ID_LCDC,
 149         .type           = CLK_TYPE_PERIPHERAL,
 150 };
 151 static struct clk ac97_clk = {
 152         .name           = "ac97_clk",
 153         .pmc_mask       = 1 << AT91SAM9G45_ID_AC97C,
 154         .type           = CLK_TYPE_PERIPHERAL,
 155 };
 156 static struct clk macb_clk = {
 157         .name           = "pclk",
 158         .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
 159         .type           = CLK_TYPE_PERIPHERAL,
 160 };
 161 static struct clk isi_clk = {
 162         .name           = "isi_clk",
 163         .pmc_mask       = 1 << AT91SAM9G45_ID_ISI,
 164         .type           = CLK_TYPE_PERIPHERAL,
 165 };
 166 static struct clk udphs_clk = {
 167         .name           = "udphs_clk",
 168         .pmc_mask       = 1 << AT91SAM9G45_ID_UDPHS,
 169         .type           = CLK_TYPE_PERIPHERAL,
 170 };
 171 static struct clk mmc1_clk = {
 172         .name           = "mci1_clk",
 173         .pmc_mask       = 1 << AT91SAM9G45_ID_MCI1,
 174         .type           = CLK_TYPE_PERIPHERAL,
 175 };
 176
 177 /* Video decoder clock - Only for sam9m10/sam9m11 */
 178 static struct clk vdec_clk = {
 179         .name           = "vdec_clk",
 180         .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
 181         .type           = CLK_TYPE_PERIPHERAL,
 182 };
 183
 184 static struct clk adc_op_clk = {
 185         .name           = "adc_op_clk",
 186         .type           = CLK_TYPE_PERIPHERAL,
 187         .rate_hz        = 300000,
 188 };
 189
 190 /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
 191 static struct clk aestdessha_clk = {
 192         .name           = "aestdessha_clk",
 193         .pmc_mask       = 1 << AT91SAM9G45_ID_AESTDESSHA,
 194         .type           = CLK_TYPE_PERIPHERAL,
 195 };
 196
 197 static struct clk *periph_clocks[] __initdata = {
 198         &pioA_clk,
 199         &pioB_clk,
 200         &pioC_clk,
 201         &pioDE_clk,
 202         &trng_clk,
 203         &usart0_clk,
 204         &usart1_clk,
 205         &usart2_clk,
 206         &usart3_clk,
 207         &mmc0_clk,
 208         &twi0_clk,
 209         &twi1_clk,
 210         &spi0_clk,
 211         &spi1_clk,
 212         &ssc0_clk,
 213         &ssc1_clk,
 214         &tcb0_clk,
 215         &pwm_clk,
 216         &tsc_clk,
 217         &dma_clk,
 218         &uhphs_clk,
 219         &lcdc_clk,
 220         &ac97_clk,
 221         &macb_clk,
 222         &isi_clk,
 223         &udphs_clk,
 224         &mmc1_clk,
 225         &adc_op_clk,
 226         &aestdessha_clk,
 227         // irq0
 228 };
 229
 230 static struct clk_lookup periph_clocks_lookups[] = {
 231         /* One additional fake clock for macb_hclk */
 232         CLKDEV_CON_ID("hclk", &macb_clk),
 233         /* One additional fake clock for ohci */
 234         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
 235         CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
 236         CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
 237         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
 238         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 239         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 240         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
 241         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
 242         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 243         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 244         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
 245         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
 246         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
 247         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
 248         CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
 249         CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
 250         CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
 251         CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
 252         CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
 253         CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
 254         CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
 255         CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
 256         CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
 257         /* more usart lookup table for DT entries */
 258         CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
 259         CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
 260         CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
 261         CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
 262         CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
 263         /* more tc lookup table for DT entries */
 264         CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
 265         CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
 266         CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
 267         CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
 268         CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
 269         CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
 270         CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
 271         CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
 272         CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
 273         CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
 274         CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
 275         CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
 276         /* fake hclk clock */
 277         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 278         CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
 279         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
 280         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
 281         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
 282         CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
 283
 284         CLKDEV_CON_ID("pioA", &pioA_clk),
 285         CLKDEV_CON_ID("pioB", &pioB_clk),
 286         CLKDEV_CON_ID("pioC", &pioC_clk),
 287         CLKDEV_CON_ID("pioD", &pioDE_clk),
 288         CLKDEV_CON_ID("pioE", &pioDE_clk),
 289         /* Fake adc clock */
 290         CLKDEV_CON_ID("adc_clk", &tsc_clk),
 291         CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 292 };
 293
 294 static struct clk_lookup usart_clocks_lookups[] = {
 295         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 296         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 297         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 298         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 299         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 300 };
 301
 302 /*
 303  * The two programmable clocks.
 304  * You must configure pin multiplexing to bring these signals out.
 305  */
 306 static struct clk pck0 = {
 307         .name           = "pck0",
 308         .pmc_mask       = AT91_PMC_PCK0,
 309         .type           = CLK_TYPE_PROGRAMMABLE,
 310         .id             = 0,
 311 };
 312 static struct clk pck1 = {
 313         .name           = "pck1",
 314         .pmc_mask       = AT91_PMC_PCK1,
 315         .type           = CLK_TYPE_PROGRAMMABLE,
 316         .id             = 1,
 317 };
 318
 319 static void __init at91sam9g45_register_clocks(void)
 320 {
 321         int i;
 322
 323         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 324                 clk_register(periph_clocks[i]);
 325
 326         clkdev_add_table(periph_clocks_lookups,
 327                          ARRAY_SIZE(periph_clocks_lookups));
 328         clkdev_add_table(usart_clocks_lookups,
 329                          ARRAY_SIZE(usart_clocks_lookups));
 330
 331         if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
 332                 clk_register(&vdec_clk);
 333
 334         clk_register(&pck0);
 335         clk_register(&pck1);
 336 }
 337 #else
 338 #define at91sam9g45_register_clocks NULL
 339 #endif
 340
 341 /* --------------------------------------------------------------------
 342  *  GPIO
 343  * -------------------------------------------------------------------- */
 344
 345 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
 346         {
 347                 .id             = AT91SAM9G45_ID_PIOA,
 348                 .regbase        = AT91SAM9G45_BASE_PIOA,
 349         }, {
 350                 .id             = AT91SAM9G45_ID_PIOB,
 351                 .regbase        = AT91SAM9G45_BASE_PIOB,
 352         }, {
 353                 .id             = AT91SAM9G45_ID_PIOC,
 354                 .regbase        = AT91SAM9G45_BASE_PIOC,
 355         }, {
 356                 .id             = AT91SAM9G45_ID_PIODE,
 357                 .regbase        = AT91SAM9G45_BASE_PIOD,
 358         }, {
 359                 .id             = AT91SAM9G45_ID_PIODE,
 360                 .regbase        = AT91SAM9G45_BASE_PIOE,
 361         }
 362 };
 363
 364 /* --------------------------------------------------------------------
 365  *  AT91SAM9G45 processor initialization
 366  * -------------------------------------------------------------------- */
 367
 368 static void __init at91sam9g45_map_io(void)
 369 {
 370         at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
 371 }
 372
 373 static void __init at91sam9g45_ioremap_registers(void)
 374 {
 375         at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
 376         at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
 377         at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
 378         at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
 379         at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
 380         at91_pm_set_standby(at91_ddr_standby);
 381 }
 382
 383 static void __init at91sam9g45_initialize(void)
 384 {
 385         arm_pm_idle = at91sam9_idle;
 386
 387         at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
 388         at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
 389
 390         /* Register GPIO subsystem */
 391         at91_gpio_init(at91sam9g45_gpio, 5);
 392 }
 393
 394 static struct resource rstc_resources[] = {
 395         [0] = {
 396                 .start  = AT91SAM9G45_BASE_RSTC,
 397                 .end    = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
 398                 .flags  = IORESOURCE_MEM,
 399         },
 400         [1] = {
 401                 .start  = AT91SAM9G45_BASE_DDRSDRC1,
 402                 .end    = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
 403                 .flags  = IORESOURCE_MEM,
 404         },
 405         [2] = {
 406                 .start  = AT91SAM9G45_BASE_DDRSDRC0,
 407                 .end    = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
 408                 .flags  = IORESOURCE_MEM,
 409         },
 410 };
 411
 412 static struct platform_device rstc_device = {
 413         .name           = "at91-sam9g45-reset",
 414         .resource       = rstc_resources,
 415         .num_resources  = ARRAY_SIZE(rstc_resources),
 416 };
 417
 418 static struct resource shdwc_resources[] = {
 419         [0] = {
 420                 .start  = AT91SAM9G45_BASE_SHDWC,
 421                 .end    = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
 422                 .flags  = IORESOURCE_MEM,
 423         },
 424 };
 425
 426 static struct platform_device shdwc_device = {
 427         .name           = "at91-poweroff",
 428         .resource       = shdwc_resources,
 429         .num_resources  = ARRAY_SIZE(shdwc_resources),
 430 };
 431
 432 static void __init at91sam9g45_register_devices(void)
 433 {
 434         platform_device_register(&rstc_device);
 435         platform_device_register(&shdwc_device);
 436 }
 437
 438 /* --------------------------------------------------------------------
 439  *  Interrupt initialization
 440  * -------------------------------------------------------------------- */
 441
 442 /*
 443  * The default interrupt priority levels (0 = lowest, 7 = highest).
 444  */
 445 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
 446         7,      /* Advanced Interrupt Controller (FIQ) */
 447         7,      /* System Peripherals */
 448         1,      /* Parallel IO Controller A */
 449         1,      /* Parallel IO Controller B */
 450         1,      /* Parallel IO Controller C */
 451         1,      /* Parallel IO Controller D and E */
 452         0,
 453         5,      /* USART 0 */
 454         5,      /* USART 1 */
 455         5,      /* USART 2 */
 456         5,      /* USART 3 */
 457         0,      /* Multimedia Card Interface 0 */
 458         6,      /* Two-Wire Interface 0 */
 459         6,      /* Two-Wire Interface 1 */
 460         5,      /* Serial Peripheral Interface 0 */
 461         5,      /* Serial Peripheral Interface 1 */
 462         4,      /* Serial Synchronous Controller 0 */
 463         4,      /* Serial Synchronous Controller 1 */
 464         0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
 465         0,      /* Pulse Width Modulation Controller */
 466         0,      /* Touch Screen Controller */
 467         0,      /* DMA Controller */
 468         2,      /* USB Host High Speed port */
 469         3,      /* LDC Controller */
 470         5,      /* AC97 Controller */
 471         3,      /* Ethernet */
 472         0,      /* Image Sensor Interface */
 473         2,      /* USB Device High speed port */
 474         0,      /* AESTDESSHA Crypto HW Accelerators */
 475         0,      /* Multimedia Card Interface 1 */
 476         0,
 477         0,      /* Advanced Interrupt Controller (IRQ0) */
 478 };
 479
 480 static void __init at91sam9g45_init_time(void)
 481 {
 482         at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 483 }
 484
 485 AT91_SOC_START(at91sam9g45)
 486         .map_io = at91sam9g45_map_io,
 487         .default_irq_priority = at91sam9g45_default_irq_priority,
 488         .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
 489         .ioremap_registers = at91sam9g45_ioremap_registers,
 490         .register_clocks = at91sam9g45_register_clocks,
 491         .register_devices = at91sam9g45_register_devices,
 492         .init = at91sam9g45_initialize,
 493         .init_time = at91sam9g45_init_time,
 494 AT91_SOC_END