arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk/at91_pmc.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/irq.h>
  19 #include <asm/mach/arch.h>
  20 #include <asm/mach/map.h>
  21 #include <asm/system_misc.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24 #include <mach/at91sam9260.h>
  25 #include <mach/hardware.h>
  26
  27 #include "at91_aic.h"
  28 #include "soc.h"
  29 #include "generic.h"
  30 #include "sam9_smc.h"
  31 #include "pm.h"
  32
  33 #if defined(CONFIG_OLD_CLK_AT91)
  34 #include "clock.h"
  35 /* --------------------------------------------------------------------
  36  *  Clocks
  37  * -------------------------------------------------------------------- */
  38
  39 /*
  40  * The peripheral clocks.
  41  */
  42 static struct clk pioA_clk = {
  43         .name           = "pioA_clk",
  44         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  45         .type           = CLK_TYPE_PERIPHERAL,
  46 };
  47 static struct clk pioB_clk = {
  48         .name           = "pioB_clk",
  49         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  50         .type           = CLK_TYPE_PERIPHERAL,
  51 };
  52 static struct clk pioC_clk = {
  53         .name           = "pioC_clk",
  54         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk adc_clk = {
  58         .name           = "adc_clk",
  59         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62
  63 static struct clk adc_op_clk = {
  64         .name           = "adc_op_clk",
  65         .type           = CLK_TYPE_PERIPHERAL,
  66         .rate_hz        = 5000000,
  67 };
  68
  69 static struct clk usart0_clk = {
  70         .name           = "usart0_clk",
  71         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk usart1_clk = {
  75         .name           = "usart1_clk",
  76         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk usart2_clk = {
  80         .name           = "usart2_clk",
  81         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk mmc_clk = {
  85         .name           = "mci_clk",
  86         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk udc_clk = {
  90         .name           = "udc_clk",
  91         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk twi_clk = {
  95         .name           = "twi_clk",
  96         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk spi0_clk = {
 100         .name           = "spi0_clk",
 101         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk spi1_clk = {
 105         .name           = "spi1_clk",
 106         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk ssc_clk = {
 110         .name           = "ssc_clk",
 111         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk tc0_clk = {
 115         .name           = "tc0_clk",
 116         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk tc1_clk = {
 120         .name           = "tc1_clk",
 121         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk tc2_clk = {
 125         .name           = "tc2_clk",
 126         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk ohci_clk = {
 130         .name           = "ohci_clk",
 131         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk macb_clk = {
 135         .name           = "pclk",
 136         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk isi_clk = {
 140         .name           = "isi_clk",
 141         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk usart3_clk = {
 145         .name           = "usart3_clk",
 146         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 static struct clk usart4_clk = {
 150         .name           = "usart4_clk",
 151         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 152         .type           = CLK_TYPE_PERIPHERAL,
 153 };
 154 static struct clk usart5_clk = {
 155         .name           = "usart5_clk",
 156         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 157         .type           = CLK_TYPE_PERIPHERAL,
 158 };
 159 static struct clk tc3_clk = {
 160         .name           = "tc3_clk",
 161         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 162         .type           = CLK_TYPE_PERIPHERAL,
 163 };
 164 static struct clk tc4_clk = {
 165         .name           = "tc4_clk",
 166         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 167         .type           = CLK_TYPE_PERIPHERAL,
 168 };
 169 static struct clk tc5_clk = {
 170         .name           = "tc5_clk",
 171         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 172         .type           = CLK_TYPE_PERIPHERAL,
 173 };
 174
 175 static struct clk *periph_clocks[] __initdata = {
 176         &pioA_clk,
 177         &pioB_clk,
 178         &pioC_clk,
 179         &adc_clk,
 180         &adc_op_clk,
 181         &usart0_clk,
 182         &usart1_clk,
 183         &usart2_clk,
 184         &mmc_clk,
 185         &udc_clk,
 186         &twi_clk,
 187         &spi0_clk,
 188         &spi1_clk,
 189         &ssc_clk,
 190         &tc0_clk,
 191         &tc1_clk,
 192         &tc2_clk,
 193         &ohci_clk,
 194         &macb_clk,
 195         &isi_clk,
 196         &usart3_clk,
 197         &usart4_clk,
 198         &usart5_clk,
 199         &tc3_clk,
 200         &tc4_clk,
 201         &tc5_clk,
 202         // irq0 .. irq2
 203 };
 204
 205 static struct clk_lookup periph_clocks_lookups[] = {
 206         /* One additional fake clock for macb_hclk */
 207         CLKDEV_CON_ID("hclk", &macb_clk),
 208         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 209         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 210         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 211         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 212         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 213         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 214         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 215         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 216         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
 217         CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
 218         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
 219         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
 220         /* more usart lookup table for DT entries */
 221         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 222         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 223         CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
 224         CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
 225         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 226         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 227         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
 228         CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
 229         /* more tc lookup table for DT entries */
 230         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 231         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 232         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 233         CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
 234         CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 235         CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 236         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
 237         CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
 238         CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
 239         CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
 240         /* fake hclk clock */
 241         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 242         CLKDEV_CON_ID("pioA", &pioA_clk),
 243         CLKDEV_CON_ID("pioB", &pioB_clk),
 244         CLKDEV_CON_ID("pioC", &pioC_clk),
 245         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
 246         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
 247         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 248 };
 249
 250 static struct clk_lookup usart_clocks_lookups[] = {
 251         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 252         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 253         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 254         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 255         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 256         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 257         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 258 };
 259
 260 /*
 261  * The two programmable clocks.
 262  * You must configure pin multiplexing to bring these signals out.
 263  */
 264 static struct clk pck0 = {
 265         .name           = "pck0",
 266         .pmc_mask       = AT91_PMC_PCK0,
 267         .type           = CLK_TYPE_PROGRAMMABLE,
 268         .id             = 0,
 269 };
 270 static struct clk pck1 = {
 271         .name           = "pck1",
 272         .pmc_mask       = AT91_PMC_PCK1,
 273         .type           = CLK_TYPE_PROGRAMMABLE,
 274         .id             = 1,
 275 };
 276
 277 static void __init at91sam9260_register_clocks(void)
 278 {
 279         int i;
 280
 281         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 282                 clk_register(periph_clocks[i]);
 283
 284         clkdev_add_table(periph_clocks_lookups,
 285                          ARRAY_SIZE(periph_clocks_lookups));
 286         clkdev_add_table(usart_clocks_lookups,
 287                          ARRAY_SIZE(usart_clocks_lookups));
 288
 289         clk_register(&pck0);
 290         clk_register(&pck1);
 291 }
 292 #else
 293 #define at91sam9260_register_clocks NULL
 294 #endif
 295
 296 /* --------------------------------------------------------------------
 297  *  GPIO
 298  * -------------------------------------------------------------------- */
 299
 300 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
 301         {
 302                 .id             = AT91SAM9260_ID_PIOA,
 303                 .regbase        = AT91SAM9260_BASE_PIOA,
 304         }, {
 305                 .id             = AT91SAM9260_ID_PIOB,
 306                 .regbase        = AT91SAM9260_BASE_PIOB,
 307         }, {
 308                 .id             = AT91SAM9260_ID_PIOC,
 309                 .regbase        = AT91SAM9260_BASE_PIOC,
 310         }
 311 };
 312
 313 /* --------------------------------------------------------------------
 314  *  AT91SAM9260 processor initialization
 315  * -------------------------------------------------------------------- */
 316
 317 static void __init at91sam9xe_map_io(void)
 318 {
 319         unsigned long sram_size;
 320
 321         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 322                 case AT91_CIDR_SRAMSIZ_32K:
 323                         sram_size = 2 * SZ_16K;
 324                         break;
 325                 case AT91_CIDR_SRAMSIZ_16K:
 326                 default:
 327                         sram_size = SZ_16K;
 328         }
 329
 330         at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
 331 }
 332
 333 static void __init at91sam9260_map_io(void)
 334 {
 335         if (cpu_is_at91sam9xe())
 336                 at91sam9xe_map_io();
 337         else if (cpu_is_at91sam9g20())
 338                 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
 339         else
 340                 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 341 }
 342
 343 static void __init at91sam9260_ioremap_registers(void)
 344 {
 345         at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
 346         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
 347         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 348         at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 349         at91_pm_set_standby(at91sam9_sdram_standby);
 350 }
 351
 352 static void __init at91sam9260_initialize(void)
 353 {
 354         arm_pm_idle = at91sam9_idle;
 355
 356         at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
 357
 358         /* Register GPIO subsystem */
 359         at91_gpio_init(at91sam9260_gpio, 3);
 360 }
 361
 362 static struct resource rstc_resources[] = {
 363         [0] = {
 364                 .start  = AT91SAM9260_BASE_RSTC,
 365                 .end    = AT91SAM9260_BASE_RSTC + SZ_16 - 1,
 366                 .flags  = IORESOURCE_MEM,
 367         },
 368         [1] = {
 369                 .start  = AT91SAM9260_BASE_SDRAMC,
 370                 .end    = AT91SAM9260_BASE_SDRAMC + SZ_512 - 1,
 371                 .flags  = IORESOURCE_MEM,
 372         },
 373 };
 374
 375 static struct platform_device rstc_device = {
 376         .name           = "at91-sam9260-reset",
 377         .resource       = rstc_resources,
 378         .num_resources  = ARRAY_SIZE(rstc_resources),
 379 };
 380
 381 static struct resource shdwc_resources[] = {
 382         [0] = {
 383                 .start  = AT91SAM9260_BASE_SHDWC,
 384                 .end    = AT91SAM9260_BASE_SHDWC + SZ_16 - 1,
 385                 .flags  = IORESOURCE_MEM,
 386         },
 387 };
 388
 389 static struct platform_device shdwc_device = {
 390         .name           = "at91-poweroff",
 391         .resource       = shdwc_resources,
 392         .num_resources  = ARRAY_SIZE(shdwc_resources),
 393 };
 394
 395 static void __init at91sam9260_register_devices(void)
 396 {
 397         platform_device_register(&rstc_device);
 398         platform_device_register(&shdwc_device);
 399 }
 400
 401 /* --------------------------------------------------------------------
 402  *  Interrupt initialization
 403  * -------------------------------------------------------------------- */
 404
 405 /*
 406  * The default interrupt priority levels (0 = lowest, 7 = highest).
 407  */
 408 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 409         7,      /* Advanced Interrupt Controller */
 410         7,      /* System Peripherals */
 411         1,      /* Parallel IO Controller A */
 412         1,      /* Parallel IO Controller B */
 413         1,      /* Parallel IO Controller C */
 414         0,      /* Analog-to-Digital Converter */
 415         5,      /* USART 0 */
 416         5,      /* USART 1 */
 417         5,      /* USART 2 */
 418         0,      /* Multimedia Card Interface */
 419         2,      /* USB Device Port */
 420         6,      /* Two-Wire Interface */
 421         5,      /* Serial Peripheral Interface 0 */
 422         5,      /* Serial Peripheral Interface 1 */
 423         5,      /* Serial Synchronous Controller */
 424         0,
 425         0,
 426         0,      /* Timer Counter 0 */
 427         0,      /* Timer Counter 1 */
 428         0,      /* Timer Counter 2 */
 429         2,      /* USB Host port */
 430         3,      /* Ethernet */
 431         0,      /* Image Sensor Interface */
 432         5,      /* USART 3 */
 433         5,      /* USART 4 */
 434         5,      /* USART 5 */
 435         0,      /* Timer Counter 3 */
 436         0,      /* Timer Counter 4 */
 437         0,      /* Timer Counter 5 */
 438         0,      /* Advanced Interrupt Controller */
 439         0,      /* Advanced Interrupt Controller */
 440         0,      /* Advanced Interrupt Controller */
 441 };
 442
 443 static void __init at91sam9260_init_time(void)
 444 {
 445         at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 446 }
 447
 448 AT91_SOC_START(at91sam9260)
 449         .map_io = at91sam9260_map_io,
 450         .default_irq_priority = at91sam9260_default_irq_priority,
 451         .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 452                     | (1 << AT91SAM9260_ID_IRQ2),
 453         .ioremap_registers = at91sam9260_ioremap_registers,
 454         .register_clocks = at91sam9260_register_clocks,
 455         .register_devices = at91sam9260_register_devices,
 456         .init = at91sam9260_initialize,
 457         .init_time = at91sam9260_init_time,
 458 AT91_SOC_END