arch/arm/mach-at91/at91rm9200_devices.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200_devices.c
   3  *
   4  *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
   5  *  Copyright (C) 2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13 #include <asm/mach/arch.h>
  14 #include <asm/mach/map.h>
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/gpio.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c-gpio.h>
  20
  21 #include <mach/board.h>
  22 #include <mach/at91rm9200.h>
  23 #include <mach/at91rm9200_mc.h>
  24 #include <mach/at91_ramc.h>
  25
  26 #include "generic.h"
  27
  28
  29 /* --------------------------------------------------------------------
  30  *  USB Host
  31  * -------------------------------------------------------------------- */
  32
  33 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  34 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  35 static struct at91_usbh_data usbh_data;
  36
  37 static struct resource usbh_resources[] = {
  38         [0] = {
  39                 .start  = AT91RM9200_UHP_BASE,
  40                 .end    = AT91RM9200_UHP_BASE + SZ_1M - 1,
  41                 .flags  = IORESOURCE_MEM,
  42         },
  43         [1] = {
  44                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
  45                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
  46                 .flags  = IORESOURCE_IRQ,
  47         },
  48 };
  49
  50 static struct platform_device at91rm9200_usbh_device = {
  51         .name           = "at91_ohci",
  52         .id             = -1,
  53         .dev            = {
  54                                 .dma_mask               = &ohci_dmamask,
  55                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  56                                 .platform_data          = &usbh_data,
  57         },
  58         .resource       = usbh_resources,
  59         .num_resources  = ARRAY_SIZE(usbh_resources),
  60 };
  61
  62 void __init at91_add_device_usbh(struct at91_usbh_data *data)
  63 {
  64         int i;
  65
  66         if (!data)
  67                 return;
  68
  69         /* Enable overcurrent notification */
  70         for (i = 0; i < data->ports; i++) {
  71                 if (data->overcurrent_pin[i])
  72                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
  73         }
  74
  75         usbh_data = *data;
  76         platform_device_register(&at91rm9200_usbh_device);
  77 }
  78 #else
  79 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
  80 #endif
  81
  82
  83 /* --------------------------------------------------------------------
  84  *  USB Device (Gadget)
  85  * -------------------------------------------------------------------- */
  86
  87 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
  88 static struct at91_udc_data udc_data;
  89
  90 static struct resource udc_resources[] = {
  91         [0] = {
  92                 .start  = AT91RM9200_BASE_UDP,
  93                 .end    = AT91RM9200_BASE_UDP + SZ_16K - 1,
  94                 .flags  = IORESOURCE_MEM,
  95         },
  96         [1] = {
  97                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
  98                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
  99                 .flags  = IORESOURCE_IRQ,
 100         },
 101 };
 102
 103 static struct platform_device at91rm9200_udc_device = {
 104         .name           = "at91_udc",
 105         .id             = -1,
 106         .dev            = {
 107                                 .platform_data          = &udc_data,
 108         },
 109         .resource       = udc_resources,
 110         .num_resources  = ARRAY_SIZE(udc_resources),
 111 };
 112
 113 void __init at91_add_device_udc(struct at91_udc_data *data)
 114 {
 115         if (!data)
 116                 return;
 117
 118         if (gpio_is_valid(data->vbus_pin)) {
 119                 at91_set_gpio_input(data->vbus_pin, 0);
 120                 at91_set_deglitch(data->vbus_pin, 1);
 121         }
 122         if (gpio_is_valid(data->pullup_pin))
 123                 at91_set_gpio_output(data->pullup_pin, 0);
 124
 125         udc_data = *data;
 126         platform_device_register(&at91rm9200_udc_device);
 127 }
 128 #else
 129 void __init at91_add_device_udc(struct at91_udc_data *data) {}
 130 #endif
 131
 132
 133 /* --------------------------------------------------------------------
 134  *  Ethernet
 135  * -------------------------------------------------------------------- */
 136
 137 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
 138 static u64 eth_dmamask = DMA_BIT_MASK(32);
 139 static struct macb_platform_data eth_data;
 140
 141 static struct resource eth_resources[] = {
 142         [0] = {
 143                 .start  = AT91RM9200_BASE_EMAC,
 144                 .end    = AT91RM9200_BASE_EMAC + SZ_16K - 1,
 145                 .flags  = IORESOURCE_MEM,
 146         },
 147         [1] = {
 148                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
 149                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
 150                 .flags  = IORESOURCE_IRQ,
 151         },
 152 };
 153
 154 static struct platform_device at91rm9200_eth_device = {
 155         .name           = "at91_ether",
 156         .id             = -1,
 157         .dev            = {
 158                                 .dma_mask               = &eth_dmamask,
 159                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 160                                 .platform_data          = &eth_data,
 161         },
 162         .resource       = eth_resources,
 163         .num_resources  = ARRAY_SIZE(eth_resources),
 164 };
 165
 166 void __init at91_add_device_eth(struct macb_platform_data *data)
 167 {
 168         if (!data)
 169                 return;
 170
 171         if (gpio_is_valid(data->phy_irq_pin)) {
 172                 at91_set_gpio_input(data->phy_irq_pin, 0);
 173                 at91_set_deglitch(data->phy_irq_pin, 1);
 174         }
 175
 176         /* Pins used for MII and RMII */
 177         at91_set_A_periph(AT91_PIN_PA16, 0);    /* EMDIO */
 178         at91_set_A_periph(AT91_PIN_PA15, 0);    /* EMDC */
 179         at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERXER */
 180         at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
 181         at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
 182         at91_set_A_periph(AT91_PIN_PA11, 0);    /* ECRS_ECRSDV */
 183         at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX1 */
 184         at91_set_A_periph(AT91_PIN_PA9, 0);     /* ETX0 */
 185         at91_set_A_periph(AT91_PIN_PA8, 0);     /* ETXEN */
 186         at91_set_A_periph(AT91_PIN_PA7, 0);     /* ETXCK_EREFCK */
 187
 188         if (!data->is_rmii) {
 189                 at91_set_B_periph(AT91_PIN_PB19, 0);    /* ERXCK */
 190                 at91_set_B_periph(AT91_PIN_PB18, 0);    /* ECOL */
 191                 at91_set_B_periph(AT91_PIN_PB17, 0);    /* ERXDV */
 192                 at91_set_B_periph(AT91_PIN_PB16, 0);    /* ERX3 */
 193                 at91_set_B_periph(AT91_PIN_PB15, 0);    /* ERX2 */
 194                 at91_set_B_periph(AT91_PIN_PB14, 0);    /* ETXER */
 195                 at91_set_B_periph(AT91_PIN_PB13, 0);    /* ETX3 */
 196                 at91_set_B_periph(AT91_PIN_PB12, 0);    /* ETX2 */
 197         }
 198
 199         eth_data = *data;
 200         platform_device_register(&at91rm9200_eth_device);
 201 }
 202 #else
 203 void __init at91_add_device_eth(struct macb_platform_data *data) {}
 204 #endif
 205
 206
 207 /* --------------------------------------------------------------------
 208  *  Compact Flash / PCMCIA
 209  * -------------------------------------------------------------------- */
 210
 211 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
 212 static struct at91_cf_data cf_data;
 213
 214 #define CF_BASE         AT91_CHIPSELECT_4
 215
 216 static struct resource cf_resources[] = {
 217         [0] = {
 218                 .start  = CF_BASE,
 219                 /* ties up CS4, CS5 and CS6 */
 220                 .end    = CF_BASE + (0x30000000 - 1),
 221                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
 222         },
 223 };
 224
 225 static struct platform_device at91rm9200_cf_device = {
 226         .name           = "at91_cf",
 227         .id             = -1,
 228         .dev            = {
 229                                 .platform_data          = &cf_data,
 230         },
 231         .resource       = cf_resources,
 232         .num_resources  = ARRAY_SIZE(cf_resources),
 233 };
 234
 235 void __init at91_add_device_cf(struct at91_cf_data *data)
 236 {
 237         unsigned int csa;
 238
 239         if (!data)
 240                 return;
 241
 242         data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
 243
 244         /* CF takes over CS4, CS5, CS6 */
 245         csa = at91_ramc_read(0, AT91_EBI_CSA);
 246         at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
 247
 248         /*
 249          * Static memory controller timing adjustments.
 250          * REVISIT:  these timings are in terms of MCK cycles, so
 251          * when MCK changes (cpufreq etc) so must these values...
 252          */
 253         at91_ramc_write(0, AT91_SMC_CSR(4),
 254                                   AT91_SMC_ACSS_STD
 255                                 | AT91_SMC_DBW_16
 256                                 | AT91_SMC_BAT
 257                                 | AT91_SMC_WSEN
 258                                 | AT91_SMC_NWS_(32)     /* wait states */
 259                                 | AT91_SMC_RWSETUP_(6)  /* setup time */
 260                                 | AT91_SMC_RWHOLD_(4)   /* hold time */
 261         );
 262
 263         /* input/irq */
 264         if (gpio_is_valid(data->irq_pin)) {
 265                 at91_set_gpio_input(data->irq_pin, 1);
 266                 at91_set_deglitch(data->irq_pin, 1);
 267         }
 268         at91_set_gpio_input(data->det_pin, 1);
 269         at91_set_deglitch(data->det_pin, 1);
 270
 271         /* outputs, initially off */
 272         if (gpio_is_valid(data->vcc_pin))
 273                 at91_set_gpio_output(data->vcc_pin, 0);
 274         at91_set_gpio_output(data->rst_pin, 0);
 275
 276         /* force poweron defaults for these pins ... */
 277         at91_set_A_periph(AT91_PIN_PC9, 0);     /* A25/CFRNW */
 278         at91_set_A_periph(AT91_PIN_PC10, 0);    /* NCS4/CFCS */
 279         at91_set_A_periph(AT91_PIN_PC11, 0);    /* NCS5/CFCE1 */
 280         at91_set_A_periph(AT91_PIN_PC12, 0);    /* NCS6/CFCE2 */
 281
 282         /* nWAIT is _not_ a default setting */
 283         at91_set_A_periph(AT91_PIN_PC6, 1);     /* nWAIT */
 284
 285         cf_data = *data;
 286         platform_device_register(&at91rm9200_cf_device);
 287 }
 288 #else
 289 void __init at91_add_device_cf(struct at91_cf_data *data) {}
 290 #endif
 291
 292
 293 /* --------------------------------------------------------------------
 294  *  MMC / SD
 295  * -------------------------------------------------------------------- */
 296
 297 #if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 298 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 299 static struct mci_platform_data mmc_data;
 300
 301 static struct resource mmc_resources[] = {
 302         [0] = {
 303                 .start  = AT91RM9200_BASE_MCI,
 304                 .end    = AT91RM9200_BASE_MCI + SZ_16K - 1,
 305                 .flags  = IORESOURCE_MEM,
 306         },
 307         [1] = {
 308                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
 309                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
 310                 .flags  = IORESOURCE_IRQ,
 311         },
 312 };
 313
 314 static struct platform_device at91rm9200_mmc_device = {
 315         .name           = "atmel_mci",
 316         .id             = -1,
 317         .dev            = {
 318                                 .dma_mask               = &mmc_dmamask,
 319                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 320                                 .platform_data          = &mmc_data,
 321         },
 322         .resource       = mmc_resources,
 323         .num_resources  = ARRAY_SIZE(mmc_resources),
 324 };
 325
 326 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 327 {
 328         unsigned int i;
 329         unsigned int slot_count = 0;
 330
 331         if (!data)
 332                 return;
 333
 334         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 335
 336                 if (!data->slot[i].bus_width)
 337                         continue;
 338
 339                 /* input/irq */
 340                 if (gpio_is_valid(data->slot[i].detect_pin)) {
 341                         at91_set_gpio_input(data->slot[i].detect_pin, 1);
 342                         at91_set_deglitch(data->slot[i].detect_pin, 1);
 343                 }
 344                 if (gpio_is_valid(data->slot[i].wp_pin))
 345                         at91_set_gpio_input(data->slot[i].wp_pin, 1);
 346
 347                 switch (i) {
 348                 case 0:                                 /* slot A */
 349                         /* CMD */
 350                         at91_set_A_periph(AT91_PIN_PA28, 1);
 351                         /* DAT0, maybe DAT1..DAT3 */
 352                         at91_set_A_periph(AT91_PIN_PA29, 1);
 353                         if (data->slot[i].bus_width == 4) {
 354                                 at91_set_B_periph(AT91_PIN_PB3, 1);
 355                                 at91_set_B_periph(AT91_PIN_PB4, 1);
 356                                 at91_set_B_periph(AT91_PIN_PB5, 1);
 357                         }
 358                         slot_count++;
 359                         break;
 360                 case 1:                                 /* slot B */
 361                         /* CMD */
 362                         at91_set_B_periph(AT91_PIN_PA8, 1);
 363                         /* DAT0, maybe DAT1..DAT3 */
 364                         at91_set_B_periph(AT91_PIN_PA9, 1);
 365                         if (data->slot[i].bus_width == 4) {
 366                                 at91_set_B_periph(AT91_PIN_PA10, 1);
 367                                 at91_set_B_periph(AT91_PIN_PA11, 1);
 368                                 at91_set_B_periph(AT91_PIN_PA12, 1);
 369                         }
 370                         slot_count++;
 371                         break;
 372                 default:
 373                         printk(KERN_ERR
 374                                "AT91: SD/MMC slot %d not available\n", i);
 375                         break;
 376                 }
 377                 if (slot_count) {
 378                         /* CLK */
 379                         at91_set_A_periph(AT91_PIN_PA27, 0);
 380
 381                         mmc_data = *data;
 382                         platform_device_register(&at91rm9200_mmc_device);
 383                 }
 384         }
 385
 386 }
 387 #else
 388 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 389 #endif
 390
 391
 392 /* --------------------------------------------------------------------
 393  *  NAND / SmartMedia
 394  * -------------------------------------------------------------------- */
 395
 396 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 397 static struct atmel_nand_data nand_data;
 398
 399 #define NAND_BASE       AT91_CHIPSELECT_3
 400
 401 static struct resource nand_resources[] = {
 402         {
 403                 .start  = NAND_BASE,
 404                 .end    = NAND_BASE + SZ_256M - 1,
 405                 .flags  = IORESOURCE_MEM,
 406         }
 407 };
 408
 409 static struct platform_device at91rm9200_nand_device = {
 410         .name           = "atmel_nand",
 411         .id             = -1,
 412         .dev            = {
 413                                 .platform_data  = &nand_data,
 414         },
 415         .resource       = nand_resources,
 416         .num_resources  = ARRAY_SIZE(nand_resources),
 417 };
 418
 419 void __init at91_add_device_nand(struct atmel_nand_data *data)
 420 {
 421         unsigned int csa;
 422
 423         if (!data)
 424                 return;
 425
 426         /* enable the address range of CS3 */
 427         csa = at91_ramc_read(0, AT91_EBI_CSA);
 428         at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
 429
 430         /* set the bus interface characteristics */
 431         at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
 432                 | AT91_SMC_NWS_(5)
 433                 | AT91_SMC_TDF_(1)
 434                 | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
 435                 | AT91_SMC_RWHOLD_(1)   /* tDH Data Hold Time 20 - ns */
 436         );
 437
 438         /* enable pin */
 439         if (gpio_is_valid(data->enable_pin))
 440                 at91_set_gpio_output(data->enable_pin, 1);
 441
 442         /* ready/busy pin */
 443         if (gpio_is_valid(data->rdy_pin))
 444                 at91_set_gpio_input(data->rdy_pin, 1);
 445
 446         /* card detect pin */
 447         if (gpio_is_valid(data->det_pin))
 448                 at91_set_gpio_input(data->det_pin, 1);
 449
 450         at91_set_A_periph(AT91_PIN_PC1, 0);             /* SMOE */
 451         at91_set_A_periph(AT91_PIN_PC3, 0);             /* SMWE */
 452
 453         nand_data = *data;
 454         platform_device_register(&at91rm9200_nand_device);
 455 }
 456 #else
 457 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 458 #endif
 459
 460
 461 /* --------------------------------------------------------------------
 462  *  TWI (i2c)
 463  * -------------------------------------------------------------------- */
 464
 465 /*
 466  * Prefer the GPIO code since the TWI controller isn't robust
 467  * (gets overruns and underruns under load) and can only issue
 468  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 469  */
 470 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 471
 472 static struct i2c_gpio_platform_data pdata = {
 473         .sda_pin                = AT91_PIN_PA25,
 474         .sda_is_open_drain      = 1,
 475         .scl_pin                = AT91_PIN_PA26,
 476         .scl_is_open_drain      = 1,
 477         .udelay                 = 2,            /* ~100 kHz */
 478 };
 479
 480 static struct platform_device at91rm9200_twi_device = {
 481         .name                   = "i2c-gpio",
 482         .id                     = 0,
 483         .dev.platform_data      = &pdata,
 484 };
 485
 486 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 487 {
 488         at91_set_GPIO_periph(AT91_PIN_PA25, 1);         /* TWD (SDA) */
 489         at91_set_multi_drive(AT91_PIN_PA25, 1);
 490
 491         at91_set_GPIO_periph(AT91_PIN_PA26, 1);         /* TWCK (SCL) */
 492         at91_set_multi_drive(AT91_PIN_PA26, 1);
 493
 494         i2c_register_board_info(0, devices, nr_devices);
 495         platform_device_register(&at91rm9200_twi_device);
 496 }
 497
 498 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 499
 500 static struct resource twi_resources[] = {
 501         [0] = {
 502                 .start  = AT91RM9200_BASE_TWI,
 503                 .end    = AT91RM9200_BASE_TWI + SZ_16K - 1,
 504                 .flags  = IORESOURCE_MEM,
 505         },
 506         [1] = {
 507                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
 508                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
 509                 .flags  = IORESOURCE_IRQ,
 510         },
 511 };
 512
 513 static struct platform_device at91rm9200_twi_device = {
 514         .name           = "i2c-at91rm9200",
 515         .id             = 0,
 516         .resource       = twi_resources,
 517         .num_resources  = ARRAY_SIZE(twi_resources),
 518 };
 519
 520 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 521 {
 522         /* pins used for TWI interface */
 523         at91_set_A_periph(AT91_PIN_PA25, 0);            /* TWD */
 524         at91_set_multi_drive(AT91_PIN_PA25, 1);
 525
 526         at91_set_A_periph(AT91_PIN_PA26, 0);            /* TWCK */
 527         at91_set_multi_drive(AT91_PIN_PA26, 1);
 528
 529         i2c_register_board_info(0, devices, nr_devices);
 530         platform_device_register(&at91rm9200_twi_device);
 531 }
 532 #else
 533 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
 534 #endif
 535
 536
 537 /* --------------------------------------------------------------------
 538  *  SPI
 539  * -------------------------------------------------------------------- */
 540
 541 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 542 static u64 spi_dmamask = DMA_BIT_MASK(32);
 543
 544 static struct resource spi_resources[] = {
 545         [0] = {
 546                 .start  = AT91RM9200_BASE_SPI,
 547                 .end    = AT91RM9200_BASE_SPI + SZ_16K - 1,
 548                 .flags  = IORESOURCE_MEM,
 549         },
 550         [1] = {
 551                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
 552                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
 553                 .flags  = IORESOURCE_IRQ,
 554         },
 555 };
 556
 557 static struct platform_device at91rm9200_spi_device = {
 558         .name           = "atmel_spi",
 559         .id             = 0,
 560         .dev            = {
 561                                 .dma_mask               = &spi_dmamask,
 562                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 563         },
 564         .resource       = spi_resources,
 565         .num_resources  = ARRAY_SIZE(spi_resources),
 566 };
 567
 568 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
 569
 570 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 571 {
 572         int i;
 573         unsigned long cs_pin;
 574
 575         at91_set_A_periph(AT91_PIN_PA0, 0);     /* MISO */
 576         at91_set_A_periph(AT91_PIN_PA1, 0);     /* MOSI */
 577         at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPCK */
 578
 579         /* Enable SPI chip-selects */
 580         for (i = 0; i < nr_devices; i++) {
 581                 if (devices[i].controller_data)
 582                         cs_pin = (unsigned long) devices[i].controller_data;
 583                 else
 584                         cs_pin = spi_standard_cs[devices[i].chip_select];
 585
 586                 if (devices[i].chip_select == 0)        /* for CS0 errata */
 587                         at91_set_A_periph(cs_pin, 0);
 588                 else
 589                         at91_set_gpio_output(cs_pin, 1);
 590
 591
 592                 /* pass chip-select pin to driver */
 593                 devices[i].controller_data = (void *) cs_pin;
 594         }
 595
 596         spi_register_board_info(devices, nr_devices);
 597         platform_device_register(&at91rm9200_spi_device);
 598 }
 599 #else
 600 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 601 #endif
 602
 603
 604 /* --------------------------------------------------------------------
 605  *  Timer/Counter blocks
 606  * -------------------------------------------------------------------- */
 607
 608 #ifdef CONFIG_ATMEL_TCLIB
 609
 610 static struct resource tcb0_resources[] = {
 611         [0] = {
 612                 .start  = AT91RM9200_BASE_TCB0,
 613                 .end    = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
 614                 .flags  = IORESOURCE_MEM,
 615         },
 616         [1] = {
 617                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
 618                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
 619                 .flags  = IORESOURCE_IRQ,
 620         },
 621         [2] = {
 622                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
 623                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
 624                 .flags  = IORESOURCE_IRQ,
 625         },
 626         [3] = {
 627                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
 628                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
 629                 .flags  = IORESOURCE_IRQ,
 630         },
 631 };
 632
 633 static struct platform_device at91rm9200_tcb0_device = {
 634         .name           = "atmel_tcb",
 635         .id             = 0,
 636         .resource       = tcb0_resources,
 637         .num_resources  = ARRAY_SIZE(tcb0_resources),
 638 };
 639
 640 static struct resource tcb1_resources[] = {
 641         [0] = {
 642                 .start  = AT91RM9200_BASE_TCB1,
 643                 .end    = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
 644                 .flags  = IORESOURCE_MEM,
 645         },
 646         [1] = {
 647                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
 648                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
 649                 .flags  = IORESOURCE_IRQ,
 650         },
 651         [2] = {
 652                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
 653                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
 654                 .flags  = IORESOURCE_IRQ,
 655         },
 656         [3] = {
 657                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
 658                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
 659                 .flags  = IORESOURCE_IRQ,
 660         },
 661 };
 662
 663 static struct platform_device at91rm9200_tcb1_device = {
 664         .name           = "atmel_tcb",
 665         .id             = 1,
 666         .resource       = tcb1_resources,
 667         .num_resources  = ARRAY_SIZE(tcb1_resources),
 668 };
 669
 670 static void __init at91_add_device_tc(void)
 671 {
 672         platform_device_register(&at91rm9200_tcb0_device);
 673         platform_device_register(&at91rm9200_tcb1_device);
 674 }
 675 #else
 676 static void __init at91_add_device_tc(void) { }
 677 #endif
 678
 679
 680 /* --------------------------------------------------------------------
 681  *  RTC
 682  * -------------------------------------------------------------------- */
 683
 684 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
 685 static struct resource rtc_resources[] = {
 686         [0] = {
 687                 .start  = AT91RM9200_BASE_RTC,
 688                 .end    = AT91RM9200_BASE_RTC + SZ_256 - 1,
 689                 .flags  = IORESOURCE_MEM,
 690         },
 691         [1] = {
 692                 .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
 693                 .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
 694                 .flags  = IORESOURCE_IRQ,
 695         },
 696 };
 697
 698 static struct platform_device at91rm9200_rtc_device = {
 699         .name           = "at91_rtc",
 700         .id             = -1,
 701         .resource       = rtc_resources,
 702         .num_resources  = ARRAY_SIZE(rtc_resources),
 703 };
 704
 705 static void __init at91_add_device_rtc(void)
 706 {
 707         platform_device_register(&at91rm9200_rtc_device);
 708 }
 709 #else
 710 static void __init at91_add_device_rtc(void) {}
 711 #endif
 712
 713
 714 /* --------------------------------------------------------------------
 715  *  Watchdog
 716  * -------------------------------------------------------------------- */
 717
 718 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
 719 static struct platform_device at91rm9200_wdt_device = {
 720         .name           = "at91_wdt",
 721         .id             = -1,
 722         .num_resources  = 0,
 723 };
 724
 725 static void __init at91_add_device_watchdog(void)
 726 {
 727         platform_device_register(&at91rm9200_wdt_device);
 728 }
 729 #else
 730 static void __init at91_add_device_watchdog(void) {}
 731 #endif
 732
 733
 734 /* --------------------------------------------------------------------
 735  *  SSC -- Synchronous Serial Controller
 736  * -------------------------------------------------------------------- */
 737
 738 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
 739 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
 740
 741 static struct resource ssc0_resources[] = {
 742         [0] = {
 743                 .start  = AT91RM9200_BASE_SSC0,
 744                 .end    = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
 745                 .flags  = IORESOURCE_MEM,
 746         },
 747         [1] = {
 748                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
 749                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
 750                 .flags  = IORESOURCE_IRQ,
 751         },
 752 };
 753
 754 static struct platform_device at91rm9200_ssc0_device = {
 755         .name   = "ssc",
 756         .id     = 0,
 757         .dev    = {
 758                 .dma_mask               = &ssc0_dmamask,
 759                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 760         },
 761         .resource       = ssc0_resources,
 762         .num_resources  = ARRAY_SIZE(ssc0_resources),
 763 };
 764
 765 static inline void configure_ssc0_pins(unsigned pins)
 766 {
 767         if (pins & ATMEL_SSC_TF)
 768                 at91_set_A_periph(AT91_PIN_PB0, 1);
 769         if (pins & ATMEL_SSC_TK)
 770                 at91_set_A_periph(AT91_PIN_PB1, 1);
 771         if (pins & ATMEL_SSC_TD)
 772                 at91_set_A_periph(AT91_PIN_PB2, 1);
 773         if (pins & ATMEL_SSC_RD)
 774                 at91_set_A_periph(AT91_PIN_PB3, 1);
 775         if (pins & ATMEL_SSC_RK)
 776                 at91_set_A_periph(AT91_PIN_PB4, 1);
 777         if (pins & ATMEL_SSC_RF)
 778                 at91_set_A_periph(AT91_PIN_PB5, 1);
 779 }
 780
 781 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
 782
 783 static struct resource ssc1_resources[] = {
 784         [0] = {
 785                 .start  = AT91RM9200_BASE_SSC1,
 786                 .end    = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
 787                 .flags  = IORESOURCE_MEM,
 788         },
 789         [1] = {
 790                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
 791                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
 792                 .flags  = IORESOURCE_IRQ,
 793         },
 794 };
 795
 796 static struct platform_device at91rm9200_ssc1_device = {
 797         .name   = "ssc",
 798         .id     = 1,
 799         .dev    = {
 800                 .dma_mask               = &ssc1_dmamask,
 801                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 802         },
 803         .resource       = ssc1_resources,
 804         .num_resources  = ARRAY_SIZE(ssc1_resources),
 805 };
 806
 807 static inline void configure_ssc1_pins(unsigned pins)
 808 {
 809         if (pins & ATMEL_SSC_TF)
 810                 at91_set_A_periph(AT91_PIN_PB6, 1);
 811         if (pins & ATMEL_SSC_TK)
 812                 at91_set_A_periph(AT91_PIN_PB7, 1);
 813         if (pins & ATMEL_SSC_TD)
 814                 at91_set_A_periph(AT91_PIN_PB8, 1);
 815         if (pins & ATMEL_SSC_RD)
 816                 at91_set_A_periph(AT91_PIN_PB9, 1);
 817         if (pins & ATMEL_SSC_RK)
 818                 at91_set_A_periph(AT91_PIN_PB10, 1);
 819         if (pins & ATMEL_SSC_RF)
 820                 at91_set_A_periph(AT91_PIN_PB11, 1);
 821 }
 822
 823 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
 824
 825 static struct resource ssc2_resources[] = {
 826         [0] = {
 827                 .start  = AT91RM9200_BASE_SSC2,
 828                 .end    = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
 829                 .flags  = IORESOURCE_MEM,
 830         },
 831         [1] = {
 832                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
 833                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
 834                 .flags  = IORESOURCE_IRQ,
 835         },
 836 };
 837
 838 static struct platform_device at91rm9200_ssc2_device = {
 839         .name   = "ssc",
 840         .id     = 2,
 841         .dev    = {
 842                 .dma_mask               = &ssc2_dmamask,
 843                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 844         },
 845         .resource       = ssc2_resources,
 846         .num_resources  = ARRAY_SIZE(ssc2_resources),
 847 };
 848
 849 static inline void configure_ssc2_pins(unsigned pins)
 850 {
 851         if (pins & ATMEL_SSC_TF)
 852                 at91_set_A_periph(AT91_PIN_PB12, 1);
 853         if (pins & ATMEL_SSC_TK)
 854                 at91_set_A_periph(AT91_PIN_PB13, 1);
 855         if (pins & ATMEL_SSC_TD)
 856                 at91_set_A_periph(AT91_PIN_PB14, 1);
 857         if (pins & ATMEL_SSC_RD)
 858                 at91_set_A_periph(AT91_PIN_PB15, 1);
 859         if (pins & ATMEL_SSC_RK)
 860                 at91_set_A_periph(AT91_PIN_PB16, 1);
 861         if (pins & ATMEL_SSC_RF)
 862                 at91_set_A_periph(AT91_PIN_PB17, 1);
 863 }
 864
 865 /*
 866  * SSC controllers are accessed through library code, instead of any
 867  * kind of all-singing/all-dancing driver.  For example one could be
 868  * used by a particular I2S audio codec's driver, while another one
 869  * on the same system might be used by a custom data capture driver.
 870  */
 871 void __init at91_add_device_ssc(unsigned id, unsigned pins)
 872 {
 873         struct platform_device *pdev;
 874
 875         /*
 876          * NOTE: caller is responsible for passing information matching
 877          * "pins" to whatever will be using each particular controller.
 878          */
 879         switch (id) {
 880         case AT91RM9200_ID_SSC0:
 881                 pdev = &at91rm9200_ssc0_device;
 882                 configure_ssc0_pins(pins);
 883                 break;
 884         case AT91RM9200_ID_SSC1:
 885                 pdev = &at91rm9200_ssc1_device;
 886                 configure_ssc1_pins(pins);
 887                 break;
 888         case AT91RM9200_ID_SSC2:
 889                 pdev = &at91rm9200_ssc2_device;
 890                 configure_ssc2_pins(pins);
 891                 break;
 892         default:
 893                 return;
 894         }
 895
 896         platform_device_register(pdev);
 897 }
 898
 899 #else
 900 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 901 #endif
 902
 903
 904 /* --------------------------------------------------------------------
 905  *  UART
 906  * -------------------------------------------------------------------- */
 907
 908 #if defined(CONFIG_SERIAL_ATMEL)
 909 static struct resource dbgu_resources[] = {
 910         [0] = {
 911                 .start  = AT91RM9200_BASE_DBGU,
 912                 .end    = AT91RM9200_BASE_DBGU + SZ_512 - 1,
 913                 .flags  = IORESOURCE_MEM,
 914         },
 915         [1] = {
 916                 .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
 917                 .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
 918                 .flags  = IORESOURCE_IRQ,
 919         },
 920 };
 921
 922 static struct atmel_uart_data dbgu_data = {
 923         .use_dma_tx     = 0,
 924         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
 925 };
 926
 927 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
 928
 929 static struct platform_device at91rm9200_dbgu_device = {
 930         .name           = "atmel_usart",
 931         .id             = 0,
 932         .dev            = {
 933                                 .dma_mask               = &dbgu_dmamask,
 934                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 935                                 .platform_data          = &dbgu_data,
 936         },
 937         .resource       = dbgu_resources,
 938         .num_resources  = ARRAY_SIZE(dbgu_resources),
 939 };
 940
 941 static inline void configure_dbgu_pins(void)
 942 {
 943         at91_set_A_periph(AT91_PIN_PA30, 0);            /* DRXD */
 944         at91_set_A_periph(AT91_PIN_PA31, 1);            /* DTXD */
 945 }
 946
 947 static struct resource uart0_resources[] = {
 948         [0] = {
 949                 .start  = AT91RM9200_BASE_US0,
 950                 .end    = AT91RM9200_BASE_US0 + SZ_16K - 1,
 951                 .flags  = IORESOURCE_MEM,
 952         },
 953         [1] = {
 954                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
 955                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
 956                 .flags  = IORESOURCE_IRQ,
 957         },
 958 };
 959
 960 static struct atmel_uart_data uart0_data = {
 961         .use_dma_tx     = 1,
 962         .use_dma_rx     = 1,
 963 };
 964
 965 static u64 uart0_dmamask = DMA_BIT_MASK(32);
 966
 967 static struct platform_device at91rm9200_uart0_device = {
 968         .name           = "atmel_usart",
 969         .id             = 1,
 970         .dev            = {
 971                                 .dma_mask               = &uart0_dmamask,
 972                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 973                                 .platform_data          = &uart0_data,
 974         },
 975         .resource       = uart0_resources,
 976         .num_resources  = ARRAY_SIZE(uart0_resources),
 977 };
 978
 979 static inline void configure_usart0_pins(unsigned pins)
 980 {
 981         at91_set_A_periph(AT91_PIN_PA17, 1);            /* TXD0 */
 982         at91_set_A_periph(AT91_PIN_PA18, 0);            /* RXD0 */
 983
 984         if (pins & ATMEL_UART_CTS)
 985                 at91_set_A_periph(AT91_PIN_PA20, 0);    /* CTS0 */
 986
 987         if (pins & ATMEL_UART_RTS) {
 988                 /*
 989                  * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
 990                  *  We need to drive the pin manually.  Default is off (RTS is active low).
 991                  */
 992                 at91_set_gpio_output(AT91_PIN_PA21, 1);
 993         }
 994 }
 995
 996 static struct resource uart1_resources[] = {
 997         [0] = {
 998                 .start  = AT91RM9200_BASE_US1,
 999                 .end    = AT91RM9200_BASE_US1 + SZ_16K - 1,
1000                 .flags  = IORESOURCE_MEM,
1001         },
1002         [1] = {
1003                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1004                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1005                 .flags  = IORESOURCE_IRQ,
1006         },
1007 };
1008
1009 static struct atmel_uart_data uart1_data = {
1010         .use_dma_tx     = 1,
1011         .use_dma_rx     = 1,
1012 };
1013
1014 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1015
1016 static struct platform_device at91rm9200_uart1_device = {
1017         .name           = "atmel_usart",
1018         .id             = 2,
1019         .dev            = {
1020                                 .dma_mask               = &uart1_dmamask,
1021                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1022                                 .platform_data          = &uart1_data,
1023         },
1024         .resource       = uart1_resources,
1025         .num_resources  = ARRAY_SIZE(uart1_resources),
1026 };
1027
1028 static inline void configure_usart1_pins(unsigned pins)
1029 {
1030         at91_set_A_periph(AT91_PIN_PB20, 1);            /* TXD1 */
1031         at91_set_A_periph(AT91_PIN_PB21, 0);            /* RXD1 */
1032
1033         if (pins & ATMEL_UART_RI)
1034                 at91_set_A_periph(AT91_PIN_PB18, 0);    /* RI1 */
1035         if (pins & ATMEL_UART_DTR)
1036                 at91_set_A_periph(AT91_PIN_PB19, 0);    /* DTR1 */
1037         if (pins & ATMEL_UART_DCD)
1038                 at91_set_A_periph(AT91_PIN_PB23, 0);    /* DCD1 */
1039         if (pins & ATMEL_UART_CTS)
1040                 at91_set_A_periph(AT91_PIN_PB24, 0);    /* CTS1 */
1041         if (pins & ATMEL_UART_DSR)
1042                 at91_set_A_periph(AT91_PIN_PB25, 0);    /* DSR1 */
1043         if (pins & ATMEL_UART_RTS)
1044                 at91_set_A_periph(AT91_PIN_PB26, 0);    /* RTS1 */
1045 }
1046
1047 static struct resource uart2_resources[] = {
1048         [0] = {
1049                 .start  = AT91RM9200_BASE_US2,
1050                 .end    = AT91RM9200_BASE_US2 + SZ_16K - 1,
1051                 .flags  = IORESOURCE_MEM,
1052         },
1053         [1] = {
1054                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1055                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1056                 .flags  = IORESOURCE_IRQ,
1057         },
1058 };
1059
1060 static struct atmel_uart_data uart2_data = {
1061         .use_dma_tx     = 1,
1062         .use_dma_rx     = 1,
1063 };
1064
1065 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1066
1067 static struct platform_device at91rm9200_uart2_device = {
1068         .name           = "atmel_usart",
1069         .id             = 3,
1070         .dev            = {
1071                                 .dma_mask               = &uart2_dmamask,
1072                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1073                                 .platform_data          = &uart2_data,
1074         },
1075         .resource       = uart2_resources,
1076         .num_resources  = ARRAY_SIZE(uart2_resources),
1077 };
1078
1079 static inline void configure_usart2_pins(unsigned pins)
1080 {
1081         at91_set_A_periph(AT91_PIN_PA22, 0);            /* RXD2 */
1082         at91_set_A_periph(AT91_PIN_PA23, 1);            /* TXD2 */
1083
1084         if (pins & ATMEL_UART_CTS)
1085                 at91_set_B_periph(AT91_PIN_PA30, 0);    /* CTS2 */
1086         if (pins & ATMEL_UART_RTS)
1087                 at91_set_B_periph(AT91_PIN_PA31, 0);    /* RTS2 */
1088 }
1089
1090 static struct resource uart3_resources[] = {
1091         [0] = {
1092                 .start  = AT91RM9200_BASE_US3,
1093                 .end    = AT91RM9200_BASE_US3 + SZ_16K - 1,
1094                 .flags  = IORESOURCE_MEM,
1095         },
1096         [1] = {
1097                 .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1098                 .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1099                 .flags  = IORESOURCE_IRQ,
1100         },
1101 };
1102
1103 static struct atmel_uart_data uart3_data = {
1104         .use_dma_tx     = 1,
1105         .use_dma_rx     = 1,
1106 };
1107
1108 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1109
1110 static struct platform_device at91rm9200_uart3_device = {
1111         .name           = "atmel_usart",
1112         .id             = 4,
1113         .dev            = {
1114                                 .dma_mask               = &uart3_dmamask,
1115                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1116                                 .platform_data          = &uart3_data,
1117         },
1118         .resource       = uart3_resources,
1119         .num_resources  = ARRAY_SIZE(uart3_resources),
1120 };
1121
1122 static inline void configure_usart3_pins(unsigned pins)
1123 {
1124         at91_set_B_periph(AT91_PIN_PA5, 1);             /* TXD3 */
1125         at91_set_B_periph(AT91_PIN_PA6, 0);             /* RXD3 */
1126
1127         if (pins & ATMEL_UART_CTS)
1128                 at91_set_B_periph(AT91_PIN_PB1, 0);     /* CTS3 */
1129         if (pins & ATMEL_UART_RTS)
1130                 at91_set_B_periph(AT91_PIN_PB0, 0);     /* RTS3 */
1131 }
1132
1133 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1134
1135 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1136 {
1137         struct platform_device *pdev;
1138         struct atmel_uart_data *pdata;
1139
1140         switch (id) {
1141                 case 0:         /* DBGU */
1142                         pdev = &at91rm9200_dbgu_device;
1143                         configure_dbgu_pins();
1144                         break;
1145                 case AT91RM9200_ID_US0:
1146                         pdev = &at91rm9200_uart0_device;
1147                         configure_usart0_pins(pins);
1148                         break;
1149                 case AT91RM9200_ID_US1:
1150                         pdev = &at91rm9200_uart1_device;
1151                         configure_usart1_pins(pins);
1152                         break;
1153                 case AT91RM9200_ID_US2:
1154                         pdev = &at91rm9200_uart2_device;
1155                         configure_usart2_pins(pins);
1156                         break;
1157                 case AT91RM9200_ID_US3:
1158                         pdev = &at91rm9200_uart3_device;
1159                         configure_usart3_pins(pins);
1160                         break;
1161                 default:
1162                         return;
1163         }
1164         pdata = pdev->dev.platform_data;
1165         pdata->num = portnr;            /* update to mapped ID */
1166
1167         if (portnr < ATMEL_MAX_UART)
1168                 at91_uarts[portnr] = pdev;
1169 }
1170
1171 void __init at91_add_device_serial(void)
1172 {
1173         int i;
1174
1175         for (i = 0; i < ATMEL_MAX_UART; i++) {
1176                 if (at91_uarts[i])
1177                         platform_device_register(at91_uarts[i]);
1178         }
1179 }
1180 #else
1181 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1182 void __init at91_add_device_serial(void) {}
1183 #endif
1184
1185
1186 /* -------------------------------------------------------------------- */
1187
1188 /*
1189  * These devices are always present and don't need any board-specific
1190  * setup.
1191  */
1192 static int __init at91_add_standard_devices(void)
1193 {
1194         at91_add_device_rtc();
1195         at91_add_device_watchdog();
1196         at91_add_device_tc();
1197         return 0;
1198 }
1199
1200 arch_initcall(at91_add_standard_devices);