arch/arm/include/asm/cputype.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_ARM_CPUTYPE_H
   3 #define __ASM_ARM_CPUTYPE_H
   4
   5 #include <linux/stringify.h>
   6 #include <linux/kernel.h>
   7
   8 #define CPUID_ID        0
   9 #define CPUID_CACHETYPE 1
  10 #define CPUID_TCM       2
  11 #define CPUID_TLBTYPE   3
  12 #define CPUID_MPUIR     4
  13 #define CPUID_MPIDR     5
  14 #define CPUID_REVIDR    6
  15
  16 #ifdef CONFIG_CPU_V7M
  17 #define CPUID_EXT_PFR0  0x40
  18 #define CPUID_EXT_PFR1  0x44
  19 #define CPUID_EXT_DFR0  0x48
  20 #define CPUID_EXT_AFR0  0x4c
  21 #define CPUID_EXT_MMFR0 0x50
  22 #define CPUID_EXT_MMFR1 0x54
  23 #define CPUID_EXT_MMFR2 0x58
  24 #define CPUID_EXT_MMFR3 0x5c
  25 #define CPUID_EXT_ISAR0 0x60
  26 #define CPUID_EXT_ISAR1 0x64
  27 #define CPUID_EXT_ISAR2 0x68
  28 #define CPUID_EXT_ISAR3 0x6c
  29 #define CPUID_EXT_ISAR4 0x70
  30 #define CPUID_EXT_ISAR5 0x74
  31 #else
  32 #define CPUID_EXT_PFR0  "c1, 0"
  33 #define CPUID_EXT_PFR1  "c1, 1"
  34 #define CPUID_EXT_DFR0  "c1, 2"
  35 #define CPUID_EXT_AFR0  "c1, 3"
  36 #define CPUID_EXT_MMFR0 "c1, 4"
  37 #define CPUID_EXT_MMFR1 "c1, 5"
  38 #define CPUID_EXT_MMFR2 "c1, 6"
  39 #define CPUID_EXT_MMFR3 "c1, 7"
  40 #define CPUID_EXT_ISAR0 "c2, 0"
  41 #define CPUID_EXT_ISAR1 "c2, 1"
  42 #define CPUID_EXT_ISAR2 "c2, 2"
  43 #define CPUID_EXT_ISAR3 "c2, 3"
  44 #define CPUID_EXT_ISAR4 "c2, 4"
  45 #define CPUID_EXT_ISAR5 "c2, 5"
  46 #endif
  47
  48 #define MPIDR_SMP_BITMASK (0x3 << 30)
  49 #define MPIDR_SMP_VALUE (0x2 << 30)
  50
  51 #define MPIDR_MT_BITMASK (0x1 << 24)
  52
  53 #define MPIDR_HWID_BITMASK 0xFFFFFF
  54
  55 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  56
  57 #define MPIDR_LEVEL_BITS 8
  58 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  59 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
  60
  61 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  62         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  63
  64 #define ARM_CPU_IMP_ARM                 0x41
  65 #define ARM_CPU_IMP_DEC                 0x44
  66 #define ARM_CPU_IMP_INTEL               0x69
  67
  68 /* ARM implemented processors */
  69 #define ARM_CPU_PART_ARM1136            0x4100b360
  70 #define ARM_CPU_PART_ARM1156            0x4100b560
  71 #define ARM_CPU_PART_ARM1176            0x4100b760
  72 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  73 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  74 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  75 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  76 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  77 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  78 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  79 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  80 #define ARM_CPU_PART_CORTEX_A53         0x4100d030
  81 #define ARM_CPU_PART_CORTEX_A57         0x4100d070
  82 #define ARM_CPU_PART_CORTEX_A72         0x4100d080
  83 #define ARM_CPU_PART_CORTEX_A73         0x4100d090
  84 #define ARM_CPU_PART_CORTEX_A75         0x4100d0a0
  85 #define ARM_CPU_PART_MASK               0xff00fff0
  86
  87 /* Broadcom cores */
  88 #define ARM_CPU_PART_BRAHMA_B15         0x420000f0
  89
  90 /* DEC implemented cores */
  91 #define ARM_CPU_PART_SA1100             0x4400a110
  92
  93 /* Intel implemented cores */
  94 #define ARM_CPU_PART_SA1110             0x6900b110
  95 #define ARM_CPU_REV_SA1110_A0           0
  96 #define ARM_CPU_REV_SA1110_B0           4
  97 #define ARM_CPU_REV_SA1110_B1           5
  98 #define ARM_CPU_REV_SA1110_B2           6
  99 #define ARM_CPU_REV_SA1110_B4           8
 100
 101 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
 102 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
 103 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
 104 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
 105
 106 /* Qualcomm implemented cores */
 107 #define ARM_CPU_PART_SCORPION           0x510002d0
 108
 109 extern unsigned int processor_id;
 110 struct proc_info_list *lookup_processor(u32 midr);
 111
 112 #ifdef CONFIG_CPU_CP15
 113 #define read_cpuid(reg)                                                 \
 114         ({                                                              \
 115                 unsigned int __val;                                     \
 116                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
 117                     : "=r" (__val)                                      \
 118                     :                                                   \
 119                     : "cc");                                            \
 120                 __val;                                                  \
 121         })
 122
 123 /*
 124  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 125  * any is_smp() tests, which can cause undefined instruction aborts on
 126  * ARM1136 r0 due to the missing extended CP15 registers.
 127  */
 128 #define read_cpuid_ext(ext_reg)                                         \
 129         ({                                                              \
 130                 unsigned int __val;                                     \
 131                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 132                     : "=r" (__val)                                      \
 133                     :                                                   \
 134                     : "memory");                                        \
 135                 __val;                                                  \
 136         })
 137
 138 #elif defined(CONFIG_CPU_V7M)
 139
 140 #include <asm/io.h>
 141 #include <asm/v7m.h>
 142
 143 #define read_cpuid(reg)                                                 \
 144         ({                                                              \
 145                 WARN_ON_ONCE(1);                                        \
 146                 0;                                                      \
 147         })
 148
 149 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 150 {
 151         return readl(BASEADDR_V7M_SCB + offset);
 152 }
 153
 154 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 155
 156 /*
 157  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 158  * have cp15 so warn on other usages.
 159  */
 160 #define read_cpuid(reg)                                                 \
 161         ({                                                              \
 162                 WARN_ON_ONCE(1);                                        \
 163                 0;                                                      \
 164         })
 165
 166 #define read_cpuid_ext(reg) read_cpuid(reg)
 167
 168 #endif /* ifdef CONFIG_CPU_CP15 / else */
 169
 170 #ifdef CONFIG_CPU_CP15
 171 /*
 172  * The CPU ID never changes at run time, so we might as well tell the
 173  * compiler that it's constant.  Use this function to read the CPU ID
 174  * rather than directly reading processor_id or read_cpuid() directly.
 175  */
 176 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 177 {
 178         return read_cpuid(CPUID_ID);
 179 }
 180
 181 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 182 {
 183         return read_cpuid(CPUID_CACHETYPE);
 184 }
 185
 186 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
 187 {
 188         return read_cpuid(CPUID_MPUIR);
 189 }
 190
 191 #elif defined(CONFIG_CPU_V7M)
 192
 193 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 194 {
 195         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 196 }
 197
 198 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 199 {
 200         return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
 201 }
 202
 203 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
 204 {
 205         return readl(BASEADDR_V7M_SCB + MPU_TYPE);
 206 }
 207
 208 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 209
 210 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 211 {
 212         return processor_id;
 213 }
 214
 215 #endif /* ifdef CONFIG_CPU_CP15 / else */
 216
 217 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 218 {
 219         return (read_cpuid_id() & 0xFF000000) >> 24;
 220 }
 221
 222 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
 223 {
 224         return read_cpuid_id() & 0x0000000f;
 225 }
 226
 227 /*
 228  * The CPU part number is meaningless without referring to the CPU
 229  * implementer: implementers are free to define their own part numbers
 230  * which are permitted to clash with other implementer part numbers.
 231  */
 232 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 233 {
 234         return read_cpuid_id() & ARM_CPU_PART_MASK;
 235 }
 236
 237 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 238 {
 239         return read_cpuid_id() & 0xFFF0;
 240 }
 241
 242 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 243 {
 244         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 245 }
 246
 247 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 248 {
 249         return read_cpuid(CPUID_TCM);
 250 }
 251
 252 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 253 {
 254         return read_cpuid(CPUID_MPIDR);
 255 }
 256
 257 /* StrongARM-11x0 CPUs */
 258 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
 259 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
 260
 261 /*
 262  * Intel's XScale3 core supports some v6 features (supersections, L2)
 263  * but advertises itself as v5 as it does not support the v6 ISA.  For
 264  * this reason, we need a way to explicitly test for this type of CPU.
 265  */
 266 #ifndef CONFIG_CPU_XSC3
 267 #define cpu_is_xsc3()   0
 268 #else
 269 static inline int cpu_is_xsc3(void)
 270 {
 271         unsigned int id;
 272         id = read_cpuid_id() & 0xffffe000;
 273         /* It covers both Intel ID and Marvell ID */
 274         if ((id == 0x69056000) || (id == 0x56056000))
 275                 return 1;
 276
 277         return 0;
 278 }
 279 #endif
 280
 281 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
 282     !defined(CONFIG_CPU_MOHAWK)
 283 #define cpu_is_xscale_family() 0
 284 #else
 285 static inline int cpu_is_xscale_family(void)
 286 {
 287         unsigned int id;
 288         id = read_cpuid_id() & 0xffffe000;
 289
 290         switch (id) {
 291         case 0x69052000: /* Intel XScale 1 */
 292         case 0x69054000: /* Intel XScale 2 */
 293         case 0x69056000: /* Intel XScale 3 */
 294         case 0x56056000: /* Marvell XScale 3 */
 295         case 0x56158000: /* Marvell Mohawk */
 296                 return 1;
 297         }
 298
 299         return 0;
 300 }
 301 #endif
 302
 303 /*
 304  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 305  * but require a specical sequence for enabling coprocessors.
 306  * For this reason, we need a way to distinguish them.
 307  */
 308 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 309 static inline int cpu_is_pj4(void)
 310 {
 311         unsigned int id;
 312
 313         id = read_cpuid_id();
 314         if ((id & 0xff0fff00) == 0x560f5800)
 315                 return 1;
 316
 317         return 0;
 318 }
 319 #else
 320 #define cpu_is_pj4()    0
 321 #endif
 322
 323 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 324                                                                   int field)
 325 {
 326         int feature = (features >> field) & 15;
 327
 328         /* feature registers are signed values */
 329         if (feature > 7)
 330                 feature -= 16;
 331
 332         return feature;
 333 }
 334
 335 #define cpuid_feature_extract(reg, field) \
 336         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 337
 338 #endif