ARM: 8711/1: V7M: Add support for MPU to M-class
[sfrench/cifs-2.6.git] / arch / arm / include / asm / cputype.h
1 #ifndef __ASM_ARM_CPUTYPE_H
2 #define __ASM_ARM_CPUTYPE_H
3
4 #include <linux/stringify.h>
5 #include <linux/kernel.h>
6
7 #define CPUID_ID        0
8 #define CPUID_CACHETYPE 1
9 #define CPUID_TCM       2
10 #define CPUID_TLBTYPE   3
11 #define CPUID_MPUIR     4
12 #define CPUID_MPIDR     5
13 #define CPUID_REVIDR    6
14
15 #ifdef CONFIG_CPU_V7M
16 #define CPUID_EXT_PFR0  0x40
17 #define CPUID_EXT_PFR1  0x44
18 #define CPUID_EXT_DFR0  0x48
19 #define CPUID_EXT_AFR0  0x4c
20 #define CPUID_EXT_MMFR0 0x50
21 #define CPUID_EXT_MMFR1 0x54
22 #define CPUID_EXT_MMFR2 0x58
23 #define CPUID_EXT_MMFR3 0x5c
24 #define CPUID_EXT_ISAR0 0x60
25 #define CPUID_EXT_ISAR1 0x64
26 #define CPUID_EXT_ISAR2 0x68
27 #define CPUID_EXT_ISAR3 0x6c
28 #define CPUID_EXT_ISAR4 0x70
29 #define CPUID_EXT_ISAR5 0x74
30 #else
31 #define CPUID_EXT_PFR0  "c1, 0"
32 #define CPUID_EXT_PFR1  "c1, 1"
33 #define CPUID_EXT_DFR0  "c1, 2"
34 #define CPUID_EXT_AFR0  "c1, 3"
35 #define CPUID_EXT_MMFR0 "c1, 4"
36 #define CPUID_EXT_MMFR1 "c1, 5"
37 #define CPUID_EXT_MMFR2 "c1, 6"
38 #define CPUID_EXT_MMFR3 "c1, 7"
39 #define CPUID_EXT_ISAR0 "c2, 0"
40 #define CPUID_EXT_ISAR1 "c2, 1"
41 #define CPUID_EXT_ISAR2 "c2, 2"
42 #define CPUID_EXT_ISAR3 "c2, 3"
43 #define CPUID_EXT_ISAR4 "c2, 4"
44 #define CPUID_EXT_ISAR5 "c2, 5"
45 #endif
46
47 #define MPIDR_SMP_BITMASK (0x3 << 30)
48 #define MPIDR_SMP_VALUE (0x2 << 30)
49
50 #define MPIDR_MT_BITMASK (0x1 << 24)
51
52 #define MPIDR_HWID_BITMASK 0xFFFFFF
53
54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
55
56 #define MPIDR_LEVEL_BITS 8
57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
58 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
59
60 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
61         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
62
63 #define ARM_CPU_IMP_ARM                 0x41
64 #define ARM_CPU_IMP_DEC                 0x44
65 #define ARM_CPU_IMP_INTEL               0x69
66
67 /* ARM implemented processors */
68 #define ARM_CPU_PART_ARM1136            0x4100b360
69 #define ARM_CPU_PART_ARM1156            0x4100b560
70 #define ARM_CPU_PART_ARM1176            0x4100b760
71 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
72 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
73 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
74 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
75 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
76 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
77 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
78 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
79 #define ARM_CPU_PART_MASK               0xff00fff0
80
81 /* DEC implemented cores */
82 #define ARM_CPU_PART_SA1100             0x4400a110
83
84 /* Intel implemented cores */
85 #define ARM_CPU_PART_SA1110             0x6900b110
86 #define ARM_CPU_REV_SA1110_A0           0
87 #define ARM_CPU_REV_SA1110_B0           4
88 #define ARM_CPU_REV_SA1110_B1           5
89 #define ARM_CPU_REV_SA1110_B2           6
90 #define ARM_CPU_REV_SA1110_B4           8
91
92 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
93 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
94 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
95 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
96
97 /* Qualcomm implemented cores */
98 #define ARM_CPU_PART_SCORPION           0x510002d0
99
100 extern unsigned int processor_id;
101
102 #ifdef CONFIG_CPU_CP15
103 #define read_cpuid(reg)                                                 \
104         ({                                                              \
105                 unsigned int __val;                                     \
106                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
107                     : "=r" (__val)                                      \
108                     :                                                   \
109                     : "cc");                                            \
110                 __val;                                                  \
111         })
112
113 /*
114  * The memory clobber prevents gcc 4.5 from reordering the mrc before
115  * any is_smp() tests, which can cause undefined instruction aborts on
116  * ARM1136 r0 due to the missing extended CP15 registers.
117  */
118 #define read_cpuid_ext(ext_reg)                                         \
119         ({                                                              \
120                 unsigned int __val;                                     \
121                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
122                     : "=r" (__val)                                      \
123                     :                                                   \
124                     : "memory");                                        \
125                 __val;                                                  \
126         })
127
128 #elif defined(CONFIG_CPU_V7M)
129
130 #include <asm/io.h>
131 #include <asm/v7m.h>
132
133 #define read_cpuid(reg)                                                 \
134         ({                                                              \
135                 WARN_ON_ONCE(1);                                        \
136                 0;                                                      \
137         })
138
139 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
140 {
141         return readl(BASEADDR_V7M_SCB + offset);
142 }
143
144 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
145
146 /*
147  * read_cpuid and read_cpuid_ext should only ever be called on machines that
148  * have cp15 so warn on other usages.
149  */
150 #define read_cpuid(reg)                                                 \
151         ({                                                              \
152                 WARN_ON_ONCE(1);                                        \
153                 0;                                                      \
154         })
155
156 #define read_cpuid_ext(reg) read_cpuid(reg)
157
158 #endif /* ifdef CONFIG_CPU_CP15 / else */
159
160 #ifdef CONFIG_CPU_CP15
161 /*
162  * The CPU ID never changes at run time, so we might as well tell the
163  * compiler that it's constant.  Use this function to read the CPU ID
164  * rather than directly reading processor_id or read_cpuid() directly.
165  */
166 static inline unsigned int __attribute_const__ read_cpuid_id(void)
167 {
168         return read_cpuid(CPUID_ID);
169 }
170
171 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
172 {
173         return read_cpuid(CPUID_CACHETYPE);
174 }
175
176 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
177 {
178         return read_cpuid(CPUID_MPUIR);
179 }
180
181 #elif defined(CONFIG_CPU_V7M)
182
183 static inline unsigned int __attribute_const__ read_cpuid_id(void)
184 {
185         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
186 }
187
188 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
189 {
190         return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
191 }
192
193 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
194 {
195         return readl(BASEADDR_V7M_SCB + MPU_TYPE);
196 }
197
198 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
199
200 static inline unsigned int __attribute_const__ read_cpuid_id(void)
201 {
202         return processor_id;
203 }
204
205 #endif /* ifdef CONFIG_CPU_CP15 / else */
206
207 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
208 {
209         return (read_cpuid_id() & 0xFF000000) >> 24;
210 }
211
212 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
213 {
214         return read_cpuid_id() & 0x0000000f;
215 }
216
217 /*
218  * The CPU part number is meaningless without referring to the CPU
219  * implementer: implementers are free to define their own part numbers
220  * which are permitted to clash with other implementer part numbers.
221  */
222 static inline unsigned int __attribute_const__ read_cpuid_part(void)
223 {
224         return read_cpuid_id() & ARM_CPU_PART_MASK;
225 }
226
227 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
228 {
229         return read_cpuid_id() & 0xFFF0;
230 }
231
232 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
233 {
234         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
235 }
236
237 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
238 {
239         return read_cpuid(CPUID_TCM);
240 }
241
242 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
243 {
244         return read_cpuid(CPUID_MPIDR);
245 }
246
247 /* StrongARM-11x0 CPUs */
248 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
249 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
250
251 /*
252  * Intel's XScale3 core supports some v6 features (supersections, L2)
253  * but advertises itself as v5 as it does not support the v6 ISA.  For
254  * this reason, we need a way to explicitly test for this type of CPU.
255  */
256 #ifndef CONFIG_CPU_XSC3
257 #define cpu_is_xsc3()   0
258 #else
259 static inline int cpu_is_xsc3(void)
260 {
261         unsigned int id;
262         id = read_cpuid_id() & 0xffffe000;
263         /* It covers both Intel ID and Marvell ID */
264         if ((id == 0x69056000) || (id == 0x56056000))
265                 return 1;
266
267         return 0;
268 }
269 #endif
270
271 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
272     !defined(CONFIG_CPU_MOHAWK)
273 #define cpu_is_xscale_family() 0
274 #else
275 static inline int cpu_is_xscale_family(void)
276 {
277         unsigned int id;
278         id = read_cpuid_id() & 0xffffe000;
279
280         switch (id) {
281         case 0x69052000: /* Intel XScale 1 */
282         case 0x69054000: /* Intel XScale 2 */
283         case 0x69056000: /* Intel XScale 3 */
284         case 0x56056000: /* Marvell XScale 3 */
285         case 0x56158000: /* Marvell Mohawk */
286                 return 1;
287         }
288
289         return 0;
290 }
291 #endif
292
293 /*
294  * Marvell's PJ4 and PJ4B cores are based on V7 version,
295  * but require a specical sequence for enabling coprocessors.
296  * For this reason, we need a way to distinguish them.
297  */
298 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
299 static inline int cpu_is_pj4(void)
300 {
301         unsigned int id;
302
303         id = read_cpuid_id();
304         if ((id & 0xff0fff00) == 0x560f5800)
305                 return 1;
306
307         return 0;
308 }
309 #else
310 #define cpu_is_pj4()    0
311 #endif
312
313 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
314                                                                   int field)
315 {
316         int feature = (features >> field) & 15;
317
318         /* feature registers are signed values */
319         if (feature > 7)
320                 feature -= 16;
321
322         return feature;
323 }
324
325 #define cpuid_feature_extract(reg, field) \
326         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
327
328 #endif