arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPUIR     4
  12 #define CPUID_MPIDR     5
  13 #define CPUID_REVIDR    6
  14
  15 #ifdef CONFIG_CPU_V7M
  16 #define CPUID_EXT_PFR0  0x40
  17 #define CPUID_EXT_PFR1  0x44
  18 #define CPUID_EXT_DFR0  0x48
  19 #define CPUID_EXT_AFR0  0x4c
  20 #define CPUID_EXT_MMFR0 0x50
  21 #define CPUID_EXT_MMFR1 0x54
  22 #define CPUID_EXT_MMFR2 0x58
  23 #define CPUID_EXT_MMFR3 0x5c
  24 #define CPUID_EXT_ISAR0 0x60
  25 #define CPUID_EXT_ISAR1 0x64
  26 #define CPUID_EXT_ISAR2 0x68
  27 #define CPUID_EXT_ISAR3 0x6c
  28 #define CPUID_EXT_ISAR4 0x70
  29 #define CPUID_EXT_ISAR5 0x74
  30 #else
  31 #define CPUID_EXT_PFR0  "c1, 0"
  32 #define CPUID_EXT_PFR1  "c1, 1"
  33 #define CPUID_EXT_DFR0  "c1, 2"
  34 #define CPUID_EXT_AFR0  "c1, 3"
  35 #define CPUID_EXT_MMFR0 "c1, 4"
  36 #define CPUID_EXT_MMFR1 "c1, 5"
  37 #define CPUID_EXT_MMFR2 "c1, 6"
  38 #define CPUID_EXT_MMFR3 "c1, 7"
  39 #define CPUID_EXT_ISAR0 "c2, 0"
  40 #define CPUID_EXT_ISAR1 "c2, 1"
  41 #define CPUID_EXT_ISAR2 "c2, 2"
  42 #define CPUID_EXT_ISAR3 "c2, 3"
  43 #define CPUID_EXT_ISAR4 "c2, 4"
  44 #define CPUID_EXT_ISAR5 "c2, 5"
  45 #endif
  46
  47 #define MPIDR_SMP_BITMASK (0x3 << 30)
  48 #define MPIDR_SMP_VALUE (0x2 << 30)
  49
  50 #define MPIDR_MT_BITMASK (0x1 << 24)
  51
  52 #define MPIDR_HWID_BITMASK 0xFFFFFF
  53
  54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  55
  56 #define MPIDR_LEVEL_BITS 8
  57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  58
  59 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  60         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  61
  62 #define ARM_CPU_IMP_ARM                 0x41
  63 #define ARM_CPU_IMP_INTEL               0x69
  64
  65 #define ARM_CPU_PART_ARM1136            0xB360
  66 #define ARM_CPU_PART_ARM1156            0xB560
  67 #define ARM_CPU_PART_ARM1176            0xB760
  68 #define ARM_CPU_PART_ARM11MPCORE        0xB020
  69 #define ARM_CPU_PART_CORTEX_A8          0xC080
  70 #define ARM_CPU_PART_CORTEX_A9          0xC090
  71 #define ARM_CPU_PART_CORTEX_A5          0xC050
  72 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
  73 #define ARM_CPU_PART_CORTEX_A7          0xC070
  74 #define ARM_CPU_PART_CORTEX_A12         0xC0D0
  75
  76 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  77 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  78 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  79 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  80
  81 extern unsigned int processor_id;
  82
  83 #ifdef CONFIG_CPU_CP15
  84 #define read_cpuid(reg)                                                 \
  85         ({                                                              \
  86                 unsigned int __val;                                     \
  87                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  88                     : "=r" (__val)                                      \
  89                     :                                                   \
  90                     : "cc");                                            \
  91                 __val;                                                  \
  92         })
  93
  94 /*
  95  * The memory clobber prevents gcc 4.5 from reordering the mrc before
  96  * any is_smp() tests, which can cause undefined instruction aborts on
  97  * ARM1136 r0 due to the missing extended CP15 registers.
  98  */
  99 #define read_cpuid_ext(ext_reg)                                         \
 100         ({                                                              \
 101                 unsigned int __val;                                     \
 102                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 103                     : "=r" (__val)                                      \
 104                     :                                                   \
 105                     : "memory");                                        \
 106                 __val;                                                  \
 107         })
 108
 109 #elif defined(CONFIG_CPU_V7M)
 110
 111 #include <asm/io.h>
 112 #include <asm/v7m.h>
 113
 114 #define read_cpuid(reg)                                                 \
 115         ({                                                              \
 116                 WARN_ON_ONCE(1);                                        \
 117                 0;                                                      \
 118         })
 119
 120 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 121 {
 122         return readl(BASEADDR_V7M_SCB + offset);
 123 }
 124
 125 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 126
 127 /*
 128  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 129  * have cp15 so warn on other usages.
 130  */
 131 #define read_cpuid(reg)                                                 \
 132         ({                                                              \
 133                 WARN_ON_ONCE(1);                                        \
 134                 0;                                                      \
 135         })
 136
 137 #define read_cpuid_ext(reg) read_cpuid(reg)
 138
 139 #endif /* ifdef CONFIG_CPU_CP15 / else */
 140
 141 #ifdef CONFIG_CPU_CP15
 142 /*
 143  * The CPU ID never changes at run time, so we might as well tell the
 144  * compiler that it's constant.  Use this function to read the CPU ID
 145  * rather than directly reading processor_id or read_cpuid() directly.
 146  */
 147 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 148 {
 149         return read_cpuid(CPUID_ID);
 150 }
 151
 152 #elif defined(CONFIG_CPU_V7M)
 153
 154 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 155 {
 156         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 157 }
 158
 159 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 160
 161 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 162 {
 163         return processor_id;
 164 }
 165
 166 #endif /* ifdef CONFIG_CPU_CP15 / else */
 167
 168 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 169 {
 170         return (read_cpuid_id() & 0xFF000000) >> 24;
 171 }
 172
 173 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 174 {
 175         return read_cpuid_id() & 0xFFF0;
 176 }
 177
 178 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 179 {
 180         return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
 181 }
 182
 183 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 184 {
 185         return read_cpuid(CPUID_CACHETYPE);
 186 }
 187
 188 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 189 {
 190         return read_cpuid(CPUID_TCM);
 191 }
 192
 193 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 194 {
 195         return read_cpuid(CPUID_MPIDR);
 196 }
 197
 198 /*
 199  * Intel's XScale3 core supports some v6 features (supersections, L2)
 200  * but advertises itself as v5 as it does not support the v6 ISA.  For
 201  * this reason, we need a way to explicitly test for this type of CPU.
 202  */
 203 #ifndef CONFIG_CPU_XSC3
 204 #define cpu_is_xsc3()   0
 205 #else
 206 static inline int cpu_is_xsc3(void)
 207 {
 208         unsigned int id;
 209         id = read_cpuid_id() & 0xffffe000;
 210         /* It covers both Intel ID and Marvell ID */
 211         if ((id == 0x69056000) || (id == 0x56056000))
 212                 return 1;
 213
 214         return 0;
 215 }
 216 #endif
 217
 218 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 219 #define cpu_is_xscale() 0
 220 #else
 221 #define cpu_is_xscale() 1
 222 #endif
 223
 224 #endif