2 * arch/arm/include/asm/cacheflush.h
4 * Copyright (C) 1999-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
16 #include <asm/shmparam.h>
17 #include <asm/cachetype.h>
19 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
28 #if defined(CONFIG_CPU_CACHE_V3)
30 # define MULTI_CACHE 1
36 #if defined(CONFIG_CPU_CACHE_V4)
38 # define MULTI_CACHE 1
44 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
45 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
46 # define MULTI_CACHE 1
49 #if defined(CONFIG_CPU_FA526)
51 # define MULTI_CACHE 1
57 #if defined(CONFIG_CPU_ARM926T)
59 # define MULTI_CACHE 1
61 # define _CACHE arm926
65 #if defined(CONFIG_CPU_ARM940T)
67 # define MULTI_CACHE 1
69 # define _CACHE arm940
73 #if defined(CONFIG_CPU_ARM946E)
75 # define MULTI_CACHE 1
77 # define _CACHE arm946
81 #if defined(CONFIG_CPU_CACHE_V4WB)
83 # define MULTI_CACHE 1
89 #if defined(CONFIG_CPU_XSCALE)
91 # define MULTI_CACHE 1
93 # define _CACHE xscale
97 #if defined(CONFIG_CPU_XSC3)
99 # define MULTI_CACHE 1
105 #if defined(CONFIG_CPU_MOHAWK)
107 # define MULTI_CACHE 1
109 # define _CACHE mohawk
113 #if defined(CONFIG_CPU_FEROCEON)
114 # define MULTI_CACHE 1
117 #if defined(CONFIG_CPU_V6)
119 # define MULTI_CACHE 1
125 #if defined(CONFIG_CPU_V7)
127 # define MULTI_CACHE 1
133 #if !defined(_CACHE) && !defined(MULTI_CACHE)
134 #error Unknown cache maintainence model
138 * This flag is used to indicate that the page pointed to by a pte
139 * is dirty and requires cleaning before returning it to the user.
141 #define PG_dcache_dirty PG_arch_1
144 * MM Cache Management
145 * ===================
147 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
148 * implement these methods.
150 * Start addresses are inclusive and end addresses are exclusive;
151 * start addresses should be rounded down, end addresses up.
153 * See Documentation/cachetlb.txt for more information.
154 * Please note that the implementation of these, and the required
155 * effects are cache-type (VIVT/VIPT/PIPT) specific.
159 * Unconditionally clean and invalidate the entire cache.
163 * Clean and invalidate all user space cache entries
164 * before a change of page tables.
166 * flush_user_range(start, end, flags)
168 * Clean and invalidate a range of cache entries in the
169 * specified address space before a change of page tables.
170 * - start - user start address (inclusive, page aligned)
171 * - end - user end address (exclusive, page aligned)
172 * - flags - vma->vm_flags field
174 * coherent_kern_range(start, end)
176 * Ensure coherency between the Icache and the Dcache in the
177 * region described by start, end. If you have non-snooping
178 * Harvard caches, you need to implement this function.
179 * - start - virtual start address
180 * - end - virtual end address
182 * coherent_user_range(start, end)
184 * Ensure coherency between the Icache and the Dcache in the
185 * region described by start, end. If you have non-snooping
186 * Harvard caches, you need to implement this function.
187 * - start - virtual start address
188 * - end - virtual end address
190 * flush_kern_dcache_area(kaddr, size)
192 * Ensure that the data held in page is written back.
193 * - kaddr - page address
194 * - size - region size
196 * DMA Cache Coherency
197 * ===================
199 * dma_inv_range(start, end)
201 * Invalidate (discard) the specified virtual address range.
202 * May not write back any entries. If 'start' or 'end'
203 * are not cache line aligned, those lines must be written
205 * - start - virtual start address
206 * - end - virtual end address
208 * dma_clean_range(start, end)
210 * Clean (write back) the specified virtual address range.
211 * - start - virtual start address
212 * - end - virtual end address
214 * dma_flush_range(start, end)
216 * Clean and invalidate the specified virtual address range.
217 * - start - virtual start address
218 * - end - virtual end address
221 struct cpu_cache_fns {
222 void (*flush_kern_all)(void);
223 void (*flush_user_all)(void);
224 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
226 void (*coherent_kern_range)(unsigned long, unsigned long);
227 void (*coherent_user_range)(unsigned long, unsigned long);
228 void (*flush_kern_dcache_area)(void *, size_t);
230 void (*dma_inv_range)(const void *, const void *);
231 void (*dma_clean_range)(const void *, const void *);
232 void (*dma_flush_range)(const void *, const void *);
235 struct outer_cache_fns {
236 void (*inv_range)(unsigned long, unsigned long);
237 void (*clean_range)(unsigned long, unsigned long);
238 void (*flush_range)(unsigned long, unsigned long);
242 * Select the calling method
246 extern struct cpu_cache_fns cpu_cache;
248 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
249 #define __cpuc_flush_user_all cpu_cache.flush_user_all
250 #define __cpuc_flush_user_range cpu_cache.flush_user_range
251 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
252 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range
253 #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
256 * These are private to the dma-mapping API. Do not use directly.
257 * Their sole purpose is to ensure that data held in the cache
258 * is visible to DMA, or data written by DMA to system memory is
259 * visible to the CPU.
261 #define dmac_inv_range cpu_cache.dma_inv_range
262 #define dmac_clean_range cpu_cache.dma_clean_range
263 #define dmac_flush_range cpu_cache.dma_flush_range
267 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
268 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
269 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
270 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
271 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
272 #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
274 extern void __cpuc_flush_kern_all(void);
275 extern void __cpuc_flush_user_all(void);
276 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
277 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
278 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
279 extern void __cpuc_flush_dcache_area(void *, size_t);
282 * These are private to the dma-mapping API. Do not use directly.
283 * Their sole purpose is to ensure that data held in the cache
284 * is visible to DMA, or data written by DMA to system memory is
285 * visible to the CPU.
287 #define dmac_inv_range __glue(_CACHE,_dma_inv_range)
288 #define dmac_clean_range __glue(_CACHE,_dma_clean_range)
289 #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
291 extern void dmac_inv_range(const void *, const void *);
292 extern void dmac_clean_range(const void *, const void *);
293 extern void dmac_flush_range(const void *, const void *);
297 #ifdef CONFIG_OUTER_CACHE
299 extern struct outer_cache_fns outer_cache;
301 static inline void outer_inv_range(unsigned long start, unsigned long end)
303 if (outer_cache.inv_range)
304 outer_cache.inv_range(start, end);
306 static inline void outer_clean_range(unsigned long start, unsigned long end)
308 if (outer_cache.clean_range)
309 outer_cache.clean_range(start, end);
311 static inline void outer_flush_range(unsigned long start, unsigned long end)
313 if (outer_cache.flush_range)
314 outer_cache.flush_range(start, end);
319 static inline void outer_inv_range(unsigned long start, unsigned long end)
321 static inline void outer_clean_range(unsigned long start, unsigned long end)
323 static inline void outer_flush_range(unsigned long start, unsigned long end)
329 * Copy user data from/to a page which is mapped into a different
330 * processes address space. Really, we want to allow our "user
331 * space" model to handle this.
333 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
335 memcpy(dst, src, len); \
336 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
339 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
341 memcpy(dst, src, len); \
345 * Convert calls to our calling convention.
347 #define flush_cache_all() __cpuc_flush_kern_all()
349 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
351 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
352 __cpuc_flush_user_all();
356 vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
358 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
359 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
364 vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
366 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
367 unsigned long addr = user_addr & PAGE_MASK;
368 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
373 vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
374 unsigned long uaddr, void *kaddr,
375 unsigned long len, int write)
377 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
378 unsigned long addr = (unsigned long)kaddr;
379 __cpuc_coherent_kern_range(addr, addr + len);
383 #ifndef CONFIG_CPU_CACHE_VIPT
384 #define flush_cache_mm(mm) \
385 vivt_flush_cache_mm(mm)
386 #define flush_cache_range(vma,start,end) \
387 vivt_flush_cache_range(vma,start,end)
388 #define flush_cache_page(vma,addr,pfn) \
389 vivt_flush_cache_page(vma,addr,pfn)
390 #define flush_ptrace_access(vma,page,ua,ka,len,write) \
391 vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
393 extern void flush_cache_mm(struct mm_struct *mm);
394 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
395 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
396 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
397 unsigned long uaddr, void *kaddr,
398 unsigned long len, int write);
401 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
404 * flush_cache_user_range is used when we want to ensure that the
405 * Harvard caches are synchronised for the user space address range.
406 * This is used for the ARM private sys_cacheflush system call.
408 #define flush_cache_user_range(vma,start,end) \
409 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
412 * Perform necessary cache operations to ensure that data previously
413 * stored within this range of addresses can be executed by the CPU.
415 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
418 * Perform necessary cache operations to ensure that the TLB will
419 * see data written in the specified area.
421 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
424 * flush_dcache_page is used when the kernel has written to the page
425 * cache page at virtual address page->virtual.
427 * If this page isn't mapped (ie, page_mapping == NULL), or it might
428 * have userspace mappings, then we _must_ always clean + invalidate
429 * the dcache entries associated with the kernel mapping.
431 * Otherwise we can defer the operation, and clean the cache when we are
432 * about to change to user space. This is the same method as used on SPARC64.
433 * See update_mmu_cache for the user space part.
435 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
436 extern void flush_dcache_page(struct page *);
438 static inline void __flush_icache_all(void)
440 #ifdef CONFIG_ARM_ERRATA_411920
441 extern void v6_icache_inval_all(void);
442 v6_icache_inval_all();
444 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
450 #define ARCH_HAS_FLUSH_ANON_PAGE
451 static inline void flush_anon_page(struct vm_area_struct *vma,
452 struct page *page, unsigned long vmaddr)
454 extern void __flush_anon_page(struct vm_area_struct *vma,
455 struct page *, unsigned long);
457 __flush_anon_page(vma, page, vmaddr);
460 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
461 static inline void flush_kernel_dcache_page(struct page *page)
463 /* highmem pages are always flushed upon kunmap already */
464 if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
465 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
468 #define flush_dcache_mmap_lock(mapping) \
469 spin_lock_irq(&(mapping)->tree_lock)
470 #define flush_dcache_mmap_unlock(mapping) \
471 spin_unlock_irq(&(mapping)->tree_lock)
473 #define flush_icache_user_range(vma,page,addr,len) \
474 flush_dcache_page(page)
477 * We don't appear to need to do anything here. In fact, if we did, we'd
478 * duplicate cache flushing elsewhere performed by flush_dcache_page().
480 #define flush_icache_page(vma,page) do { } while (0)
483 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
484 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
485 * caches, since the direct-mappings of these pages may contain cached
486 * data, we need to do a full cache flush to ensure that writebacks
487 * don't corrupt data placed into these pages via the new mappings.
489 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
491 if (!cache_is_vipt_nonaliasing())
495 * set_pte_at() called from vmap_pte_range() does not
496 * have a DSB after cleaning the cache line.
501 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
503 if (!cache_is_vipt_nonaliasing())