2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
31 * Endian independent macros for shifting bytes within registers.
36 #define get_byte_0 lsl #0
37 #define get_byte_1 lsr #8
38 #define get_byte_2 lsr #16
39 #define get_byte_3 lsr #24
40 #define put_byte_0 lsl #0
41 #define put_byte_1 lsl #8
42 #define put_byte_2 lsl #16
43 #define put_byte_3 lsl #24
47 #define get_byte_0 lsr #24
48 #define get_byte_1 lsr #16
49 #define get_byte_2 lsr #8
50 #define get_byte_3 lsl #0
51 #define put_byte_0 lsl #24
52 #define put_byte_1 lsl #16
53 #define put_byte_2 lsl #8
54 #define put_byte_3 lsl #0
57 /* Select code for any configuration running in BE8 mode */
58 #ifdef CONFIG_CPU_ENDIAN_BE8
59 #define ARM_BE8(code...) code
61 #define ARM_BE8(code...)
65 * Data preload for architectures that support it
67 #if __LINUX_ARM_ARCH__ >= 5
68 #define PLD(code...) code
74 * This can be used to enable code to cacheline align the destination
75 * pointer when bulk writing to memory. Experiments on StrongARM and
76 * XScale didn't show this a worthwhile thing to do when the cache is not
77 * set to write-allocate (this would need further testing on XScale when WA
80 * On Feroceon there is much to gain however, regardless of cache mode.
82 #ifdef CONFIG_CPU_FEROCEON
83 #define CALGN(code...) code
85 #define CALGN(code...)
89 * Enable and disable interrupts
91 #if __LINUX_ARM_ARCH__ >= 6
92 .macro disable_irq_notrace
96 .macro enable_irq_notrace
100 .macro disable_irq_notrace
101 msr cpsr_c, #PSR_I_BIT | SVC_MODE
104 .macro enable_irq_notrace
105 msr cpsr_c, #SVC_MODE
109 .macro asm_trace_hardirqs_off
110 #if defined(CONFIG_TRACE_IRQFLAGS)
111 stmdb sp!, {r0-r3, ip, lr}
112 bl trace_hardirqs_off
113 ldmia sp!, {r0-r3, ip, lr}
117 .macro asm_trace_hardirqs_on_cond, cond
118 #if defined(CONFIG_TRACE_IRQFLAGS)
120 * actually the registers should be pushed and pop'd conditionally, but
121 * after bl the flags are certainly clobbered
123 stmdb sp!, {r0-r3, ip, lr}
124 bl\cond trace_hardirqs_on
125 ldmia sp!, {r0-r3, ip, lr}
129 .macro asm_trace_hardirqs_on
130 asm_trace_hardirqs_on_cond al
135 asm_trace_hardirqs_off
139 asm_trace_hardirqs_on
143 * Save the current IRQ state and disable IRQs. Note that this macro
144 * assumes FIQs are enabled, and that the processor is in SVC mode.
146 .macro save_and_disable_irqs, oldcpsr
147 #ifdef CONFIG_CPU_V7M
148 mrs \oldcpsr, primask
155 .macro save_and_disable_irqs_notrace, oldcpsr
161 * Restore interrupt state previously stored in a register. We don't
162 * guarantee that this will preserve the flags.
164 .macro restore_irqs_notrace, oldcpsr
165 #ifdef CONFIG_CPU_V7M
166 msr primask, \oldcpsr
172 .macro restore_irqs, oldcpsr
173 tst \oldcpsr, #PSR_I_BIT
174 asm_trace_hardirqs_on_cond eq
175 restore_irqs_notrace \oldcpsr
179 * Get current thread_info.
181 .macro get_thread_info, rd
182 ARM( mov \rd, sp, lsr #13 )
184 THUMB( lsr \rd, \rd, #13 )
185 mov \rd, \rd, lsl #13
189 * Increment/decrement the preempt count.
191 #ifdef CONFIG_PREEMPT_COUNT
192 .macro inc_preempt_count, ti, tmp
193 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
194 add \tmp, \tmp, #1 @ increment it
195 str \tmp, [\ti, #TI_PREEMPT]
198 .macro dec_preempt_count, ti, tmp
199 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
200 sub \tmp, \tmp, #1 @ decrement it
201 str \tmp, [\ti, #TI_PREEMPT]
204 .macro dec_preempt_count_ti, ti, tmp
206 dec_preempt_count \ti, \tmp
209 .macro inc_preempt_count, ti, tmp
212 .macro dec_preempt_count, ti, tmp
215 .macro dec_preempt_count_ti, ti, tmp
221 .pushsection __ex_table,"a"; \
227 #define ALT_SMP(instr...) \
230 * Note: if you get assembler errors from ALT_UP() when building with
231 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
232 * ALT_SMP( W(instr) ... )
234 #define ALT_UP(instr...) \
235 .pushsection ".alt.smp.init", "a" ;\
238 .if . - 9997b != 4 ;\
239 .error "ALT_UP() content must assemble to exactly 4 bytes";\
242 #define ALT_UP_B(label) \
243 .equ up_b_offset, label - 9998b ;\
244 .pushsection ".alt.smp.init", "a" ;\
246 W(b) . + up_b_offset ;\
249 #define ALT_SMP(instr...)
250 #define ALT_UP(instr...) instr
251 #define ALT_UP_B(label) b label
255 * Instruction barrier
258 #if __LINUX_ARM_ARCH__ >= 7
260 #elif __LINUX_ARM_ARCH__ == 6
261 mcr p15, 0, r0, c7, c5, 4
266 * SMP data memory barrier
270 #if __LINUX_ARM_ARCH__ >= 7
276 #elif __LINUX_ARM_ARCH__ == 6
277 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
279 #error Incompatible SMP platform
289 #if defined(CONFIG_CPU_V7M)
291 * setmode is used to assert to be in svc mode during boot. For v7-M
292 * this is done in __v7m_setup, so setmode can be empty here.
294 .macro setmode, mode, reg
296 #elif defined(CONFIG_THUMB2_KERNEL)
297 .macro setmode, mode, reg
302 .macro setmode, mode, reg
308 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
309 * a scratch register for the macro to overwrite.
311 * This macro is intended for forcing the CPU into SVC mode at boot time.
312 * you cannot return to the original mode.
314 .macro safe_svcmode_maskall reg:req
315 #if __LINUX_ARM_ARCH__ >= 6
317 eor \reg, \reg, #HYP_MODE
319 bic \reg , \reg , #MODE_MASK
320 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
321 THUMB( orr \reg , \reg , #PSR_T_BIT )
323 orr \reg, \reg, #PSR_A_BIT
332 * workaround for possibly broken pre-v6 hardware
333 * (akita, Sharp Zaurus C-1000, PXA270-based)
335 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
340 * STRT/LDRT access macros with ARM and Thumb-2 variants
342 #ifdef CONFIG_THUMB2_KERNEL
344 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
347 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
349 \instr\cond\()\t\().w \reg, [\ptr, #\off]
351 .error "Unsupported inc macro argument"
354 .pushsection __ex_table,"a"
360 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
361 @ explicit IT instruction needed because of the label
362 @ introduced by the USER macro
369 .error "Unsupported rept macro argument"
373 @ Slightly optimised to avoid incrementing the pointer twice
374 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
376 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
379 add\cond \ptr, #\rept * \inc
382 #else /* !CONFIG_THUMB2_KERNEL */
384 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
388 \instr\cond\()b\()\t \reg, [\ptr], #\inc
390 \instr\cond\()\t \reg, [\ptr], #\inc
392 .error "Unsupported inc macro argument"
395 .pushsection __ex_table,"a"
402 #endif /* CONFIG_THUMB2_KERNEL */
404 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
405 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
408 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
409 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
412 /* Utility macro for declaring string literals */
413 .macro string name:req, string
414 .type \name , #object
417 .size \name , . - \name
420 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
421 #ifndef CONFIG_CPU_USE_DOMAINS
422 adds \tmp, \addr, #\size - 1
423 sbcccs \tmp, \tmp, \limit
428 #endif /* __ASM_ASSEMBLER_H__ */