arch/arm/boot/dts/zynq-zc702.dts

   1 /*
   2  *  Copyright (C) 2011 Xilinx
   3  *  Copyright (C) 2012 National Instruments Corp.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 /dts-v1/;
  15 /include/ "zynq-7000.dtsi"
  16
  17 / {
  18         model = "Zynq ZC702 Development Board";
  19         compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  20
  21         memory {
  22                 device_type = "memory";
  23                 reg = <0x0 0x40000000>;
  24         };
  25
  26         chosen {
  27                 bootargs = "console=ttyPS0,115200 earlyprintk";
  28         };
  29
  30 };
  31
  32 &can0 {
  33         status = "okay";
  34 };
  35
  36 &gem0 {
  37         status = "okay";
  38         phy-mode = "rgmii";
  39 };
  40
  41 &i2c0 {
  42         status = "okay";
  43         clock-frequency = <400000>;
  44
  45         i2cswitch@74 {
  46                 compatible = "nxp,pca9548";
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 reg = <0x74>;
  50
  51                 i2c@0 {
  52                         #address-cells = <1>;
  53                         #size-cells = <0>;
  54                         reg = <0>;
  55                         si570: clock-generator@5d {
  56                                 #clock-cells = <0>;
  57                                 compatible = "silabs,si570";
  58                                 temperature-stability = <50>;
  59                                 reg = <0x5d>;
  60                                 factory-fout = <156250000>;
  61                                 clock-frequency = <148500000>;
  62                         };
  63                 };
  64
  65                 i2c@2 {
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                         reg = <2>;
  69                         eeprom@54 {
  70                                 compatible = "at,24c08";
  71                                 reg = <0x54>;
  72                         };
  73                 };
  74
  75                 i2c@3 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         reg = <3>;
  79                         gpio@21 {
  80                                 compatible = "ti,tca6416";
  81                                 reg = <0x21>;
  82                                 gpio-controller;
  83                                 #gpio-cells = <2>;
  84                         };
  85                 };
  86
  87                 i2c@4 {
  88                         #address-cells = <1>;
  89                         #size-cells = <0>;
  90                         reg = <4>;
  91                         rtc@51 {
  92                                 compatible = "nxp,pcf8563";
  93                                 reg = <0x51>;
  94                         };
  95                 };
  96
  97                 i2c@7 {
  98                         #address-cells = <1>;
  99                         #size-cells = <0>;
 100                         reg = <7>;
 101                         hwmon@52 {
 102                                 compatible = "ti,ucd9248";
 103                                 reg = <52>;
 104                         };
 105                         hwmon@53 {
 106                                 compatible = "ti,ucd9248";
 107                                 reg = <53>;
 108                         };
 109                         hwmon@54 {
 110                                 compatible = "ti,ucd9248";
 111                                 reg = <54>;
 112                         };
 113                 };
 114         };
 115 };
 116
 117 &sdhci0 {
 118         status = "okay";
 119 };
 120
 121 &uart1 {
 122         status = "okay";
 123 };