arch/arm/boot/dts/zx296702.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/zx296702-clock.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 / {
   8         cpus {
   9                 #address-cells = <1>;
  10                 #size-cells = <0>;
  11                 enable-method = "zte,zx296702-smp";
  12
  13                 cpu@0 {
  14                         compatible = "arm,cortex-a9";
  15                         device_type = "cpu";
  16                         next-level-cache = <&l2cc>;
  17                         reg = <0>;
  18                 };
  19
  20                 cpu@1 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         next-level-cache = <&l2cc>;
  24                         reg = <1>;
  25                 };
  26         };
  27
  28
  29         soc {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 compatible = "simple-bus";
  33                 interrupt-parent = <&intc>;
  34                 ranges;
  35
  36                 matrix: bus-matrix@400000 {
  37                         compatible = "zte,zx-bus-matrix";
  38                         reg = <0x00400000 0x1000>;
  39                 };
  40
  41                 intc: interrupt-controller@801000 {
  42                         compatible = "arm,cortex-a9-gic";
  43                         #interrupt-cells = <3>;
  44                         #address-cells = <1>;
  45                         #size-cells = <1>;
  46                         interrupt-controller;
  47                         reg = <0x00801000 0x1000>,
  48                               <0x00800100 0x100>;
  49                 };
  50
  51                 global_timer: timer@8000200 {
  52                         compatible = "arm,cortex-a9-global-timer";
  53                         reg = <0x00800200 0x20>;
  54                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  55                         interrupt-parent = <&intc>;
  56                         clocks = <&topclk ZX296702_A9_PERIPHCLK>;
  57                 };
  58
  59                 l2cc: l2-cache-controller@0x00c00000 {
  60                         compatible = "arm,pl310-cache";
  61                         reg = <0x00c00000 0x1000>;
  62                         cache-unified;
  63                         cache-level = <2>;
  64                         arm,data-latency = <1 1 1>;
  65                         arm,tag-latency = <1 1 1>;
  66                         arm,double-linefill = <1>;
  67                         arm,double-linefill-incr = <0>;
  68                 };
  69
  70                 pcu: pcu@0xa0008000 {
  71                         compatible = "zte,zx296702-pcu";
  72                         reg = <0xa0008000 0x1000>;
  73                 };
  74
  75                 topclk: topclk@0x09800000 {
  76                         compatible = "zte,zx296702-topcrm-clk";
  77                         reg = <0x09800000 0x1000>;
  78                         #clock-cells = <1>;
  79                 };
  80
  81                 lsp1clk: lsp1clk@0x09400000 {
  82                         compatible = "zte,zx296702-lsp1crpm-clk";
  83                         reg = <0x09400000 0x1000>;
  84                         #clock-cells = <1>;
  85                 };
  86
  87                 lsp0clk: lsp0clk@0x0b000000 {
  88                         compatible = "zte,zx296702-lsp0crpm-clk";
  89                         reg = <0x0b000000 0x1000>;
  90                         #clock-cells = <1>;
  91                 };
  92
  93                 uart0: serial@0x09405000 {
  94                         compatible = "zte,zx296702-uart";
  95                         reg = <0x09405000 0x1000>;
  96                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  97                         clocks = <&lsp1clk ZX296702_UART0_WCLK>;
  98                         status = "disabled";
  99                 };
 100
 101                 uart1: serial@0x09406000 {
 102                         compatible = "zte,zx296702-uart";
 103                         reg = <0x09406000 0x1000>;
 104                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&lsp1clk ZX296702_UART1_WCLK>;
 106                         status = "disabled";
 107                 };
 108
 109                 mmc0: mmc@0x09408000 {
 110                         compatible = "snps,dw-mshc";
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         reg = <0x09408000 0x1000>;
 114                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 115                         fifo-depth = <32>;
 116                         clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
 117                                  <&lsp1clk ZX296702_SDMMC0_WCLK>;
 118                         clock-names = "biu", "ciu";
 119                         status = "disabled";
 120                 };
 121
 122                 mmc1: mmc@0x0b003000 {
 123                         compatible = "snps,dw-mshc";
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         reg = <0x0b003000 0x1000>;
 127                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 128                         fifo-depth = <32>;
 129                         clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
 130                                  <&lsp0clk ZX296702_SDMMC1_WCLK>;
 131                         clock-names = "biu", "ciu";
 132                         status = "disabled";
 133                 };
 134
 135                 sysctrl: sysctrl@0xa0007000 {
 136                         compatible = "zte,sysctrl", "syscon";
 137                         reg = <0xa0007000 0x1000>;
 138                 };
 139         };
 140 };