arch/arm/boot/dts/wm8505.dtsi

   1 /*
   2  * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
   3  *
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         compatible = "wm,wm8505";
  13
  14         cpus {
  15                 #address-cells = <0>;
  16                 #size-cells = <0>;
  17
  18                 cpu {
  19                         device_type = "cpu";
  20                         compatible = "arm,arm926ej-s";
  21                 };
  22         };
  23
  24         memory {
  25                 device_type = "memory";
  26                 reg = <0x0 0x0>;
  27         };
  28
  29         aliases {
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &uart2;
  33                 serial3 = &uart3;
  34                 serial4 = &uart4;
  35                 serial5 = &uart5;
  36         };
  37
  38         soc {
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 compatible = "simple-bus";
  42                 ranges;
  43                 interrupt-parent = <&intc0>;
  44
  45                 intc0: interrupt-controller@d8140000 {
  46                         compatible = "via,vt8500-intc";
  47                         interrupt-controller;
  48                         reg = <0xd8140000 0x10000>;
  49                         #interrupt-cells = <1>;
  50                 };
  51
  52                 /* Secondary IC cascaded to intc0 */
  53                 intc1: interrupt-controller@d8150000 {
  54                         compatible = "via,vt8500-intc";
  55                         interrupt-controller;
  56                         #interrupt-cells = <1>;
  57                         reg = <0xD8150000 0x10000>;
  58                         interrupts = <56 57 58 59 60 61 62 63>;
  59                 };
  60
  61                 pinctrl: pinctrl@d8110000 {
  62                         compatible = "wm,wm8505-pinctrl";
  63                         reg = <0xd8110000 0x10000>;
  64                         interrupt-controller;
  65                         #interrupt-cells = <2>;
  66                         gpio-controller;
  67                         #gpio-cells = <2>;
  68                 };
  69
  70                 pmc@d8130000 {
  71                         compatible = "via,vt8500-pmc";
  72                         reg = <0xd8130000 0x1000>;
  73                         clocks {
  74                                 #address-cells = <1>;
  75                                 #size-cells = <0>;
  76
  77                                 ref24: ref24M {
  78                                         #clock-cells = <0>;
  79                                         compatible = "fixed-clock";
  80                                         clock-frequency = <24000000>;
  81                                 };
  82
  83                                 ref25: ref25M {
  84                                         #clock-cells = <0>;
  85                                         compatible = "fixed-clock";
  86                                         clock-frequency = <25000000>;
  87                                 };
  88
  89                                 plla: plla {
  90                                         #clock-cells = <0>;
  91                                         compatible = "via,vt8500-pll-clock";
  92                                         clocks = <&ref25>;
  93                                         reg = <0x200>;
  94                                 };
  95
  96                                 pllb: pllb {
  97                                         #clock-cells = <0>;
  98                                         compatible = "via,vt8500-pll-clock";
  99                                         clocks = <&ref25>;
 100                                         reg = <0x204>;
 101                                 };
 102
 103                                 pllc: pllc {
 104                                         #clock-cells = <0>;
 105                                         compatible = "via,vt8500-pll-clock";
 106                                         clocks = <&ref25>;
 107                                         reg = <0x208>;
 108                                 };
 109
 110                                 plld: plld {
 111                                         #clock-cells = <0>;
 112                                         compatible = "via,vt8500-pll-clock";
 113                                         clocks = <&ref25>;
 114                                         reg = <0x20c>;
 115                                 };
 116
 117                                 clkarm: arm {
 118                                         #clock-cells = <0>;
 119                                         compatible = "via,vt8500-device-clock";
 120                                         clocks = <&plla>;
 121                                         divisor-reg = <0x300>;
 122                                 };
 123
 124                                 clkahb: ahb {
 125                                         #clock-cells = <0>;
 126                                         compatible = "via,vt8500-device-clock";
 127                                         clocks = <&pllb>;
 128                                         divisor-reg = <0x304>;
 129                                 };
 130
 131                                 clkapb: apb {
 132                                         #clock-cells = <0>;
 133                                         compatible = "via,vt8500-device-clock";
 134                                         clocks = <&pllb>;
 135                                         divisor-reg = <0x350>;
 136                                 };
 137
 138                                 clkddr: ddr {
 139                                         #clock-cells = <0>;
 140                                         compatible = "via,vt8500-device-clock";
 141                                         clocks = <&plld>;
 142                                         divisor-reg = <0x310>;
 143                                 };
 144
 145                                 clkuart0: uart0 {
 146                                         #clock-cells = <0>;
 147                                         compatible = "via,vt8500-device-clock";
 148                                         clocks = <&ref24>;
 149                                         enable-reg = <0x250>;
 150                                         enable-bit = <1>;
 151                                 };
 152
 153                                 clkuart1: uart1 {
 154                                         #clock-cells = <0>;
 155                                         compatible = "via,vt8500-device-clock";
 156                                         clocks = <&ref24>;
 157                                         enable-reg = <0x250>;
 158                                         enable-bit = <2>;
 159                                 };
 160
 161                                 clkuart2: uart2 {
 162                                         #clock-cells = <0>;
 163                                         compatible = "via,vt8500-device-clock";
 164                                         clocks = <&ref24>;
 165                                         enable-reg = <0x250>;
 166                                         enable-bit = <3>;
 167                                 };
 168
 169                                 clkuart3: uart3 {
 170                                         #clock-cells = <0>;
 171                                         compatible = "via,vt8500-device-clock";
 172                                         clocks = <&ref24>;
 173                                         enable-reg = <0x250>;
 174                                         enable-bit = <4>;
 175                                 };
 176
 177                                 clkuart4: uart4 {
 178                                         #clock-cells = <0>;
 179                                         compatible = "via,vt8500-device-clock";
 180                                         clocks = <&ref24>;
 181                                         enable-reg = <0x250>;
 182                                         enable-bit = <22>;
 183                                 };
 184
 185                                 clkuart5: uart5 {
 186                                         #clock-cells = <0>;
 187                                         compatible = "via,vt8500-device-clock";
 188                                         clocks = <&ref24>;
 189                                         enable-reg = <0x250>;
 190                                         enable-bit = <23>;
 191                                 };
 192
 193                                 clksdhc: sdhc {
 194                                         #clock-cells = <0>;
 195                                         compatible = "via,vt8500-device-clock";
 196                                         clocks = <&pllb>;
 197                                         divisor-reg = <0x328>;
 198                                         divisor-mask = <0x3f>;
 199                                         enable-reg = <0x254>;
 200                                         enable-bit = <18>;
 201                                 };
 202                         };
 203                 };
 204
 205                 timer@d8130100 {
 206                         compatible = "via,vt8500-timer";
 207                         reg = <0xd8130100 0x28>;
 208                         interrupts = <36>;
 209                 };
 210
 211                 ehci@d8007100 {
 212                         compatible = "via,vt8500-ehci";
 213                         reg = <0xd8007100 0x200>;
 214                         interrupts = <1>;
 215                 };
 216
 217                 uhci@d8007300 {
 218                         compatible = "platform-uhci";
 219                         reg = <0xd8007300 0x200>;
 220                         interrupts = <0>;
 221                 };
 222
 223                 fb: fb@d8050800 {
 224                         compatible = "wm,wm8505-fb";
 225                         reg = <0xd8050800 0x200>;
 226                 };
 227
 228                 ge_rops@d8050400 {
 229                         compatible = "wm,prizm-ge-rops";
 230                         reg = <0xd8050400 0x100>;
 231                 };
 232
 233                 uart0: serial@d8200000 {
 234                         compatible = "via,vt8500-uart";
 235                         reg = <0xd8200000 0x1040>;
 236                         interrupts = <32>;
 237                         clocks = <&clkuart0>;
 238                         status = "disabled";
 239                 };
 240
 241                 uart1: serial@d82b0000 {
 242                         compatible = "via,vt8500-uart";
 243                         reg = <0xd82b0000 0x1040>;
 244                         interrupts = <33>;
 245                         clocks = <&clkuart1>;
 246                         status = "disabled";
 247                 };
 248
 249                 uart2: serial@d8210000 {
 250                         compatible = "via,vt8500-uart";
 251                         reg = <0xd8210000 0x1040>;
 252                         interrupts = <47>;
 253                         clocks = <&clkuart2>;
 254                         status = "disabled";
 255                 };
 256
 257                 uart3: serial@d82c0000 {
 258                         compatible = "via,vt8500-uart";
 259                         reg = <0xd82c0000 0x1040>;
 260                         interrupts = <50>;
 261                         clocks = <&clkuart3>;
 262                         status = "disabled";
 263                 };
 264
 265                 uart4: serial@d8370000 {
 266                         compatible = "via,vt8500-uart";
 267                         reg = <0xd8370000 0x1040>;
 268                         interrupts = <31>;
 269                         clocks = <&clkuart4>;
 270                         status = "disabled";
 271                 };
 272
 273                 uart5: serial@d8380000 {
 274                         compatible = "via,vt8500-uart";
 275                         reg = <0xd8380000 0x1040>;
 276                         interrupts = <30>;
 277                         clocks = <&clkuart5>;
 278                         status = "disabled";
 279                 };
 280
 281                 rtc@d8100000 {
 282                         compatible = "via,vt8500-rtc";
 283                         reg = <0xd8100000 0x10000>;
 284                         interrupts = <48>;
 285                 };
 286
 287                 sdhc@d800a000 {
 288                         compatible = "wm,wm8505-sdhc";
 289                         reg = <0xd800a000 0x400>;
 290                         interrupts = <20>, <21>;
 291                         clocks = <&clksdhc>;
 292                         bus-width = <4>;
 293                 };
 294         };
 295 };