arch/arm/boot/dts/vf610-zii-spb4.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SPB4 board
   5  *
   6  * SPB - Seat Power Box
   7  *
   8  * Copyright (C) 2019 Zodiac Inflight Innovations
   9  */
  10
  11 /dts-v1/;
  12 #include "vf610.dtsi"
  13
  14 / {
  15         model = "ZII VF610 SPB4 Board";
  16         compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
  17
  18         chosen {
  19                 stdout-path = &uart0;
  20         };
  21
  22         memory@80000000 {
  23                 device_type = "memory";
  24                 reg = <0x80000000 0x20000000>;
  25         };
  26
  27         gpio-leds {
  28                 compatible = "gpio-leds";
  29                 pinctrl-0 = <&pinctrl_leds_debug>;
  30                 pinctrl-names = "default";
  31
  32                 led-debug {
  33                         label = "zii:green:debug1";
  34                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  35                         linux,default-trigger = "heartbeat";
  36                 };
  37         };
  38
  39         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "vcc_3v3_mcu";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44         };
  45 };
  46
  47 &adc0 {
  48         vref-supply = <&reg_vcc_3v3_mcu>;
  49         status = "okay";
  50 };
  51
  52 &adc1 {
  53         vref-supply = <&reg_vcc_3v3_mcu>;
  54         status = "okay";
  55 };
  56
  57 &dspi1 {
  58         bus-num = <1>;
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_dspi1>;
  61         status = "okay";
  62
  63         flash@0 {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 compatible = "m25p128", "jedec,spi-nor";
  67                 reg = <0>;
  68                 spi-max-frequency = <50000000>;
  69         };
  70 };
  71
  72 &edma0 {
  73         status = "okay";
  74 };
  75
  76 &edma1 {
  77         status = "okay";
  78 };
  79
  80 &esdhc0 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_esdhc0>;
  83         bus-width = <8>;
  84         non-removable;
  85         no-1-8-v;
  86         keep-power-in-suspend;
  87         no-sdio;
  88         no-sd;
  89         status = "okay";
  90 };
  91
  92 &esdhc1 {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&pinctrl_esdhc1>;
  95         bus-width = <4>;
  96         no-sdio;
  97         status = "okay";
  98 };
  99
 100 &fec1 {
 101         phy-mode = "rmii";
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_fec1>;
 104         status = "okay";
 105
 106         fixed-link {
 107                 speed = <100>;
 108                 full-duplex;
 109         };
 110
 111         mdio1: mdio {
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 status = "okay";
 115
 116                 switch0: switch0@0 {
 117                         compatible = "marvell,mv88e6190";
 118                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 119                         pinctrl-names = "default";
 120                         reg = <0>;
 121                         eeprom-length = <65536>;
 122                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 123                         interrupt-parent = <&gpio3>;
 124                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 125                         interrupt-controller;
 126                         #interrupt-cells = <2>;
 127
 128                         ports {
 129                                 #address-cells = <1>;
 130                                 #size-cells = <0>;
 131
 132                                 port@0 {
 133                                         reg = <0>;
 134                                         label = "cpu";
 135                                         ethernet = <&fec1>;
 136
 137                                         fixed-link {
 138                                                 speed = <100>;
 139                                                 full-duplex;
 140                                         };
 141                                 };
 142
 143                                 port@1 {
 144                                         reg = <1>;
 145                                         label = "eth_cu_1000_1";
 146                                 };
 147
 148                                 port@2 {
 149                                         reg = <2>;
 150                                         label = "eth_cu_1000_2";
 151                                 };
 152
 153                                 port@3 {
 154                                         reg = <3>;
 155                                         label = "eth_cu_1000_3";
 156                                 };
 157
 158                                 port@4 {
 159                                         reg = <4>;
 160                                         label = "eth_cu_1000_4";
 161                                 };
 162
 163                                 port@5 {
 164                                         reg = <5>;
 165                                         label = "eth_cu_1000_5";
 166                                 };
 167
 168                                 port@6 {
 169                                         reg = <6>;
 170                                         label = "eth_cu_1000_6";
 171                                 };
 172                         };
 173                 };
 174         };
 175 };
 176
 177 &i2c0 {
 178         clock-frequency = <100000>;
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_i2c0>;
 181         status = "okay";
 182
 183         io-expander@22 {
 184                 compatible = "nxp,pca9554";
 185                 reg = <0x22>;
 186                 gpio-controller;
 187                 #gpio-cells = <2>;
 188         };
 189
 190         eeprom@50 {
 191                 compatible = "atmel,24c04";
 192                 reg = <0x50>;
 193                 label = "nameplate";
 194         };
 195
 196         eeprom@52 {
 197                 compatible = "atmel,24c04";
 198                 reg = <0x52>;
 199         };
 200 };
 201
 202 &snvsrtc {
 203         status = "disabled";
 204 };
 205
 206 &uart0 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_uart0>;
 209         status = "okay";
 210 };
 211
 212 &uart1 {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_uart1>;
 215         status = "okay";
 216 };
 217
 218 &uart2 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_uart2>;
 221         status = "okay";
 222
 223         rave-sp {
 224                 compatible = "zii,rave-sp-rdu2";
 225                 current-speed = <1000000>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228
 229                 watchdog {
 230                         compatible = "zii,rave-sp-watchdog";
 231                 };
 232
 233                 eeprom@a3 {
 234                         compatible = "zii,rave-sp-eeprom";
 235                         reg = <0xa3 0x4000>;
 236                         #address-cells = <1>;
 237                         #size-cells = <1>;
 238                         zii,eeprom-name = "main-eeprom";
 239                 };
 240         };
 241 };
 242
 243 &uart3 {
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_uart3>;
 246         status = "okay";
 247 };
 248
 249 &wdoga5 {
 250        status = "disabled";
 251 };
 252
 253 &iomuxc {
 254         pinctrl_dspi1: dspi1grp {
 255                 fsl,pins = <
 256                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 257                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 258                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 259                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 260                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 261                 >;
 262         };
 263
 264         pinctrl_esdhc0: esdhc0grp {
 265                 fsl,pins = <
 266                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 267                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 268                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 269                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 270                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 271                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 272                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 273                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 274                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 275                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 276                 >;
 277         };
 278
 279         pinctrl_esdhc1: esdhc1grp {
 280                 fsl,pins = <
 281                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 282                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 283                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 284                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 285                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 286                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 287                 >;
 288         };
 289
 290         pinctrl_fec1: fec1grp {
 291                 fsl,pins = <
 292                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 293                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 294                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 295                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 296                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 297                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 298                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 299                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 300                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 301                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 302                 >;
 303         };
 304
 305         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 306                 fsl,pins = <
 307                         VF610_PAD_PTE2__GPIO_107                0x31c2
 308                         VF610_PAD_PTB28__GPIO_98                0x219d
 309                 >;
 310         };
 311
 312         pinctrl_i2c0: i2c0grp {
 313                 fsl,pins = <
 314                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 315                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 316                 >;
 317         };
 318
 319         pinctrl_leds_debug: pinctrl-leds-debug {
 320                 fsl,pins = <
 321                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 322                 >;
 323         };
 324
 325         pinctrl_uart0: uart0grp {
 326                 fsl,pins = <
 327                         VF610_PAD_PTB10__UART0_TX               0x21a2
 328                         VF610_PAD_PTB11__UART0_RX               0x21a1
 329                 >;
 330         };
 331
 332         pinctrl_uart1: uart1grp {
 333                 fsl,pins = <
 334                         VF610_PAD_PTB23__UART1_TX               0x21a2
 335                         VF610_PAD_PTB24__UART1_RX               0x21a1
 336                 >;
 337         };
 338
 339         pinctrl_uart2: uart2grp {
 340                 fsl,pins = <
 341                         VF610_PAD_PTD0__UART2_TX                0x21a2
 342                         VF610_PAD_PTD1__UART2_RX                0x21a1
 343                 >;
 344         };
 345
 346         pinctrl_uart3: uart3grp {
 347                 fsl,pins = <
 348                         VF610_PAD_PTA30__UART3_TX               0x21a2
 349                         VF610_PAD_PTA31__UART3_RX               0x21a1
 350                 >;
 351         };
 352 };