arch/arm/boot/dts/vf610-zii-dev-rev-c.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev C";
  50         compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  59                 mdio-parent-bus = <&mdio1>;
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 mdio_mux_1: mdio@1 {
  64                         reg = <1>;
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67
  68                         switch0: switch@0 {
  69                                 compatible = "marvell,mv88e6190";
  70                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  71                                 pinctrl-names = "default";
  72                                 reg = <0>;
  73                                 dsa,member = <0 0>;
  74                                 eeprom-length = <65536>;
  75                                 interrupt-parent = <&gpio0>;
  76                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  77                                 interrupt-controller;
  78                                 #interrupt-cells = <2>;
  79
  80                                 ports {
  81                                         #address-cells = <1>;
  82                                         #size-cells = <0>;
  83
  84                                         port@0 {
  85                                                 reg = <0>;
  86                                                 label = "cpu";
  87                                                 ethernet = <&fec1>;
  88
  89                                                 fixed-link {
  90                                                         speed = <100>;
  91                                                         full-duplex;
  92                                                 };
  93                                         };
  94
  95                                         port@1 {
  96                                                 reg = <1>;
  97                                                 label = "lan1";
  98                                                 phy-handle = <&switch0phy1>;
  99                                         };
 100
 101                                         port@2 {
 102                                                 reg = <2>;
 103                                                 label = "lan2";
 104                                                 phy-handle = <&switch0phy2>;
 105                                         };
 106
 107                                         port@3 {
 108                                                 reg = <3>;
 109                                                 label = "lan3";
 110                                                 phy-handle = <&switch0phy3>;
 111                                         };
 112
 113                                         port@4 {
 114                                                 reg = <4>;
 115                                                 label = "lan4";
 116                                                 phy-handle = <&switch0phy4>;
 117                                         };
 118
 119                                         switch0port10: port@10 {
 120                                                 reg = <10>;
 121                                                 label = "dsa";
 122                                                 phy-mode = "xaui";
 123                                                 link = <&switch1port10>;
 124                                         };
 125                                 };
 126
 127                                 mdio {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130
 131                                         switch0phy1: switch0phy@1 {
 132                                                 reg = <1>;
 133                                                 interrupt-parent = <&switch0>;
 134                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 135                                         };
 136
 137                                         switch0phy2: switch0phy@2 {
 138                                                 reg = <2>;
 139                                                 interrupt-parent = <&switch0>;
 140                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 141                                         };
 142
 143                                         switch0phy3: switch0phy@3 {
 144                                                 reg = <3>;
 145                                                 interrupt-parent = <&switch0>;
 146                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 147                                         };
 148
 149                                         switch0phy4: switch0phy@4 {
 150                                                 reg = <4>;
 151                                                 interrupt-parent = <&switch0>;
 152                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 153                                         };
 154                                 };
 155                         };
 156                 };
 157
 158                 mdio_mux_2: mdio@2 {
 159                         reg = <2>;
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162
 163                         switch1: switch@0 {
 164                                 compatible = "marvell,mv88e6190";
 165                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 166                                 pinctrl-names = "default";
 167                                 reg = <0>;
 168                                 dsa,member = <0 1>;
 169                                 eeprom-length = <65536>;
 170                                 interrupt-parent = <&gpio0>;
 171                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 172                                 interrupt-controller;
 173                                 #interrupt-cells = <2>;
 174
 175                                 ports {
 176                                         #address-cells = <1>;
 177                                         #size-cells = <0>;
 178
 179                                         port@1 {
 180                                                 reg = <1>;
 181                                                 label = "lan5";
 182                                                 phy-handle = <&switch1phy1>;
 183                                         };
 184
 185                                         port@2 {
 186                                                 reg = <2>;
 187                                                 label = "lan6";
 188                                                 phy-handle = <&switch1phy2>;
 189                                         };
 190
 191                                         port@3 {
 192                                                 reg = <3>;
 193                                                 label = "lan7";
 194                                                 phy-handle = <&switch1phy3>;
 195                                         };
 196
 197                                         port@4 {
 198                                                 reg = <4>;
 199                                                 label = "lan8";
 200                                                 phy-handle = <&switch1phy4>;
 201                                         };
 202
 203                                         port@9 {
 204                                                 reg = <9>;
 205                                                 label = "sff2";
 206                                                 phy-mode = "sgmii";
 207                                                 managed = "in-band-status";
 208                                                 sfp = <&sff2>;
 209                                         };
 210
 211                                         switch1port10: port@10 {
 212                                                 reg = <10>;
 213                                                 label = "dsa";
 214                                                 phy-mode = "xaui";
 215                                                 link = <&switch0port10>;
 216                                         };
 217                                 };
 218                                 mdio {
 219                                         #address-cells = <1>;
 220                                         #size-cells = <0>;
 221
 222                                         switch1phy1: switch1phy@1 {
 223                                                 reg = <1>;
 224                                                 interrupt-parent = <&switch1>;
 225                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 226                                         };
 227
 228                                         switch1phy2: switch1phy@2 {
 229                                                 reg = <2>;
 230                                                 interrupt-parent = <&switch1>;
 231                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 232                                         };
 233
 234                                         switch1phy3: switch1phy@3 {
 235                                                 reg = <3>;
 236                                                 interrupt-parent = <&switch1>;
 237                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 238                                         };
 239
 240                                         switch1phy4: switch1phy@4 {
 241                                                 reg = <4>;
 242                                                 interrupt-parent = <&switch1>;
 243                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 244                                         };
 245                                 };
 246                         };
 247                 };
 248
 249                 mdio_mux_4: mdio@4 {
 250                         reg = <4>;
 251                         #address-cells = <1>;
 252                         #size-cells = <0>;
 253                 };
 254         };
 255
 256         sff2: sff2 {
 257                 /* lower */
 258                 compatible = "sff,sff";
 259                 i2c-bus = <&sff2_i2c>;
 260                 los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
 261                 tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
 262         };
 263
 264         sff3: sff3 {
 265                 /* upper */
 266                 compatible = "sff,sff";
 267                 i2c-bus = <&sff3_i2c>;
 268                 los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 269                 tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
 270         };
 271 };
 272
 273 &dspi0 {
 274         bus-num = <0>;
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_dspi0>;
 277         status = "okay";
 278         spi-num-chipselects = <2>;
 279
 280         m25p128@0 {
 281                 compatible = "m25p128", "jedec,spi-nor";
 282                 #address-cells = <1>;
 283                 #size-cells = <1>;
 284                 reg = <0>;
 285                 spi-max-frequency = <1000000>;
 286         };
 287
 288         atzb-rf-233@1 {
 289                 compatible = "atmel,at86rf233";
 290
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&pinctr_atzb_rf_233>;
 293
 294                 spi-max-frequency = <7500000>;
 295                 reg = <1>;
 296                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 297                 interrupt-parent = <&gpio3>;
 298                 xtal-trim = /bits/ 8 <0x06>;
 299
 300                 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
 301                 reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
 302
 303                 fsl,spi-cs-sck-delay = <180>;
 304                 fsl,spi-sck-cs-delay = <250>;
 305         };
 306 };
 307
 308 &i2c0 {
 309         /*
 310          * U712
 311          *
 312          * Exposed signals:
 313          *    P1 - WE2_CMD
 314          *    P2 - WE2_CLK
 315          */
 316         gpio5: pca9557@18 {
 317                 compatible = "nxp,pca9557";
 318                 reg = <0x18>;
 319                 gpio-controller;
 320                 #gpio-cells = <2>;
 321         };
 322
 323         /*
 324          * U121
 325          *
 326          * Exposed signals:
 327          *    I/O0  - ENET_SWR_EN
 328          *    I/O1  - ESW1_RESETn
 329          *    I/O2  - ARINC_RESET
 330          *    I/O3  - DD1_IO_RESET
 331          *    I/O4  - ESW2_RESETn
 332          *    I/O5  - ESW3_RESETn
 333          *    I/O6  - ESW4_RESETn
 334          *    I/O8  - TP909
 335          *    I/O9  - FEM_SEL
 336          *    I/O10 - WIFI_RESETn
 337          *    I/O11 - PHY_RSTn
 338          *    I/O12 - OPT1_SD
 339          *    I/O13 - OPT2_SD
 340          *    I/O14 - OPT1_TX_DIS
 341          *    I/O15 - OPT2_TX_DIS
 342          */
 343         gpio6: sx1503@20 {
 344                 compatible = "semtech,sx1503q";
 345
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&pinctrl_sx1503_20>;
 348                 #gpio-cells = <2>;
 349                 #interrupt-cells = <2>;
 350                 reg = <0x20>;
 351                 interrupt-parent = <&gpio0>;
 352                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
 353                 gpio-controller;
 354                 interrupt-controller;
 355         };
 356
 357         /*
 358          * U715
 359          *
 360          * Exposed signals:
 361          *     IO0 - WE1_CLK
 362          *     IO1 - WE1_CMD
 363          */
 364         gpio7: pca9554@22 {
 365                 compatible = "nxp,pca9554";
 366                 reg = <0x22>;
 367                 gpio-controller;
 368                 #gpio-cells = <2>;
 369
 370         };
 371 };
 372
 373 &i2c1 {
 374         at24mac602@50 {
 375                 compatible = "atmel,24c02";
 376                 reg = <0x50>;
 377                 read-only;
 378         };
 379 };
 380
 381 &i2c2 {
 382         tca9548@70 {
 383                 compatible = "nxp,pca9548";
 384                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 385                 pinctrl-names = "default";
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 reg = <0x70>;
 389                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 390
 391                 i2c@0 {
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         reg = <0>;
 395                 };
 396
 397                 sff2_i2c: i2c@1 {
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         reg = <1>;
 401                 };
 402
 403                 sff3_i2c: i2c@2 {
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         reg = <2>;
 407                 };
 408
 409                 i2c@3 {
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         reg = <3>;
 413                 };
 414         };
 415 };
 416
 417 &uart3 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_uart3>;
 420         status = "okay";
 421 };
 422
 423 &gpio0 {
 424         eth0_intrp {
 425                 gpio-hog;
 426                 gpios = <23 GPIO_ACTIVE_HIGH>;
 427                 input;
 428                 line-name = "sx1503-irq";
 429         };
 430 };
 431
 432 &gpio3 {
 433         eth0_intrp {
 434                 gpio-hog;
 435                 gpios = <2 GPIO_ACTIVE_HIGH>;
 436                 input;
 437                 line-name = "eth0-intrp";
 438         };
 439 };
 440
 441 &fec0 {
 442         mdio {
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 status = "okay";
 446
 447                 ethernet-phy@0 {
 448                         compatible = "ethernet-phy-ieee802.3-c22";
 449
 450                         pinctrl-names = "default";
 451                         pinctrl-0 = <&pinctrl_fec0_phy_int>;
 452
 453                         interrupt-parent = <&gpio3>;
 454                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 455                         reg = <0>;
 456                 };
 457         };
 458 };
 459
 460 &iomuxc {
 461         pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
 462                 fsl,pins = <
 463                         VF610_PAD_PTB2__GPIO_24         0x31c2
 464                         VF610_PAD_PTE27__GPIO_132       0x33e2
 465                 >;
 466         };
 467
 468
 469         pinctrl_sx1503_20: pinctrl-sx1503-20 {
 470                 fsl,pins = <
 471                         VF610_PAD_PTB1__GPIO_23         0x219d
 472                 >;
 473         };
 474
 475         pinctrl_uart3: uart3grp {
 476                 fsl,pins = <
 477                         VF610_PAD_PTA20__UART3_TX       0x21a2
 478                         VF610_PAD_PTA21__UART3_RX       0x21a1
 479                 >;
 480         };
 481
 482         pinctrl_mdio_mux: pinctrl-mdio-mux {
 483                 fsl,pins = <
 484                         VF610_PAD_PTA18__GPIO_8         0x31c2
 485                         VF610_PAD_PTA19__GPIO_9         0x31c2
 486                         VF610_PAD_PTB3__GPIO_25         0x31c2
 487                 >;
 488         };
 489
 490         pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
 491                 fsl,pins = <
 492                         VF610_PAD_PTB28__GPIO_98        0x219d
 493                 >;
 494         };
 495 };