arch/arm/boot/dts/vf610-zii-dev-rev-c.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev C";
  50         compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  59                 mdio-parent-bus = <&mdio1>;
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 mdio_mux_1: mdio@1 {
  64                         reg = <1>;
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67
  68                         switch0: switch@0 {
  69                                 compatible = "marvell,mv88e6190";
  70                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  71                                 pinctrl-names = "default";
  72                                 reg = <0>;
  73                                 dsa,member = <0 0>;
  74                                 eeprom-length = <65536>;
  75                                 interrupt-parent = <&gpio0>;
  76                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  77                                 interrupt-controller;
  78                                 #interrupt-cells = <2>;
  79
  80                                 ports {
  81                                         #address-cells = <1>;
  82                                         #size-cells = <0>;
  83
  84                                         port@0 {
  85                                                 reg = <0>;
  86                                                 label = "cpu";
  87                                                 ethernet = <&fec1>;
  88
  89                                                 fixed-link {
  90                                                         speed = <100>;
  91                                                         full-duplex;
  92                                                 };
  93                                         };
  94
  95                                         port@1 {
  96                                                 reg = <1>;
  97                                                 label = "lan1";
  98                                                 phy-handle = <&switch0phy1>;
  99                                         };
 100
 101                                         port@2 {
 102                                                 reg = <2>;
 103                                                 label = "lan2";
 104                                                 phy-handle = <&switch0phy2>;
 105                                         };
 106
 107                                         port@3 {
 108                                                 reg = <3>;
 109                                                 label = "lan3";
 110                                                 phy-handle = <&switch0phy3>;
 111                                         };
 112
 113                                         port@4 {
 114                                                 reg = <4>;
 115                                                 label = "lan4";
 116                                                 phy-handle = <&switch0phy4>;
 117                                         };
 118
 119                                         switch0port10: port@10 {
 120                                                 reg = <10>;
 121                                                 label = "dsa";
 122                                                 phy-mode = "xaui";
 123                                                 link = <&switch1port10>;
 124                                         };
 125                                 };
 126
 127                                 mdio {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130
 131                                         switch0phy1: switch0phy@1 {
 132                                                 reg = <1>;
 133                                                 interrupt-parent = <&switch0>;
 134                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 135                                         };
 136
 137                                         switch0phy2: switch0phy@2 {
 138                                                 reg = <2>;
 139                                                 interrupt-parent = <&switch0>;
 140                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 141                                         };
 142
 143                                         switch0phy3: switch0phy@3 {
 144                                                 reg = <3>;
 145                                                 interrupt-parent = <&switch0>;
 146                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 147                                         };
 148
 149                                         switch0phy4: switch0phy@4 {
 150                                                 reg = <4>;
 151                                                 interrupt-parent = <&switch0>;
 152                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 153                                         };
 154                                 };
 155                         };
 156                 };
 157
 158                 mdio_mux_2: mdio@2 {
 159                         reg = <2>;
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162
 163                         switch1: switch@0 {
 164                                 compatible = "marvell,mv88e6190";
 165                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 166                                 pinctrl-names = "default";
 167                                 reg = <0>;
 168                                 dsa,member = <0 1>;
 169                                 eeprom-length = <65536>;
 170                                 interrupt-parent = <&gpio0>;
 171                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 172                                 interrupt-controller;
 173                                 #interrupt-cells = <2>;
 174
 175                                 ports {
 176                                         #address-cells = <1>;
 177                                         #size-cells = <0>;
 178
 179                                         port@1 {
 180                                                 reg = <1>;
 181                                                 label = "lan5";
 182                                                 phy-handle = <&switch1phy1>;
 183                                         };
 184
 185                                         port@2 {
 186                                                 reg = <2>;
 187                                                 label = "lan6";
 188                                                 phy-handle = <&switch1phy2>;
 189                                         };
 190
 191                                         port@3 {
 192                                                 reg = <3>;
 193                                                 label = "lan7";
 194                                                 phy-handle = <&switch1phy3>;
 195                                         };
 196
 197                                         port@4 {
 198                                                 reg = <4>;
 199                                                 label = "lan8";
 200                                                 phy-handle = <&switch1phy4>;
 201                                         };
 202
 203
 204                                         switch1port10: port@10 {
 205                                                 reg = <10>;
 206                                                 label = "dsa";
 207                                                 phy-mode = "xaui";
 208                                                 link = <&switch0port10>;
 209                                         };
 210                                 };
 211                                 mdio {
 212                                         #address-cells = <1>;
 213                                         #size-cells = <0>;
 214
 215                                         switch1phy1: switch1phy@1 {
 216                                                 reg = <1>;
 217                                                 interrupt-parent = <&switch1>;
 218                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 219                                         };
 220
 221                                         switch1phy2: switch1phy@2 {
 222                                                 reg = <2>;
 223                                                 interrupt-parent = <&switch1>;
 224                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 225                                         };
 226
 227                                         switch1phy3: switch1phy@3 {
 228                                                 reg = <3>;
 229                                                 interrupt-parent = <&switch1>;
 230                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 231                                         };
 232
 233                                         switch1phy4: switch1phy@4 {
 234                                                 reg = <4>;
 235                                                 interrupt-parent = <&switch1>;
 236                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 237                                         };
 238                                 };
 239                         };
 240                 };
 241
 242                 mdio_mux_4: mdio@4 {
 243                         reg = <4>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                 };
 247         };
 248 };
 249
 250 &dspi0 {
 251         bus-num = <0>;
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_dspi0>;
 254         status = "okay";
 255         spi-num-chipselects = <2>;
 256
 257         m25p128@0 {
 258                 compatible = "m25p128", "jedec,spi-nor";
 259                 #address-cells = <1>;
 260                 #size-cells = <1>;
 261                 reg = <0>;
 262                 spi-max-frequency = <1000000>;
 263         };
 264
 265         atzb-rf-233@1 {
 266                 compatible = "atmel,at86rf233";
 267
 268                 pinctrl-names = "default";
 269                 pinctrl-0 = <&pinctr_atzb_rf_233>;
 270
 271                 spi-max-frequency = <7500000>;
 272                 reg = <1>;
 273                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 274                 interrupt-parent = <&gpio3>;
 275                 xtal-trim = /bits/ 8 <0x06>;
 276
 277                 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
 278                 reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
 279
 280                 fsl,spi-cs-sck-delay = <180>;
 281                 fsl,spi-sck-cs-delay = <250>;
 282         };
 283 };
 284
 285 &i2c0 {
 286         /*
 287          * U712
 288          *
 289          * Exposed signals:
 290          *    P1 - WE2_CMD
 291          *    P2 - WE2_CLK
 292          */
 293         gpio5: pca9557@18 {
 294                 compatible = "nxp,pca9557";
 295                 reg = <0x18>;
 296                 gpio-controller;
 297                 #gpio-cells = <2>;
 298         };
 299
 300         /*
 301          * U121
 302          *
 303          * Exposed signals:
 304          *    I/O0  - ENET_SWR_EN
 305          *    I/O1  - ESW1_RESETn
 306          *    I/O2  - ARINC_RESET
 307          *    I/O3  - DD1_IO_RESET
 308          *    I/O4  - ESW2_RESETn
 309          *    I/O5  - ESW3_RESETn
 310          *    I/O6  - ESW4_RESETn
 311          *    I/O8  - TP909
 312          *    I/O9  - FEM_SEL
 313          *    I/O10 - WIFI_RESETn
 314          *    I/O11 - PHY_RSTn
 315          *    I/O12 - OPT1_SD
 316          *    I/O13 - OPT2_SD
 317          *    I/O14 - OPT1_TX_DIS
 318          *    I/O15 - OPT2_TX_DIS
 319          */
 320         gpio6: sx1503@20 {
 321                 compatible = "semtech,sx1503q";
 322
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&pinctrl_sx1503_20>;
 325                 #gpio-cells = <2>;
 326                 #interrupt-cells = <2>;
 327                 reg = <0x20>;
 328                 interrupt-parent = <&gpio0>;
 329                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
 330                 gpio-controller;
 331                 interrupt-controller;
 332
 333                 enet_swr_en {
 334                         gpio-hog;
 335                         gpios = <0 GPIO_ACTIVE_HIGH>;
 336                         output-high;
 337                         line-name = "enet-swr-en";
 338                 };
 339         };
 340
 341         /*
 342          * U715
 343          *
 344          * Exposed signals:
 345          *     IO0 - WE1_CLK
 346          *     IO1 - WE1_CMD
 347          */
 348         gpio7: pca9554@22 {
 349                 compatible = "nxp,pca9554";
 350                 reg = <0x22>;
 351                 gpio-controller;
 352                 #gpio-cells = <2>;
 353
 354         };
 355 };
 356
 357 &i2c1 {
 358         at24mac602@50 {
 359                 compatible = "atmel,24c02";
 360                 reg = <0x50>;
 361                 read-only;
 362         };
 363 };
 364
 365 &i2c2 {
 366         tca9548@70 {
 367                 compatible = "nxp,pca9548";
 368                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 369                 pinctrl-names = "default";
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 reg = <0x70>;
 373                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 374
 375                 i2c@0 {
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         reg = <0>;
 379                 };
 380
 381                 i2c@1 {
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         reg = <1>;
 385
 386                         sfp2: at24c04@50 {
 387                                 compatible = "atmel,24c02";
 388                                 reg = <0x50>;
 389                         };
 390                 };
 391
 392                 i2c@2 {
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         reg = <2>;
 396
 397                         sfp3: at24c04@50 {
 398                                 compatible = "atmel,24c02";
 399                                 reg = <0x50>;
 400                         };
 401                 };
 402
 403                 i2c@3 {
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         reg = <3>;
 407                 };
 408         };
 409 };
 410
 411 &uart3 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_uart3>;
 414         status = "okay";
 415 };
 416
 417 &gpio0 {
 418         eth0_intrp {
 419                 gpio-hog;
 420                 gpios = <23 GPIO_ACTIVE_HIGH>;
 421                 input;
 422                 line-name = "sx1503-irq";
 423         };
 424 };
 425
 426 &gpio3 {
 427         eth0_intrp {
 428                 gpio-hog;
 429                 gpios = <2 GPIO_ACTIVE_HIGH>;
 430                 input;
 431                 line-name = "eth0-intrp";
 432         };
 433 };
 434
 435 &fec0 {
 436         mdio {
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 status = "okay";
 440
 441                 ethernet-phy@0 {
 442                         compatible = "ethernet-phy-ieee802.3-c22";
 443
 444                         pinctrl-names = "default";
 445                         pinctrl-0 = <&pinctrl_fec0_phy_int>;
 446
 447                         interrupt-parent = <&gpio3>;
 448                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 449                         reg = <0>;
 450                 };
 451         };
 452 };
 453
 454 &iomuxc {
 455         pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
 456                 fsl,pins = <
 457                         VF610_PAD_PTB2__GPIO_24         0x31c2
 458                         VF610_PAD_PTE27__GPIO_132       0x33e2
 459                 >;
 460         };
 461
 462
 463         pinctrl_sx1503_20: pinctrl-sx1503-20 {
 464                 fsl,pins = <
 465                         VF610_PAD_PTB1__GPIO_23         0x219d
 466                 >;
 467         };
 468
 469         pinctrl_uart3: uart3grp {
 470                 fsl,pins = <
 471                         VF610_PAD_PTA20__UART3_TX       0x21a2
 472                         VF610_PAD_PTA21__UART3_RX       0x21a1
 473                 >;
 474         };
 475
 476         pinctrl_mdio_mux: pinctrl-mdio-mux {
 477                 fsl,pins = <
 478                         VF610_PAD_PTA18__GPIO_8         0x31c2
 479                         VF610_PAD_PTA19__GPIO_9         0x31c2
 480                         VF610_PAD_PTB3__GPIO_25         0x31c2
 481                 >;
 482         };
 483
 484         pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
 485                 fsl,pins = <
 486                         VF610_PAD_PTB28__GPIO_98        0x219d
 487                 >;
 488         };
 489 };