arch/arm/boot/dts/vf610-zii-dev-rev-c.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev C";
  50         compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  59                 mdio-parent-bus = <&mdio1>;
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 mdio_mux_1: mdio@1 {
  64                         reg = <1>;
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67
  68                         switch0: switch@0 {
  69                                 compatible = "marvell,mv88e6190";
  70                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  71                                 pinctrl-names = "default";
  72                                 #address-cells = <1>;
  73                                 #size-cells = <0>;
  74                                 reg = <0>;
  75                                 dsa,member = <0 0>;
  76                                 eeprom-length = <512>;
  77                                 interrupt-parent = <&gpio0>;
  78                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  79                                 interrupt-controller;
  80                                 #interrupt-cells = <2>;
  81
  82                                 ports {
  83                                         #address-cells = <1>;
  84                                         #size-cells = <0>;
  85
  86                                         port@0 {
  87                                                 reg = <0>;
  88                                                 label = "cpu";
  89                                                 ethernet = <&fec1>;
  90
  91                                                 fixed-link {
  92                                                         speed = <100>;
  93                                                         full-duplex;
  94                                                 };
  95                                         };
  96
  97                                         port@1 {
  98                                                 reg = <1>;
  99                                                 label = "lan1";
 100                                                 phy-handle = <&switch0phy1>;
 101                                         };
 102
 103                                         port@2 {
 104                                                 reg = <2>;
 105                                                 label = "lan2";
 106                                                 phy-handle = <&switch0phy2>;
 107                                         };
 108
 109                                         port@3 {
 110                                                 reg = <3>;
 111                                                 label = "lan3";
 112                                                 phy-handle = <&switch0phy3>;
 113                                         };
 114
 115                                         port@4 {
 116                                                 reg = <4>;
 117                                                 label = "lan4";
 118                                                 phy-handle = <&switch0phy4>;
 119                                         };
 120
 121                                         switch0port10: port@10 {
 122                                                 reg = <10>;
 123                                                 label = "dsa";
 124                                                 phy-mode = "xgmii";
 125                                                 link = <&switch1port10>;
 126                                         };
 127                                 };
 128
 129                                 mdio {
 130                                         #address-cells = <1>;
 131                                         #size-cells = <0>;
 132
 133                                         switch0phy1: switch0phy@1 {
 134                                                 reg = <1>;
 135                                                 interrupt-parent = <&switch0>;
 136                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 137                                         };
 138
 139                                         switch0phy2: switch0phy@2 {
 140                                                 reg = <2>;
 141                                                 interrupt-parent = <&switch0>;
 142                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 143                                         };
 144
 145                                         switch0phy3: switch0phy@3 {
 146                                                 reg = <3>;
 147                                                 interrupt-parent = <&switch0>;
 148                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 149                                         };
 150
 151                                         switch0phy4: switch0phy@4 {
 152                                                 reg = <4>;
 153                                                 interrupt-parent = <&switch0>;
 154                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 155                                         };
 156                                 };
 157                         };
 158                 };
 159
 160                 mdio_mux_2: mdio@2 {
 161                         reg = <2>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164
 165                         switch1: switch@0 {
 166                                 compatible = "marvell,mv88e6190";
 167                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 168                                 pinctrl-names = "default";
 169                                 #address-cells = <1>;
 170                                 #size-cells = <0>;
 171                                 reg = <0>;
 172                                 dsa,member = <0 1>;
 173                                 eeprom-length = <512>;
 174                                 interrupt-parent = <&gpio0>;
 175                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 176                                 interrupt-controller;
 177                                 #interrupt-cells = <2>;
 178
 179                                 ports {
 180                                         #address-cells = <1>;
 181                                         #size-cells = <0>;
 182
 183                                         port@1 {
 184                                                 reg = <1>;
 185                                                 label = "lan5";
 186                                                 phy-handle = <&switch1phy1>;
 187                                         };
 188
 189                                         port@2 {
 190                                                 reg = <2>;
 191                                                 label = "lan6";
 192                                                 phy-handle = <&switch1phy2>;
 193                                         };
 194
 195                                         port@3 {
 196                                                 reg = <3>;
 197                                                 label = "lan7";
 198                                                 phy-handle = <&switch1phy3>;
 199                                         };
 200
 201                                         port@4 {
 202                                                 reg = <4>;
 203                                                 label = "lan8";
 204                                                 phy-handle = <&switch1phy4>;
 205                                         };
 206
 207
 208                                         switch1port10: port@10 {
 209                                                 reg = <10>;
 210                                                 label = "dsa";
 211                                                 phy-mode = "xgmii";
 212                                                 link = <&switch0port10>;
 213                                         };
 214                                 };
 215                                 mdio {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218
 219                                         switch1phy1: switch1phy@1 {
 220                                                 reg = <1>;
 221                                                 interrupt-parent = <&switch1>;
 222                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 223                                         };
 224
 225                                         switch1phy2: switch1phy@2 {
 226                                                 reg = <2>;
 227                                                 interrupt-parent = <&switch1>;
 228                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 229                                         };
 230
 231                                         switch1phy3: switch1phy@3 {
 232                                                 reg = <3>;
 233                                                 interrupt-parent = <&switch1>;
 234                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 235                                         };
 236
 237                                         switch1phy4: switch1phy@4 {
 238                                                 reg = <4>;
 239                                                 interrupt-parent = <&switch1>;
 240                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 241                                         };
 242                                 };
 243                         };
 244                 };
 245
 246                 mdio_mux_4: mdio@4 {
 247                         reg = <4>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                 };
 251         };
 252 };
 253
 254 &dspi0 {
 255         bus-num = <0>;
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_dspi0>;
 258         status = "okay";
 259         spi-num-chipselects = <2>;
 260
 261         m25p128@0 {
 262                 compatible = "m25p128", "jedec,spi-nor";
 263                 #address-cells = <1>;
 264                 #size-cells = <1>;
 265                 reg = <0>;
 266                 spi-max-frequency = <1000000>;
 267         };
 268
 269         atzb-rf-233@1 {
 270                 compatible = "atmel,at86rf233";
 271
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&pinctr_atzb_rf_233>;
 274
 275                 spi-max-frequency = <7500000>;
 276                 reg = <1>;
 277                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 278                 interrupt-parent = <&gpio3>;
 279                 xtal-trim = /bits/ 8 <0x06>;
 280
 281                 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
 282                 reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
 283
 284                 fsl,spi-cs-sck-delay = <180>;
 285                 fsl,spi-sck-cs-delay = <250>;
 286         };
 287 };
 288
 289 &i2c0 {
 290         /*
 291          * U712
 292          *
 293          * Exposed signals:
 294          *    P1 - WE2_CMD
 295          *    P2 - WE2_CLK
 296          */
 297         gpio5: pca9557@18 {
 298                 compatible = "nxp,pca9557";
 299                 reg = <0x18>;
 300                 gpio-controller;
 301                 #gpio-cells = <2>;
 302         };
 303
 304         /*
 305          * U121
 306          *
 307          * Exposed signals:
 308          *    I/O0  - ENET_SWR_EN
 309          *    I/O1  - ESW1_RESETn
 310          *    I/O2  - ARINC_RESET
 311          *    I/O3  - DD1_IO_RESET
 312          *    I/O4  - ESW2_RESETn
 313          *    I/O5  - ESW3_RESETn
 314          *    I/O6  - ESW4_RESETn
 315          *    I/O8  - TP909
 316          *    I/O9  - FEM_SEL
 317          *    I/O10 - WIFI_RESETn
 318          *    I/O11 - PHY_RSTn
 319          *    I/O12 - OPT1_SD
 320          *    I/O13 - OPT2_SD
 321          *    I/O14 - OPT1_TX_DIS
 322          *    I/O15 - OPT2_TX_DIS
 323          */
 324         gpio6: sx1503@20 {
 325                 compatible = "semtech,sx1503q";
 326
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&pinctrl_sx1503_20>;
 329                 #gpio-cells = <2>;
 330                 #interrupt-cells = <2>;
 331                 reg = <0x20>;
 332                 interrupt-parent = <&gpio0>;
 333                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
 334                 gpio-controller;
 335                 interrupt-controller;
 336
 337                 enet_swr_en {
 338                         gpio-hog;
 339                         gpios = <0 GPIO_ACTIVE_HIGH>;
 340                         output-high;
 341                         line-name = "enet-swr-en";
 342                 };
 343         };
 344
 345         /*
 346          * U715
 347          *
 348          * Exposed signals:
 349          *     IO0 - WE1_CLK
 350          *     IO1 - WE1_CMD
 351          */
 352         gpio7: pca9554@22 {
 353                 compatible = "nxp,pca9554";
 354                 reg = <0x22>;
 355                 gpio-controller;
 356                 #gpio-cells = <2>;
 357
 358         };
 359 };
 360
 361 &i2c1 {
 362         at24mac602@0 {
 363                 compatible = "atmel,24c02";
 364                 reg = <0x50>;
 365                 read-only;
 366         };
 367 };
 368
 369 &i2c2 {
 370         tca9548@70 {
 371                 compatible = "nxp,pca9548";
 372                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 373                 pinctrl-names = "default";
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 reg = <0x70>;
 377                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 378
 379                 i2c@0 {
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         reg = <0>;
 383                 };
 384
 385                 i2c@1 {
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         reg = <1>;
 389
 390                         sfp2: at24c04@50 {
 391                                 compatible = "atmel,24c02";
 392                                 reg = <0x50>;
 393                         };
 394                 };
 395
 396                 i2c@2 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         reg = <2>;
 400
 401                         sfp3: at24c04@50 {
 402                                 compatible = "atmel,24c02";
 403                                 reg = <0x50>;
 404                         };
 405                 };
 406
 407                 i2c@3 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         reg = <3>;
 411                 };
 412         };
 413 };
 414
 415 &uart3 {
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&pinctrl_uart3>;
 418         status = "okay";
 419 };
 420
 421 &gpio0 {
 422         eth0_intrp {
 423                 gpio-hog;
 424                 gpios = <23 GPIO_ACTIVE_HIGH>;
 425                 input;
 426                 line-name = "sx1503-irq";
 427         };
 428 };
 429
 430 &gpio3 {
 431         eth0_intrp {
 432                 gpio-hog;
 433                 gpios = <2 GPIO_ACTIVE_HIGH>;
 434                 input;
 435                 line-name = "eth0-intrp";
 436         };
 437 };
 438
 439 &fec0 {
 440         mdio {
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 status = "okay";
 444
 445                 ethernet-phy@0 {
 446                         compatible = "ethernet-phy-ieee802.3-c22";
 447
 448                         pinctrl-names = "default";
 449                         pinctrl-0 = <&pinctrl_fec0_phy_int>;
 450
 451                         interrupt-parent = <&gpio3>;
 452                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 453                         reg = <0>;
 454                 };
 455         };
 456 };
 457
 458 &iomuxc {
 459         pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
 460                 fsl,pins = <
 461                         VF610_PAD_PTB2__GPIO_24         0x31c2
 462                         VF610_PAD_PTE27__GPIO_132       0x33e2
 463                 >;
 464         };
 465
 466
 467         pinctrl_sx1503_20: pinctrl-sx1503-20 {
 468                 fsl,pins = <
 469                         VF610_PAD_PTB1__GPIO_23         0x219d
 470                 >;
 471         };
 472
 473         pinctrl_uart3: uart3grp {
 474                 fsl,pins = <
 475                         VF610_PAD_PTA20__UART3_TX       0x21a2
 476                         VF610_PAD_PTA21__UART3_RX       0x21a1
 477                 >;
 478         };
 479
 480         pinctrl_mdio_mux: pinctrl-mdio-mux {
 481                 fsl,pins = <
 482                         VF610_PAD_PTA18__GPIO_8         0x31c2
 483                         VF610_PAD_PTA19__GPIO_9         0x31c2
 484                         VF610_PAD_PTB3__GPIO_25         0x31c2
 485                 >;
 486         };
 487
 488         pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
 489                 fsl,pins = <
 490                         VF610_PAD_PTB28__GPIO_98        0x219d
 491                 >;
 492         };
 493 };