arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev B";
  50         compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 24 GPIO_ACTIVE_HIGH
  59                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  60                 mdio-parent-bus = <&mdio1>;
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 mdio_mux_1: mdio@1 {
  65                         reg = <1>;
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68
  69                         switch0: switch@0 {
  70                                 compatible = "marvell,mv88e6085";
  71                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  72                                 pinctrl-names = "default";
  73                                 #address-cells = <1>;
  74                                 #size-cells = <0>;
  75                                 reg = <0>;
  76                                 dsa,member = <0 0>;
  77                                 interrupt-parent = <&gpio0>;
  78                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  79                                 interrupt-controller;
  80                                 #interrupt-cells = <2>;
  81                                 eeprom-length = <512>;
  82
  83                                 ports {
  84                                         #address-cells = <1>;
  85                                         #size-cells = <0>;
  86
  87                                         port@0 {
  88                                                 reg = <0>;
  89                                                 label = "lan0";
  90                                                 phy-handle = <&switch0phy0>;
  91                                         };
  92
  93                                         port@1 {
  94                                                 reg = <1>;
  95                                                 label = "lan1";
  96                                                 phy-handle = <&switch0phy1>;
  97                                         };
  98
  99                                         port@2 {
 100                                                 reg = <2>;
 101                                                 label = "lan2";
 102                                                 phy-handle = <&switch0phy2>;
 103                                         };
 104
 105                                         switch0port5: port@5 {
 106                                                 reg = <5>;
 107                                                 label = "dsa";
 108                                                 phy-mode = "rgmii-txid";
 109                                                 link = <&switch1port6
 110                                                         &switch2port9>;
 111                                                 fixed-link {
 112                                                         speed = <1000>;
 113                                                         full-duplex;
 114                                                 };
 115                                         };
 116
 117                                         port@6 {
 118                                                 reg = <6>;
 119                                                 label = "cpu";
 120                                                 ethernet = <&fec1>;
 121
 122                                                 fixed-link {
 123                                                         speed = <100>;
 124                                                         full-duplex;
 125                                                 };
 126                                         };
 127                                 };
 128                                 mdio {
 129                                         #address-cells = <1>;
 130                                         #size-cells = <0>;
 131                                         switch0phy0: switch0phy0@0 {
 132                                                 reg = <0>;
 133                                                 interrupt-parent = <&switch0>;
 134                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 135                                         };
 136                                         switch0phy1: switch1phy0@1 {
 137                                                 reg = <1>;
 138                                                 interrupt-parent = <&switch0>;
 139                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 140                                         };
 141                                         switch0phy2: switch1phy0@2 {
 142                                                 reg = <2>;
 143                                                 interrupt-parent = <&switch0>;
 144                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 145                                         };
 146                                 };
 147                         };
 148                 };
 149
 150                 mdio_mux_2: mdio@2 {
 151                         reg = <2>;
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154
 155                         switch1: switch@0 {
 156                                 compatible = "marvell,mv88e6085";
 157                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 158                                 pinctrl-names = "default";
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                                 reg = <0>;
 162                                 dsa,member = <0 1>;
 163                                 interrupt-parent = <&gpio0>;
 164                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 165                                 interrupt-controller;
 166                                 #interrupt-cells = <2>;
 167                                 eeprom-length = <512>;
 168
 169                                 ports {
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172
 173                                         port@0 {
 174                                                 reg = <0>;
 175                                                 label = "lan3";
 176                                                 phy-handle = <&switch1phy0>;
 177                                         };
 178
 179                                         port@1 {
 180                                                 reg = <1>;
 181                                                 label = "lan4";
 182                                                 phy-handle = <&switch1phy1>;
 183                                         };
 184
 185                                         port@2 {
 186                                                 reg = <2>;
 187                                                 label = "lan5";
 188                                                 phy-handle = <&switch1phy2>;
 189                                         };
 190
 191                                         switch1port5: port@5 {
 192                                                 reg = <5>;
 193                                                 label = "dsa";
 194                                                 link = <&switch2port9>;
 195                                                 phy-mode = "rgmii-txid";
 196
 197                                                 fixed-link {
 198                                                         speed = <1000>;
 199                                                         full-duplex;
 200                                                 };
 201                                         };
 202
 203                                         switch1port6: port@6 {
 204                                                 reg = <6>;
 205                                                 label = "dsa";
 206                                                 phy-mode = "rgmii-txid";
 207                                                 link = <&switch0port5>;
 208                                                 fixed-link {
 209                                                         speed = <1000>;
 210                                                         full-duplex;
 211                                                 };
 212                                         };
 213                                 };
 214                                 mdio {
 215                                         #address-cells = <1>;
 216                                         #size-cells = <0>;
 217
 218                                         switch1phy0: switch1phy0@0 {
 219                                                 reg = <0>;
 220                                                 interrupt-parent = <&switch1>;
 221                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 222                                         };
 223
 224                                         switch1phy1: switch1phy0@1 {
 225                                                 reg = <1>;
 226                                                 interrupt-parent = <&switch1>;
 227                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 228                                         };
 229
 230                                         switch1phy2: switch1phy0@2 {
 231                                                 reg = <2>;
 232                                                 interrupt-parent = <&switch1>;
 233                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 234                                         };
 235                                 };
 236                         };
 237                 };
 238
 239                 mdio_mux_4: mdio@4 {
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         reg = <4>;
 243
 244                         switch2: switch@0 {
 245                                 compatible = "marvell,mv88e6085";
 246                                 #address-cells = <1>;
 247                                 #size-cells = <0>;
 248                                 reg = <0>;
 249                                 dsa,member = <0 2>;
 250
 251                                 ports {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254
 255                                         port@0 {
 256                                                 reg = <0>;
 257                                                 label = "lan6";
 258                                                 phy-handle = <&switch2phy0>;
 259                                         };
 260
 261                                         port@1 {
 262                                                 reg = <1>;
 263                                                 label = "lan7";
 264                                                 phy-handle = <&switch2phy1>;
 265                                         };
 266
 267                                         port@2 {
 268                                                 reg = <2>;
 269                                                 label = "lan8";
 270                                                 phy-handle = <&switch2phy2>;
 271                                         };
 272
 273                                         port@3 {
 274                                                 reg = <3>;
 275                                                 label = "optical3";
 276
 277                                                 fixed-link {
 278                                                         speed = <1000>;
 279                                                         full-duplex;
 280                                                         link-gpios = <&gpio6 2
 281                                                               GPIO_ACTIVE_HIGH>;
 282                                                 };
 283                                         };
 284
 285                                         port@4 {
 286                                                 reg = <4>;
 287                                                 label = "optical4";
 288
 289                                                 fixed-link {
 290                                                         speed = <1000>;
 291                                                         full-duplex;
 292                                                         link-gpios = <&gpio6 3
 293                                                               GPIO_ACTIVE_HIGH>;
 294                                                 };
 295                                         };
 296
 297                                         switch2port9: port@9 {
 298                                                 reg = <9>;
 299                                                 label = "dsa";
 300                                                 phy-mode = "rgmii-txid";
 301                                                 link = <&switch1port5
 302                                                         &switch0port5>;
 303
 304                                                 fixed-link {
 305                                                         speed = <1000>;
 306                                                         full-duplex;
 307                                                 };
 308                                         };
 309                                 };
 310                                 mdio {
 311                                         #address-cells = <1>;
 312                                         #size-cells = <0>;
 313
 314                                         switch2phy0: phy@0 {
 315                                                 reg = <0>;
 316                                         };
 317                                         switch2phy1: phy@1 {
 318                                                 reg = <1>;
 319                                         };
 320                                         switch2phy2: phy@2 {
 321                                                 reg = <2>;
 322                                         };
 323                                 };
 324                         };
 325                 };
 326
 327                 mdio_mux_8: mdio@8 {
 328                         reg = <8>;
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                 };
 332         };
 333
 334         spi0 {
 335                 compatible = "spi-gpio";
 336                 pinctrl-0 = <&pinctrl_gpio_spi0>;
 337                 pinctrl-names = "default";
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 341                 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 342                 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 343                 cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
 344                              &gpio1  8 GPIO_ACTIVE_HIGH>;
 345                 num-chipselects = <2>;
 346
 347                 m25p128@0 {
 348                         compatible = "m25p128", "jedec,spi-nor";
 349                         #address-cells = <1>;
 350                         #size-cells = <1>;
 351                         reg = <0>;
 352                         spi-max-frequency = <1000000>;
 353                 };
 354
 355                 at93c46d@1 {
 356                         compatible = "atmel,at93c46d";
 357                         pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
 358                         pinctrl-names = "default";
 359                         #address-cells = <0>;
 360                         #size-cells = <0>;
 361                         reg = <1>;
 362                         spi-max-frequency = <500000>;
 363                         spi-cs-high;
 364                         data-size = <16>;
 365                         select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
 366                 };
 367         };
 368 };
 369
 370 &i2c0 {
 371         clock-frequency = <100000>;
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&pinctrl_i2c0>;
 374         status = "okay";
 375
 376         gpio5: pca9554@20 {
 377                 compatible = "nxp,pca9554";
 378                 reg = <0x20>;
 379                 gpio-controller;
 380                 #gpio-cells = <2>;
 381
 382         };
 383
 384         gpio6: pca9554@22 {
 385                 compatible = "nxp,pca9554";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pinctrl_pca9554_22>;
 388                 reg = <0x22>;
 389                 gpio-controller;
 390                 #gpio-cells = <2>;
 391                 interrupt-controller;
 392                 interrupt-parent = <&gpio3>;
 393                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 394         };
 395 };
 396
 397 &i2c2 {
 398         clock-frequency = <100000>;
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_i2c2>;
 401         status = "okay";
 402
 403         tca9548@70 {
 404                 compatible = "nxp,pca9548";
 405                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 406                 pinctrl-names = "default";
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 reg = <0x70>;
 410                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 411
 412                 i2c@0 {
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         reg = <0>;
 416
 417                         sfp1: at24c04@50 {
 418                                 compatible = "atmel,24c02";
 419                                 reg = <0x50>;
 420                         };
 421                 };
 422
 423                 i2c@1 {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         reg = <1>;
 427
 428                         sfp2: at24c04@50 {
 429                                 compatible = "atmel,24c02";
 430                                 reg = <0x50>;
 431                         };
 432                 };
 433
 434                 i2c@2 {
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         reg = <2>;
 438
 439                         sfp3: at24c04@50 {
 440                                 compatible = "atmel,24c02";
 441                                 reg = <0x50>;
 442                         };
 443                 };
 444
 445                 i2c@3 {
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         reg = <3>;
 449
 450                         sfp4: at24c04@50 {
 451                                 compatible = "atmel,24c02";
 452                                 reg = <0x50>;
 453                         };
 454                 };
 455
 456                 i2c@4 {
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         reg = <4>;
 460                 };
 461         };
 462 };
 463
 464
 465 &iomuxc {
 466         pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
 467                 fsl,pins = <
 468                         VF610_PAD_PTE27__GPIO_132       0x33e2
 469                 >;
 470         };
 471
 472         pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
 473                 fsl,pins = <
 474                         VF610_PAD_PTB22__GPIO_44        0x33e2
 475                         VF610_PAD_PTB21__GPIO_43        0x33e2
 476                         VF610_PAD_PTB20__GPIO_42        0x33e1
 477                         VF610_PAD_PTB19__GPIO_41        0x33e2
 478                         VF610_PAD_PTB18__GPIO_40        0x33e2
 479                 >;
 480         };
 481
 482         pinctrl_mdio_mux: pinctrl-mdio-mux {
 483                 fsl,pins = <
 484                         VF610_PAD_PTA18__GPIO_8         0x31c2
 485                         VF610_PAD_PTA19__GPIO_9         0x31c2
 486                         VF610_PAD_PTB2__GPIO_24         0x31c2
 487                         VF610_PAD_PTB3__GPIO_25         0x31c2
 488                 >;
 489         };
 490
 491         pinctrl_pca9554_22: pinctrl-pca95540-22 {
 492                 fsl,pins = <
 493                         VF610_PAD_PTB28__GPIO_98        0x219d
 494                 >;
 495         };
 496 };