arch/arm/boot/dts/vf610-zii-cfu1.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Copyright (C) 2018 Zodiac Inflight Innovations
   5  */
   6
   7 /dts-v1/;
   8 #include "vf610.dtsi"
   9
  10 / {
  11         model = "ZII VF610 CFU1 Board";
  12         compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";
  13
  14         chosen {
  15                 stdout-path = &uart0;
  16         };
  17
  18         memory@80000000 {
  19                 reg = <0x80000000 0x20000000>;
  20         };
  21
  22         gpio-leds {
  23                 compatible = "gpio-leds";
  24                 pinctrl-0 = <&pinctrl_leds_debug>;
  25                 pinctrl-names = "default";
  26
  27                 led-debug {
  28                         label = "zii:green:debug1";
  29                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  30                         linux,default-trigger = "heartbeat";
  31                         max-brightness = <1>;
  32                 };
  33
  34                 led-fail {
  35                         label = "zii:red:fail";
  36                         gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
  37                         default-state = "off";
  38                         max-brightness = <1>;
  39                 };
  40
  41                 led-status {
  42                         label = "zii:green:status";
  43                         gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  44                         default-state = "off";
  45                         max-brightness = <1>;
  46                 };
  47
  48                 led-debug-a {
  49                         label = "zii:green:debug_a";
  50                         gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
  51                         default-state = "off";
  52                         max-brightness = <1>;
  53                 };
  54
  55                 led-debug-b {
  56                         label = "zii:green:debug_b";
  57                         gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
  58                         default-state = "off";
  59                         max-brightness = <1>;
  60                 };
  61         };
  62
  63         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
  64                  compatible = "regulator-fixed";
  65                  regulator-name = "vcc_3v3_mcu";
  66                  regulator-min-microvolt = <3300000>;
  67                  regulator-max-microvolt = <3300000>;
  68         };
  69
  70         sff: sfp {
  71                 compatible = "sff,sff";
  72                 pinctrl-0 = <&pinctrl_optical>;
  73                 pinctrl-names = "default";
  74                 i2c-bus = <&i2c0>;
  75                 los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
  76                 tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  77         };
  78 };
  79
  80 &adc0 {
  81         vref-supply = <&reg_vcc_3v3_mcu>;
  82         status = "okay";
  83 };
  84
  85 &adc1 {
  86         vref-supply = <&reg_vcc_3v3_mcu>;
  87         status = "okay";
  88 };
  89
  90 &dspi1 {
  91         bus-num = <1>;
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_dspi1>;
  94         status = "okay";
  95
  96         m25p128@0 {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 compatible = "m25p128", "jedec,spi-nor";
 100                 reg = <0>;
 101                 spi-max-frequency = <50000000>;
 102
 103                 partition@0 {
 104                         label = "m25p128-0";
 105                         reg = <0x0 0x01000000>;
 106                 };
 107         };
 108 };
 109
 110 &edma0 {
 111         status = "okay";
 112 };
 113
 114 &edma1 {
 115         status = "okay";
 116 };
 117
 118 &esdhc0 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_esdhc0>;
 121         bus-width = <8>;
 122         non-removable;
 123         no-1-8-v;
 124         keep-power-in-suspend;
 125         no-sdio;
 126         no-sd;
 127         status = "okay";
 128 };
 129
 130 &esdhc1 {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_esdhc1>;
 133         bus-width = <4>;
 134         no-sdio;
 135         status = "okay";
 136 };
 137
 138 &fec1 {
 139         phy-mode = "rmii";
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_fec1>;
 142         status = "okay";
 143
 144         fixed-link {
 145                 speed = <100>;
 146                 full-duplex;
 147         };
 148
 149         mdio1: mdio {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 status = "okay";
 153
 154                 switch0: switch0@0 {
 155                         compatible = "marvell,mv88e6085";
 156                         pinctrl-names = "default";
 157                         pinctrl-0 = <&pinctrl_switch>;
 158                         reg = <0>;
 159                         eeprom-length = <512>;
 160                         interrupt-parent = <&gpio3>;
 161                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 162                         interrupt-controller;
 163                         #interrupt-cells = <2>;
 164                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 165
 166                         ports {
 167                                 #address-cells = <1>;
 168                                 #size-cells = <0>;
 169
 170                                 port@0 {
 171                                         reg = <0>;
 172                                         label = "eth_cu_1000_1";
 173                                 };
 174
 175                                 port@1 {
 176                                         reg = <1>;
 177                                         label = "eth_cu_1000_2";
 178                                 };
 179
 180                                 port@2 {
 181                                         reg = <2>;
 182                                         label = "eth_cu_1000_3";
 183                                 };
 184
 185                                 port@5 {
 186                                         reg = <5>;
 187                                         label = "eth_fc_1000_1";
 188                                         phy-mode = "1000base-x";
 189                                         managed = "in-band-status";
 190                                         sfp = <&sff>;
 191                                 };
 192
 193                                 port@6 {
 194                                         reg = <6>;
 195                                         label = "cpu";
 196                                         ethernet = <&fec1>;
 197
 198                                         fixed-link {
 199                                                 speed = <100>;
 200                                                 full-duplex;
 201                                         };
 202                                 };
 203                         };
 204                 };
 205         };
 206 };
 207
 208 &i2c0 {
 209         clock-frequency = <100000>;
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_i2c0>;
 212         status = "okay";
 213
 214         pca9554@22 {
 215                 compatible = "nxp,pca9554";
 216                 reg = <0x22>;
 217                 gpio-controller;
 218         };
 219
 220         lm75@48 {
 221                 compatible = "national,lm75";
 222                 reg = <0x48>;
 223         };
 224
 225         at24c04@52 {
 226                 compatible = "atmel,24c04";
 227                 reg = <0x52>;
 228                 label = "nvm";
 229         };
 230
 231         at24c04@54 {
 232                 compatible = "atmel,24c04";
 233                 reg = <0x54>;
 234                 label = "nameplate";
 235         };
 236 };
 237
 238 &uart0 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_uart0>;
 241         status = "okay";
 242 };
 243
 244 &iomuxc {
 245         pinctrl_dspi1: dspi1grp {
 246                 fsl,pins = <
 247                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 248                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 249                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 250                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 251                 >;
 252         };
 253
 254         pinctrl_esdhc0: esdhc0grp {
 255                 fsl,pins = <
 256                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 257                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 258                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 259                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 260                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 261                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 262                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 263                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 264                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 265                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 266                 >;
 267         };
 268
 269         pinctrl_esdhc1: esdhc1grp {
 270                 fsl,pins = <
 271                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 272                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 273                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 274                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 275                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 276                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 277                 >;
 278         };
 279
 280         pinctrl_fec1: fec1grp {
 281                 fsl,pins = <
 282                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 283                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30fe
 284                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 285                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 286                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 287                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 288                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 289                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 290                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 291                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 292                 >;
 293         };
 294
 295         pinctrl_i2c0: i2c0grp {
 296                 fsl,pins = <
 297                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 298                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 299                 >;
 300         };
 301
 302         pinctrl_leds_debug: pinctrl-leds-debug {
 303                 fsl,pins = <
 304                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 305                         VF610_PAD_PTE3__GPIO_108                0x31c2
 306                         VF610_PAD_PTE4__GPIO_109                0x31c2
 307                         VF610_PAD_PTE5__GPIO_110                0x31c2
 308                         VF610_PAD_PTE6__GPIO_111                0x31c2
 309                 >;
 310         };
 311
 312         pinctrl_optical: optical-grp {
 313                 fsl,pins = <
 314                 /* SFF SD input */
 315                 VF610_PAD_PTE27__GPIO_132       0x3061
 316
 317                 /* SFF Transmit disable output */
 318                 VF610_PAD_PTE13__GPIO_118       0x3043
 319                 >;
 320         };
 321
 322         pinctrl_switch: switch-grp {
 323                 fsl,pins = <
 324                         VF610_PAD_PTB28__GPIO_98                0x3061
 325                         VF610_PAD_PTE2__GPIO_107                0x1042
 326                 >;
 327         };
 328
 329         pinctrl_uart0: uart0grp {
 330                 fsl,pins = <
 331                         VF610_PAD_PTB10__UART0_TX               0x21a2
 332                         VF610_PAD_PTB11__UART0_RX               0x21a1
 333                 >;
 334         };
 335 };