arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 /dts-v1/;
  11 #include "vf610.dtsi"
  12
  13 / {
  14         model = "VF610 Tower Board";
  15         compatible = "fsl,vf610-twr", "fsl,vf610";
  16
  17         chosen {
  18                 bootargs = "console=ttyLP1,115200";
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x8000000>;
  23         };
  24
  25         clocks {
  26                 audio_ext {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <24576000>;
  30                 };
  31
  32                 enet_ext {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <50000000>;
  36                 };
  37         };
  38
  39         regulators {
  40                 compatible = "simple-bus";
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 reg_3p3v: regulator@0 {
  45                         compatible = "regulator-fixed";
  46                         reg = <0>;
  47                         regulator-name = "3P3V";
  48                         regulator-min-microvolt = <3300000>;
  49                         regulator-max-microvolt = <3300000>;
  50                         regulator-always-on;
  51                 };
  52
  53                 reg_vcc_3v3_mcu: regulator@1 {
  54                         compatible = "regulator-fixed";
  55                         reg = <1>;
  56                         regulator-name = "vcc_3v3_mcu";
  57                         regulator-min-microvolt = <3300000>;
  58                         regulator-max-microvolt = <3300000>;
  59                 };
  60         };
  61
  62         sound {
  63                 compatible = "simple-audio-card";
  64                 simple-audio-card,format = "i2s";
  65                 simple-audio-card,widgets =
  66                         "Microphone", "Microphone Jack",
  67                         "Headphone", "Headphone Jack",
  68                         "Speaker", "Speaker Ext",
  69                         "Line", "Line In Jack";
  70                 simple-audio-card,routing =
  71                         "MIC_IN", "Microphone Jack",
  72                         "Microphone Jack", "Mic Bias",
  73                         "LINE_IN", "Line In Jack",
  74                         "Headphone Jack", "HP_OUT",
  75                         "Speaker Ext", "LINE_OUT";
  76
  77                 simple-audio-card,cpu {
  78                         sound-dai = <&sai2>;
  79                         frame-master;
  80                         bitclock-master;
  81                 };
  82
  83                 simple-audio-card,codec {
  84                         sound-dai = <&codec>;
  85                         frame-master;
  86                         bitclock-master;
  87                 };
  88         };
  89 };
  90
  91 &adc0 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_adc0_ad5>;
  94         vref-supply = <&reg_vcc_3v3_mcu>;
  95         status = "okay";
  96 };
  97
  98 &dspi0 {
  99         bus-num = <0>;
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&pinctrl_dspi0>;
 102         status = "okay";
 103
 104         sflash: at26df081a@0 {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 compatible = "atmel,at26df081a";
 108                 spi-max-frequency = <16000000>;
 109                 spi-cpol;
 110                 spi-cpha;
 111                 reg = <0>;
 112         };
 113 };
 114
 115 &esdhc1 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_esdhc1>;
 118         bus-width = <4>;
 119         status = "okay";
 120 };
 121
 122 &fec0 {
 123         phy-mode = "rmii";
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_fec0>;
 126         status = "okay";
 127 };
 128
 129 &fec1 {
 130         phy-mode = "rmii";
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_fec1>;
 133         status = "okay";
 134 };
 135
 136 &i2c0 {
 137         clock-frequency = <100000>;
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_i2c0>;
 140         status = "okay";
 141
 142         codec: sgtl5000@0a {
 143                #sound-dai-cells = <0>;
 144                compatible = "fsl,sgtl5000";
 145                reg = <0x0a>;
 146                VDDA-supply = <&reg_3p3v>;
 147                VDDIO-supply = <&reg_3p3v>;
 148                clocks = <&clks VF610_CLK_SAI2>;
 149        };
 150 };
 151
 152 &iomuxc {
 153         vf610-twr {
 154                 pinctrl_adc0_ad5: adc0ad5grp {
 155                         fsl,pins = <
 156                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 157                         >;
 158                 };
 159
 160                 pinctrl_dspi0: dspi0grp {
 161                         fsl,pins = <
 162                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 163                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 164                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 165                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 166                         >;
 167                 };
 168
 169                 pinctrl_esdhc1: esdhc1grp {
 170                         fsl,pins = <
 171                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 172                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 173                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 174                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 175                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 176                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 177                                 VF610_PAD_PTA7__GPIO_134        0x219d
 178                         >;
 179                 };
 180
 181                 pinctrl_fec0: fec0grp {
 182                         fsl,pins = <
 183                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 184                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 185                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 186                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 187                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 188                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 189                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 190                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 191                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 192                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 193                         >;
 194                 };
 195
 196                 pinctrl_fec1: fec1grp {
 197                         fsl,pins = <
 198                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 199                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 200                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 201                                 VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
 202                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 203                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 204                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 205                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 206                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 207                         >;
 208                 };
 209
 210                 pinctrl_i2c0: i2c0grp {
 211                         fsl,pins = <
 212                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 213                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 214                         >;
 215                 };
 216
 217                 pinctrl_pwm0: pwm0grp {
 218                         fsl,pins = <
 219                                 VF610_PAD_PTB0__FTM0_CH0                0x1582
 220                                 VF610_PAD_PTB1__FTM0_CH1                0x1582
 221                                 VF610_PAD_PTB2__FTM0_CH2                0x1582
 222                                 VF610_PAD_PTB3__FTM0_CH3                0x1582
 223                         >;
 224                 };
 225
 226                 pinctrl_sai2: sai2grp {
 227                         fsl,pins = <
 228                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 229                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 230                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 231                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 232                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 233                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 234                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 235                         >;
 236                 };
 237
 238                 pinctrl_uart1: uart1grp {
 239                         fsl,pins = <
 240                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 241                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 242                         >;
 243                 };
 244
 245                 pinctrl_uart2: uart2grp {
 246                         fsl,pins = <
 247                                 VF610_PAD_PTB6__UART2_TX                0x21a2
 248                                 VF610_PAD_PTB7__UART2_RX                0x21a1
 249                         >;
 250                 };
 251         };
 252 };
 253
 254 &pwm0 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_pwm0>;
 257         status = "okay";
 258 };
 259
 260 &sai2 {
 261         #sound-dai-cells = <0>;
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_sai2>;
 264         status = "okay";
 265 };
 266
 267 &uart1 {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_uart1>;
 270         status = "okay";
 271 };
 272
 273 &uart2 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_uart2>;
 276         status = "okay";
 277 };
 278
 279 &usbdev0 {
 280         disable-over-current;
 281         status = "okay";
 282 };
 283
 284 &usbh1 {
 285         disable-over-current;
 286         status = "okay";
 287 };