arch/arm/boot/dts/vf610-colibri.dts

   1 /*
   2  * Copyright 2014 Toradex AG
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 /dts-v1/;
  11 #include "vf610.dtsi"
  12
  13 / {
  14         model = "Toradex Colibri VF61 COM";
  15         compatible = "toradex,vf610-colibri", "fsl,vf610";
  16
  17         chosen {
  18                 bootargs = "console=ttyLP0,115200";
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x10000000>;
  23         };
  24
  25         clocks {
  26                 enet_ext {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <50000000>;
  30                 };
  31         };
  32
  33 };
  34
  35 &esdhc1 {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_esdhc1>;
  38         bus-width = <4>;
  39         status = "okay";
  40 };
  41
  42 &fec1 {
  43         phy-mode = "rmii";
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_fec1>;
  46         status = "okay";
  47 };
  48
  49 &L2 {
  50         arm,data-latency = <2 1 2>;
  51         arm,tag-latency = <3 2 3>;
  52 };
  53
  54 &uart0 {
  55         pinctrl-names = "default";
  56         pinctrl-0 = <&pinctrl_uart0>;
  57         status = "okay";
  58 };
  59
  60 &uart1 {
  61         pinctrl-names = "default";
  62         pinctrl-0 = <&pinctrl_uart1>;
  63         status = "okay";
  64 };
  65
  66 &uart2 {
  67         pinctrl-names = "default";
  68         pinctrl-0 = <&pinctrl_uart2>;
  69         status = "okay";
  70 };
  71
  72 &iomuxc {
  73         vf610-colibri {
  74                 pinctrl_esdhc1: esdhc1grp {
  75                         fsl,fsl,pins = <
  76                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
  77                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
  78                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
  79                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
  80                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
  81                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
  82                                 VF610_PAD_PTB20__GPIO_42        0x219d
  83                         >;
  84                 };
  85
  86                 pinctrl_fec1: fec1grp {
  87                         fsl,pins = <
  88                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
  89                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
  90                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
  91                                 VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
  92                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
  93                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
  94                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
  95                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
  96                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
  97                         >;
  98                 };
  99
 100                 pinctrl_uart0: uart0grp {
 101                         fsl,pins = <
 102                                 VF610_PAD_PTB10__UART0_TX               0x21a2
 103                                 VF610_PAD_PTB11__UART0_RX               0x21a1
 104                         >;
 105                 };
 106
 107                 pinctrl_uart1: uart1grp {
 108                         fsl,pins = <
 109                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 110                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 111                         >;
 112                 };
 113
 114                 pinctrl_uart2: uart2grp {
 115                         fsl,pins = <
 116                                 VF610_PAD_PTD0__UART2_TX                0x21a2
 117                                 VF610_PAD_PTD1__UART2_RX                0x21a1
 118                                 VF610_PAD_PTD2__UART2_RTS               0x21a2
 119                                 VF610_PAD_PTD3__UART2_CTS               0x21a1
 120                         >;
 121                 };
 122         };
 123 };