arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A15x2 A7x3
   5  * Cortex-A15_A7 MPCore (V2P-CA15_A7)
   6  *
   7  * HBI-0249A
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "V2P-CA15_CA7";
  14         arm,hbi = <0x249>;
  15         arm,vexpress,site = <0xf>;
  16         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         aliases {
  24                 serial0 = &v2m_serial0;
  25                 serial1 = &v2m_serial1;
  26                 serial2 = &v2m_serial2;
  27                 serial3 = &v2m_serial3;
  28                 i2c0 = &v2m_i2c_dvi;
  29                 i2c1 = &v2m_i2c_pcie;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0>;
  40                         cci-control-port = <&cci_control1>;
  41                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
  42                         capacity-dmips-mhz = <1024>;
  43                 };
  44
  45                 cpu1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <1>;
  49                         cci-control-port = <&cci_control1>;
  50                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
  51                         capacity-dmips-mhz = <1024>;
  52                 };
  53
  54                 cpu2: cpu@2 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         reg = <0x100>;
  58                         cci-control-port = <&cci_control2>;
  59                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  60                         capacity-dmips-mhz = <516>;
  61                 };
  62
  63                 cpu3: cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a7";
  66                         reg = <0x101>;
  67                         cci-control-port = <&cci_control2>;
  68                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  69                         capacity-dmips-mhz = <516>;
  70                 };
  71
  72                 cpu4: cpu@4 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0x102>;
  76                         cci-control-port = <&cci_control2>;
  77                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  78                         capacity-dmips-mhz = <516>;
  79                 };
  80
  81                 idle-states {
  82                         CLUSTER_SLEEP_BIG: cluster-sleep-big {
  83                                 compatible = "arm,idle-state";
  84                                 local-timer-stop;
  85                                 entry-latency-us = <1000>;
  86                                 exit-latency-us = <700>;
  87                                 min-residency-us = <2000>;
  88                         };
  89
  90                         CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
  91                                 compatible = "arm,idle-state";
  92                                 local-timer-stop;
  93                                 entry-latency-us = <1000>;
  94                                 exit-latency-us = <500>;
  95                                 min-residency-us = <2500>;
  96                         };
  97                 };
  98         };
  99
 100         memory@80000000 {
 101                 device_type = "memory";
 102                 reg = <0 0x80000000 0 0x40000000>;
 103         };
 104
 105         wdt@2a490000 {
 106                 compatible = "arm,sp805", "arm,primecell";
 107                 reg = <0 0x2a490000 0 0x1000>;
 108                 interrupts = <0 98 4>;
 109                 clocks = <&oscclk6a>, <&oscclk6a>;
 110                 clock-names = "wdogclk", "apb_pclk";
 111         };
 112
 113         hdlcd@2b000000 {
 114                 compatible = "arm,hdlcd";
 115                 reg = <0 0x2b000000 0 0x1000>;
 116                 interrupts = <0 85 4>;
 117                 clocks = <&hdlcd_clk>;
 118                 clock-names = "pxlclk";
 119         };
 120
 121         memory-controller@2b0a0000 {
 122                 compatible = "arm,pl341", "arm,primecell";
 123                 reg = <0 0x2b0a0000 0 0x1000>;
 124                 clocks = <&oscclk6a>;
 125                 clock-names = "apb_pclk";
 126         };
 127
 128         gic: interrupt-controller@2c001000 {
 129                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 130                 #interrupt-cells = <3>;
 131                 #address-cells = <0>;
 132                 interrupt-controller;
 133                 reg = <0 0x2c001000 0 0x1000>,
 134                       <0 0x2c002000 0 0x2000>,
 135                       <0 0x2c004000 0 0x2000>,
 136                       <0 0x2c006000 0 0x2000>;
 137                 interrupts = <1 9 0xf04>;
 138         };
 139
 140         cci@2c090000 {
 141                 compatible = "arm,cci-400";
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 reg = <0 0x2c090000 0 0x1000>;
 145                 ranges = <0x0 0x0 0x2c090000 0x10000>;
 146
 147                 cci_control1: slave-if@4000 {
 148                         compatible = "arm,cci-400-ctrl-if";
 149                         interface-type = "ace";
 150                         reg = <0x4000 0x1000>;
 151                 };
 152
 153                 cci_control2: slave-if@5000 {
 154                         compatible = "arm,cci-400-ctrl-if";
 155                         interface-type = "ace";
 156                         reg = <0x5000 0x1000>;
 157                 };
 158
 159                 pmu@9000 {
 160                          compatible = "arm,cci-400-pmu,r0";
 161                          reg = <0x9000 0x5000>;
 162                          interrupts = <0 105 4>,
 163                                       <0 101 4>,
 164                                       <0 102 4>,
 165                                       <0 103 4>,
 166                                       <0 104 4>;
 167                 };
 168         };
 169
 170         memory-controller@7ffd0000 {
 171                 compatible = "arm,pl354", "arm,primecell";
 172                 reg = <0 0x7ffd0000 0 0x1000>;
 173                 interrupts = <0 86 4>,
 174                              <0 87 4>;
 175                 clocks = <&oscclk6a>;
 176                 clock-names = "apb_pclk";
 177         };
 178
 179         dma@7ff00000 {
 180                 compatible = "arm,pl330", "arm,primecell";
 181                 reg = <0 0x7ff00000 0 0x1000>;
 182                 interrupts = <0 92 4>,
 183                              <0 88 4>,
 184                              <0 89 4>,
 185                              <0 90 4>,
 186                              <0 91 4>;
 187                 clocks = <&oscclk6a>;
 188                 clock-names = "apb_pclk";
 189         };
 190
 191         scc@7fff0000 {
 192                 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
 193                 reg = <0 0x7fff0000 0 0x1000>;
 194                 interrupts = <0 95 4>;
 195         };
 196
 197         timer {
 198                 compatible = "arm,armv7-timer";
 199                 interrupts = <1 13 0xf08>,
 200                              <1 14 0xf08>,
 201                              <1 11 0xf08>,
 202                              <1 10 0xf08>;
 203         };
 204
 205         pmu_a15 {
 206                 compatible = "arm,cortex-a15-pmu";
 207                 interrupts = <0 68 4>,
 208                              <0 69 4>;
 209                 interrupt-affinity = <&cpu0>,
 210                                      <&cpu1>;
 211         };
 212
 213         pmu_a7 {
 214                 compatible = "arm,cortex-a7-pmu";
 215                 interrupts = <0 128 4>,
 216                              <0 129 4>,
 217                              <0 130 4>;
 218                 interrupt-affinity = <&cpu2>,
 219                                      <&cpu3>,
 220                                      <&cpu4>;
 221         };
 222
 223         oscclk6a: oscclk6a {
 224                 /* Reference 24MHz clock */
 225                 compatible = "fixed-clock";
 226                 #clock-cells = <0>;
 227                 clock-frequency = <24000000>;
 228                 clock-output-names = "oscclk6a";
 229         };
 230
 231         dcc {
 232                 compatible = "arm,vexpress,config-bus";
 233                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 234
 235                 oscclk0 {
 236                         /* A15 PLL 0 reference clock */
 237                         compatible = "arm,vexpress-osc";
 238                         arm,vexpress-sysreg,func = <1 0>;
 239                         freq-range = <17000000 50000000>;
 240                         #clock-cells = <0>;
 241                         clock-output-names = "oscclk0";
 242                 };
 243
 244                 oscclk1 {
 245                         /* A15 PLL 1 reference clock */
 246                         compatible = "arm,vexpress-osc";
 247                         arm,vexpress-sysreg,func = <1 1>;
 248                         freq-range = <17000000 50000000>;
 249                         #clock-cells = <0>;
 250                         clock-output-names = "oscclk1";
 251                 };
 252
 253                 oscclk2 {
 254                         /* A7 PLL 0 reference clock */
 255                         compatible = "arm,vexpress-osc";
 256                         arm,vexpress-sysreg,func = <1 2>;
 257                         freq-range = <17000000 50000000>;
 258                         #clock-cells = <0>;
 259                         clock-output-names = "oscclk2";
 260                 };
 261
 262                 oscclk3 {
 263                         /* A7 PLL 1 reference clock */
 264                         compatible = "arm,vexpress-osc";
 265                         arm,vexpress-sysreg,func = <1 3>;
 266                         freq-range = <17000000 50000000>;
 267                         #clock-cells = <0>;
 268                         clock-output-names = "oscclk3";
 269                 };
 270
 271                 oscclk4 {
 272                         /* External AXI master clock */
 273                         compatible = "arm,vexpress-osc";
 274                         arm,vexpress-sysreg,func = <1 4>;
 275                         freq-range = <20000000 40000000>;
 276                         #clock-cells = <0>;
 277                         clock-output-names = "oscclk4";
 278                 };
 279
 280                 hdlcd_clk: oscclk5 {
 281                         /* HDLCD PLL reference clock */
 282                         compatible = "arm,vexpress-osc";
 283                         arm,vexpress-sysreg,func = <1 5>;
 284                         freq-range = <23750000 165000000>;
 285                         #clock-cells = <0>;
 286                         clock-output-names = "oscclk5";
 287                 };
 288
 289                 smbclk: oscclk6 {
 290                         /* Static memory controller clock */
 291                         compatible = "arm,vexpress-osc";
 292                         arm,vexpress-sysreg,func = <1 6>;
 293                         freq-range = <20000000 40000000>;
 294                         #clock-cells = <0>;
 295                         clock-output-names = "oscclk6";
 296                 };
 297
 298                 oscclk7 {
 299                         /* SYS PLL reference clock */
 300                         compatible = "arm,vexpress-osc";
 301                         arm,vexpress-sysreg,func = <1 7>;
 302                         freq-range = <17000000 50000000>;
 303                         #clock-cells = <0>;
 304                         clock-output-names = "oscclk7";
 305                 };
 306
 307                 oscclk8 {
 308                         /* DDR2 PLL reference clock */
 309                         compatible = "arm,vexpress-osc";
 310                         arm,vexpress-sysreg,func = <1 8>;
 311                         freq-range = <20000000 50000000>;
 312                         #clock-cells = <0>;
 313                         clock-output-names = "oscclk8";
 314                 };
 315
 316                 volt-a15 {
 317                         /* A15 CPU core voltage */
 318                         compatible = "arm,vexpress-volt";
 319                         arm,vexpress-sysreg,func = <2 0>;
 320                         regulator-name = "A15 Vcore";
 321                         regulator-min-microvolt = <800000>;
 322                         regulator-max-microvolt = <1050000>;
 323                         regulator-always-on;
 324                         label = "A15 Vcore";
 325                 };
 326
 327                 volt-a7 {
 328                         /* A7 CPU core voltage */
 329                         compatible = "arm,vexpress-volt";
 330                         arm,vexpress-sysreg,func = <2 1>;
 331                         regulator-name = "A7 Vcore";
 332                         regulator-min-microvolt = <800000>;
 333                         regulator-max-microvolt = <1050000>;
 334                         regulator-always-on;
 335                         label = "A7 Vcore";
 336                 };
 337
 338                 amp-a15 {
 339                         /* Total current for the two A15 cores */
 340                         compatible = "arm,vexpress-amp";
 341                         arm,vexpress-sysreg,func = <3 0>;
 342                         label = "A15 Icore";
 343                 };
 344
 345                 amp-a7 {
 346                         /* Total current for the three A7 cores */
 347                         compatible = "arm,vexpress-amp";
 348                         arm,vexpress-sysreg,func = <3 1>;
 349                         label = "A7 Icore";
 350                 };
 351
 352                 temp-dcc {
 353                         /* DCC internal temperature */
 354                         compatible = "arm,vexpress-temp";
 355                         arm,vexpress-sysreg,func = <4 0>;
 356                         label = "DCC";
 357                 };
 358
 359                 power-a15 {
 360                         /* Total power for the two A15 cores */
 361                         compatible = "arm,vexpress-power";
 362                         arm,vexpress-sysreg,func = <12 0>;
 363                         label = "A15 Pcore";
 364                 };
 365
 366                 power-a7 {
 367                         /* Total power for the three A7 cores */
 368                         compatible = "arm,vexpress-power";
 369                         arm,vexpress-sysreg,func = <12 1>;
 370                         label = "A7 Pcore";
 371                 };
 372
 373                 energy-a15 {
 374                         /* Total energy for the two A15 cores */
 375                         compatible = "arm,vexpress-energy";
 376                         arm,vexpress-sysreg,func = <13 0>, <13 1>;
 377                         label = "A15 Jcore";
 378                 };
 379
 380                 energy-a7 {
 381                         /* Total energy for the three A7 cores */
 382                         compatible = "arm,vexpress-energy";
 383                         arm,vexpress-sysreg,func = <13 2>, <13 3>;
 384                         label = "A7 Jcore";
 385                 };
 386         };
 387
 388         etb@0,20010000 {
 389                 compatible = "arm,coresight-etb10", "arm,primecell";
 390                 reg = <0 0x20010000 0 0x1000>;
 391
 392                 clocks = <&oscclk6a>;
 393                 clock-names = "apb_pclk";
 394                 port {
 395                         etb_in_port: endpoint {
 396                                 slave-mode;
 397                                 remote-endpoint = <&replicator_out_port0>;
 398                         };
 399                 };
 400         };
 401
 402         tpiu@0,20030000 {
 403                 compatible = "arm,coresight-tpiu", "arm,primecell";
 404                 reg = <0 0x20030000 0 0x1000>;
 405
 406                 clocks = <&oscclk6a>;
 407                 clock-names = "apb_pclk";
 408                 port {
 409                         tpiu_in_port: endpoint {
 410                                 slave-mode;
 411                                 remote-endpoint = <&replicator_out_port1>;
 412                         };
 413                 };
 414         };
 415
 416         replicator {
 417                 /* non-configurable replicators don't show up on the
 418                  * AMBA bus.  As such no need to add "arm,primecell".
 419                  */
 420                 compatible = "arm,coresight-replicator";
 421
 422                 ports {
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425
 426                         /* replicator output ports */
 427                         port@0 {
 428                                 reg = <0>;
 429                                 replicator_out_port0: endpoint {
 430                                         remote-endpoint = <&etb_in_port>;
 431                                 };
 432                         };
 433
 434                         port@1 {
 435                                 reg = <1>;
 436                                 replicator_out_port1: endpoint {
 437                                         remote-endpoint = <&tpiu_in_port>;
 438                                 };
 439                         };
 440
 441                         /* replicator input port */
 442                         port@2 {
 443                                 reg = <0>;
 444                                 replicator_in_port0: endpoint {
 445                                         slave-mode;
 446                                         remote-endpoint = <&funnel_out_port0>;
 447                                 };
 448                         };
 449                 };
 450         };
 451
 452         funnel@0,20040000 {
 453                 compatible = "arm,coresight-funnel", "arm,primecell";
 454                 reg = <0 0x20040000 0 0x1000>;
 455
 456                 clocks = <&oscclk6a>;
 457                 clock-names = "apb_pclk";
 458                 ports {
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461
 462                         /* funnel output port */
 463                         port@0 {
 464                                 reg = <0>;
 465                                 funnel_out_port0: endpoint {
 466                                         remote-endpoint =
 467                                                 <&replicator_in_port0>;
 468                                 };
 469                         };
 470
 471                         /* funnel input ports */
 472                         port@1 {
 473                                 reg = <0>;
 474                                 funnel_in_port0: endpoint {
 475                                         slave-mode;
 476                                         remote-endpoint = <&ptm0_out_port>;
 477                                 };
 478                         };
 479
 480                         port@2 {
 481                                 reg = <1>;
 482                                 funnel_in_port1: endpoint {
 483                                         slave-mode;
 484                                         remote-endpoint = <&ptm1_out_port>;
 485                                 };
 486                         };
 487
 488                         port@3 {
 489                                 reg = <2>;
 490                                 funnel_in_port2: endpoint {
 491                                         slave-mode;
 492                                         remote-endpoint = <&etm0_out_port>;
 493                                 };
 494                         };
 495
 496                         /* Input port #3 is for ITM, not supported here */
 497
 498                         port@4 {
 499                                 reg = <4>;
 500                                 funnel_in_port4: endpoint {
 501                                         slave-mode;
 502                                         remote-endpoint = <&etm1_out_port>;
 503                                 };
 504                         };
 505
 506                         port@5 {
 507                                 reg = <5>;
 508                                 funnel_in_port5: endpoint {
 509                                         slave-mode;
 510                                         remote-endpoint = <&etm2_out_port>;
 511                                 };
 512                         };
 513                 };
 514         };
 515
 516         ptm@0,2201c000 {
 517                 compatible = "arm,coresight-etm3x", "arm,primecell";
 518                 reg = <0 0x2201c000 0 0x1000>;
 519
 520                 cpu = <&cpu0>;
 521                 clocks = <&oscclk6a>;
 522                 clock-names = "apb_pclk";
 523                 port {
 524                         ptm0_out_port: endpoint {
 525                                 remote-endpoint = <&funnel_in_port0>;
 526                         };
 527                 };
 528         };
 529
 530         ptm@0,2201d000 {
 531                 compatible = "arm,coresight-etm3x", "arm,primecell";
 532                 reg = <0 0x2201d000 0 0x1000>;
 533
 534                 cpu = <&cpu1>;
 535                 clocks = <&oscclk6a>;
 536                 clock-names = "apb_pclk";
 537                 port {
 538                         ptm1_out_port: endpoint {
 539                                 remote-endpoint = <&funnel_in_port1>;
 540                         };
 541                 };
 542         };
 543
 544         etm@0,2203c000 {
 545                 compatible = "arm,coresight-etm3x", "arm,primecell";
 546                 reg = <0 0x2203c000 0 0x1000>;
 547
 548                 cpu = <&cpu2>;
 549                 clocks = <&oscclk6a>;
 550                 clock-names = "apb_pclk";
 551                 port {
 552                         etm0_out_port: endpoint {
 553                                 remote-endpoint = <&funnel_in_port2>;
 554                         };
 555                 };
 556         };
 557
 558         etm@0,2203d000 {
 559                 compatible = "arm,coresight-etm3x", "arm,primecell";
 560                 reg = <0 0x2203d000 0 0x1000>;
 561
 562                 cpu = <&cpu3>;
 563                 clocks = <&oscclk6a>;
 564                 clock-names = "apb_pclk";
 565                 port {
 566                         etm1_out_port: endpoint {
 567                                 remote-endpoint = <&funnel_in_port4>;
 568                         };
 569                 };
 570         };
 571
 572         etm@0,2203e000 {
 573                 compatible = "arm,coresight-etm3x", "arm,primecell";
 574                 reg = <0 0x2203e000 0 0x1000>;
 575
 576                 cpu = <&cpu4>;
 577                 clocks = <&oscclk6a>;
 578                 clock-names = "apb_pclk";
 579                 port {
 580                         etm2_out_port: endpoint {
 581                                 remote-endpoint = <&funnel_in_port5>;
 582                         };
 583                 };
 584         };
 585
 586         smb@08000000 {
 587                 compatible = "simple-bus";
 588
 589                 #address-cells = <2>;
 590                 #size-cells = <1>;
 591                 ranges = <0 0 0 0x08000000 0x04000000>,
 592                          <1 0 0 0x14000000 0x04000000>,
 593                          <2 0 0 0x18000000 0x04000000>,
 594                          <3 0 0 0x1c000000 0x04000000>,
 595                          <4 0 0 0x0c000000 0x04000000>,
 596                          <5 0 0 0x10000000 0x04000000>;
 597
 598                 #interrupt-cells = <1>;
 599                 interrupt-map-mask = <0 0 63>;
 600                 interrupt-map = <0 0  0 &gic 0  0 4>,
 601                                 <0 0  1 &gic 0  1 4>,
 602                                 <0 0  2 &gic 0  2 4>,
 603                                 <0 0  3 &gic 0  3 4>,
 604                                 <0 0  4 &gic 0  4 4>,
 605                                 <0 0  5 &gic 0  5 4>,
 606                                 <0 0  6 &gic 0  6 4>,
 607                                 <0 0  7 &gic 0  7 4>,
 608                                 <0 0  8 &gic 0  8 4>,
 609                                 <0 0  9 &gic 0  9 4>,
 610                                 <0 0 10 &gic 0 10 4>,
 611                                 <0 0 11 &gic 0 11 4>,
 612                                 <0 0 12 &gic 0 12 4>,
 613                                 <0 0 13 &gic 0 13 4>,
 614                                 <0 0 14 &gic 0 14 4>,
 615                                 <0 0 15 &gic 0 15 4>,
 616                                 <0 0 16 &gic 0 16 4>,
 617                                 <0 0 17 &gic 0 17 4>,
 618                                 <0 0 18 &gic 0 18 4>,
 619                                 <0 0 19 &gic 0 19 4>,
 620                                 <0 0 20 &gic 0 20 4>,
 621                                 <0 0 21 &gic 0 21 4>,
 622                                 <0 0 22 &gic 0 22 4>,
 623                                 <0 0 23 &gic 0 23 4>,
 624                                 <0 0 24 &gic 0 24 4>,
 625                                 <0 0 25 &gic 0 25 4>,
 626                                 <0 0 26 &gic 0 26 4>,
 627                                 <0 0 27 &gic 0 27 4>,
 628                                 <0 0 28 &gic 0 28 4>,
 629                                 <0 0 29 &gic 0 29 4>,
 630                                 <0 0 30 &gic 0 30 4>,
 631                                 <0 0 31 &gic 0 31 4>,
 632                                 <0 0 32 &gic 0 32 4>,
 633                                 <0 0 33 &gic 0 33 4>,
 634                                 <0 0 34 &gic 0 34 4>,
 635                                 <0 0 35 &gic 0 35 4>,
 636                                 <0 0 36 &gic 0 36 4>,
 637                                 <0 0 37 &gic 0 37 4>,
 638                                 <0 0 38 &gic 0 38 4>,
 639                                 <0 0 39 &gic 0 39 4>,
 640                                 <0 0 40 &gic 0 40 4>,
 641                                 <0 0 41 &gic 0 41 4>,
 642                                 <0 0 42 &gic 0 42 4>;
 643
 644                 /include/ "vexpress-v2m-rs1.dtsi"
 645         };
 646
 647         site2: hsb@40000000 {
 648                 compatible = "simple-bus";
 649                 #address-cells = <1>;
 650                 #size-cells = <1>;
 651                 ranges = <0 0 0x40000000 0x3fef0000>;
 652                 #interrupt-cells = <1>;
 653                 interrupt-map-mask = <0 3>;
 654                 interrupt-map = <0 0 &gic 0 36 4>,
 655                                 <0 1 &gic 0 37 4>,
 656                                 <0 2 &gic 0 38 4>,
 657                                 <0 3 &gic 0 39 4>;
 658         };
 659 };