arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Versatile Express
   4  *
   5  * CoreTile Express A15x2 A7x3
   6  * Cortex-A15_A7 MPCore (V2P-CA15_A7)
   7  *
   8  * HBI-0249A
   9  */
  10
  11 /dts-v1/;
  12 #include "vexpress-v2m-rs1.dtsi"
  13
  14 / {
  15         model = "V2P-CA15_CA7";
  16         arm,hbi = <0x249>;
  17         arm,vexpress,site = <0xf>;
  18         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         aliases {
  26                 serial0 = &v2m_serial0;
  27                 serial1 = &v2m_serial1;
  28                 serial2 = &v2m_serial2;
  29                 serial3 = &v2m_serial3;
  30                 i2c0 = &v2m_i2c_dvi;
  31                 i2c1 = &v2m_i2c_pcie;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <0>;
  42                         cci-control-port = <&cci_control1>;
  43                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
  44                         capacity-dmips-mhz = <1024>;
  45                         dynamic-power-coefficient = <990>;
  46                 };
  47
  48                 cpu1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <1>;
  52                         cci-control-port = <&cci_control1>;
  53                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
  54                         capacity-dmips-mhz = <1024>;
  55                         dynamic-power-coefficient = <990>;
  56                 };
  57
  58                 cpu2: cpu@2 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a7";
  61                         reg = <0x100>;
  62                         cci-control-port = <&cci_control2>;
  63                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  64                         capacity-dmips-mhz = <516>;
  65                         dynamic-power-coefficient = <133>;
  66                 };
  67
  68                 cpu3: cpu@3 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a7";
  71                         reg = <0x101>;
  72                         cci-control-port = <&cci_control2>;
  73                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  74                         capacity-dmips-mhz = <516>;
  75                         dynamic-power-coefficient = <133>;
  76                 };
  77
  78                 cpu4: cpu@4 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0x102>;
  82                         cci-control-port = <&cci_control2>;
  83                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  84                         capacity-dmips-mhz = <516>;
  85                         dynamic-power-coefficient = <133>;
  86                 };
  87
  88                 idle-states {
  89                         CLUSTER_SLEEP_BIG: cluster-sleep-big {
  90                                 compatible = "arm,idle-state";
  91                                 local-timer-stop;
  92                                 entry-latency-us = <1000>;
  93                                 exit-latency-us = <700>;
  94                                 min-residency-us = <2000>;
  95                         };
  96
  97                         CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
  98                                 compatible = "arm,idle-state";
  99                                 local-timer-stop;
 100                                 entry-latency-us = <1000>;
 101                                 exit-latency-us = <500>;
 102                                 min-residency-us = <2500>;
 103                         };
 104                 };
 105         };
 106
 107         memory@80000000 {
 108                 device_type = "memory";
 109                 reg = <0 0x80000000 0 0x40000000>;
 110         };
 111
 112         reserved-memory {
 113                 #address-cells = <2>;
 114                 #size-cells = <2>;
 115                 ranges;
 116
 117                 /* Chipselect 2 is physically at 0x18000000 */
 118                 vram: vram@18000000 {
 119                         /* 8 MB of designated video RAM */
 120                         compatible = "shared-dma-pool";
 121                         reg = <0 0x18000000 0 0x00800000>;
 122                         no-map;
 123                 };
 124         };
 125
 126         wdt@2a490000 {
 127                 compatible = "arm,sp805", "arm,primecell";
 128                 reg = <0 0x2a490000 0 0x1000>;
 129                 interrupts = <0 98 4>;
 130                 clocks = <&oscclk6a>, <&oscclk6a>;
 131                 clock-names = "wdogclk", "apb_pclk";
 132         };
 133
 134         hdlcd@2b000000 {
 135                 compatible = "arm,hdlcd";
 136                 reg = <0 0x2b000000 0 0x1000>;
 137                 interrupts = <0 85 4>;
 138                 clocks = <&hdlcd_clk>;
 139                 clock-names = "pxlclk";
 140         };
 141
 142         memory-controller@2b0a0000 {
 143                 compatible = "arm,pl341", "arm,primecell";
 144                 reg = <0 0x2b0a0000 0 0x1000>;
 145                 clocks = <&oscclk6a>;
 146                 clock-names = "apb_pclk";
 147         };
 148
 149         gic: interrupt-controller@2c001000 {
 150                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 151                 #interrupt-cells = <3>;
 152                 #address-cells = <0>;
 153                 interrupt-controller;
 154                 reg = <0 0x2c001000 0 0x1000>,
 155                       <0 0x2c002000 0 0x2000>,
 156                       <0 0x2c004000 0 0x2000>,
 157                       <0 0x2c006000 0 0x2000>;
 158                 interrupts = <1 9 0xf04>;
 159         };
 160
 161         cci@2c090000 {
 162                 compatible = "arm,cci-400";
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 reg = <0 0x2c090000 0 0x1000>;
 166                 ranges = <0x0 0x0 0x2c090000 0x10000>;
 167
 168                 cci_control1: slave-if@4000 {
 169                         compatible = "arm,cci-400-ctrl-if";
 170                         interface-type = "ace";
 171                         reg = <0x4000 0x1000>;
 172                 };
 173
 174                 cci_control2: slave-if@5000 {
 175                         compatible = "arm,cci-400-ctrl-if";
 176                         interface-type = "ace";
 177                         reg = <0x5000 0x1000>;
 178                 };
 179
 180                 pmu@9000 {
 181                          compatible = "arm,cci-400-pmu,r0";
 182                          reg = <0x9000 0x5000>;
 183                          interrupts = <0 105 4>,
 184                                       <0 101 4>,
 185                                       <0 102 4>,
 186                                       <0 103 4>,
 187                                       <0 104 4>;
 188                 };
 189         };
 190
 191         memory-controller@7ffd0000 {
 192                 compatible = "arm,pl354", "arm,primecell";
 193                 reg = <0 0x7ffd0000 0 0x1000>;
 194                 interrupts = <0 86 4>,
 195                              <0 87 4>;
 196                 clocks = <&oscclk6a>;
 197                 clock-names = "apb_pclk";
 198         };
 199
 200         dma@7ff00000 {
 201                 compatible = "arm,pl330", "arm,primecell";
 202                 reg = <0 0x7ff00000 0 0x1000>;
 203                 interrupts = <0 92 4>,
 204                              <0 88 4>,
 205                              <0 89 4>,
 206                              <0 90 4>,
 207                              <0 91 4>;
 208                 clocks = <&oscclk6a>;
 209                 clock-names = "apb_pclk";
 210         };
 211
 212         scc@7fff0000 {
 213                 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
 214                 reg = <0 0x7fff0000 0 0x1000>;
 215                 interrupts = <0 95 4>;
 216         };
 217
 218         timer {
 219                 compatible = "arm,armv7-timer";
 220                 interrupts = <1 13 0xf08>,
 221                              <1 14 0xf08>,
 222                              <1 11 0xf08>,
 223                              <1 10 0xf08>;
 224         };
 225
 226         pmu-a15 {
 227                 compatible = "arm,cortex-a15-pmu";
 228                 interrupts = <0 68 4>,
 229                              <0 69 4>;
 230                 interrupt-affinity = <&cpu0>,
 231                                      <&cpu1>;
 232         };
 233
 234         pmu-a7 {
 235                 compatible = "arm,cortex-a7-pmu";
 236                 interrupts = <0 128 4>,
 237                              <0 129 4>,
 238                              <0 130 4>;
 239                 interrupt-affinity = <&cpu2>,
 240                                      <&cpu3>,
 241                                      <&cpu4>;
 242         };
 243
 244         oscclk6a: oscclk6a {
 245                 /* Reference 24MHz clock */
 246                 compatible = "fixed-clock";
 247                 #clock-cells = <0>;
 248                 clock-frequency = <24000000>;
 249                 clock-output-names = "oscclk6a";
 250         };
 251
 252         dcc {
 253                 compatible = "arm,vexpress,config-bus";
 254                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 255
 256                 oscclk0 {
 257                         /* A15 PLL 0 reference clock */
 258                         compatible = "arm,vexpress-osc";
 259                         arm,vexpress-sysreg,func = <1 0>;
 260                         freq-range = <17000000 50000000>;
 261                         #clock-cells = <0>;
 262                         clock-output-names = "oscclk0";
 263                 };
 264
 265                 oscclk1 {
 266                         /* A15 PLL 1 reference clock */
 267                         compatible = "arm,vexpress-osc";
 268                         arm,vexpress-sysreg,func = <1 1>;
 269                         freq-range = <17000000 50000000>;
 270                         #clock-cells = <0>;
 271                         clock-output-names = "oscclk1";
 272                 };
 273
 274                 oscclk2 {
 275                         /* A7 PLL 0 reference clock */
 276                         compatible = "arm,vexpress-osc";
 277                         arm,vexpress-sysreg,func = <1 2>;
 278                         freq-range = <17000000 50000000>;
 279                         #clock-cells = <0>;
 280                         clock-output-names = "oscclk2";
 281                 };
 282
 283                 oscclk3 {
 284                         /* A7 PLL 1 reference clock */
 285                         compatible = "arm,vexpress-osc";
 286                         arm,vexpress-sysreg,func = <1 3>;
 287                         freq-range = <17000000 50000000>;
 288                         #clock-cells = <0>;
 289                         clock-output-names = "oscclk3";
 290                 };
 291
 292                 oscclk4 {
 293                         /* External AXI master clock */
 294                         compatible = "arm,vexpress-osc";
 295                         arm,vexpress-sysreg,func = <1 4>;
 296                         freq-range = <20000000 40000000>;
 297                         #clock-cells = <0>;
 298                         clock-output-names = "oscclk4";
 299                 };
 300
 301                 hdlcd_clk: oscclk5 {
 302                         /* HDLCD PLL reference clock */
 303                         compatible = "arm,vexpress-osc";
 304                         arm,vexpress-sysreg,func = <1 5>;
 305                         freq-range = <23750000 165000000>;
 306                         #clock-cells = <0>;
 307                         clock-output-names = "oscclk5";
 308                 };
 309
 310                 smbclk: oscclk6 {
 311                         /* Static memory controller clock */
 312                         compatible = "arm,vexpress-osc";
 313                         arm,vexpress-sysreg,func = <1 6>;
 314                         freq-range = <20000000 40000000>;
 315                         #clock-cells = <0>;
 316                         clock-output-names = "oscclk6";
 317                 };
 318
 319                 oscclk7 {
 320                         /* SYS PLL reference clock */
 321                         compatible = "arm,vexpress-osc";
 322                         arm,vexpress-sysreg,func = <1 7>;
 323                         freq-range = <17000000 50000000>;
 324                         #clock-cells = <0>;
 325                         clock-output-names = "oscclk7";
 326                 };
 327
 328                 oscclk8 {
 329                         /* DDR2 PLL reference clock */
 330                         compatible = "arm,vexpress-osc";
 331                         arm,vexpress-sysreg,func = <1 8>;
 332                         freq-range = <20000000 50000000>;
 333                         #clock-cells = <0>;
 334                         clock-output-names = "oscclk8";
 335                 };
 336
 337                 volt-a15 {
 338                         /* A15 CPU core voltage */
 339                         compatible = "arm,vexpress-volt";
 340                         arm,vexpress-sysreg,func = <2 0>;
 341                         regulator-name = "A15 Vcore";
 342                         regulator-min-microvolt = <800000>;
 343                         regulator-max-microvolt = <1050000>;
 344                         regulator-always-on;
 345                         label = "A15 Vcore";
 346                 };
 347
 348                 volt-a7 {
 349                         /* A7 CPU core voltage */
 350                         compatible = "arm,vexpress-volt";
 351                         arm,vexpress-sysreg,func = <2 1>;
 352                         regulator-name = "A7 Vcore";
 353                         regulator-min-microvolt = <800000>;
 354                         regulator-max-microvolt = <1050000>;
 355                         regulator-always-on;
 356                         label = "A7 Vcore";
 357                 };
 358
 359                 amp-a15 {
 360                         /* Total current for the two A15 cores */
 361                         compatible = "arm,vexpress-amp";
 362                         arm,vexpress-sysreg,func = <3 0>;
 363                         label = "A15 Icore";
 364                 };
 365
 366                 amp-a7 {
 367                         /* Total current for the three A7 cores */
 368                         compatible = "arm,vexpress-amp";
 369                         arm,vexpress-sysreg,func = <3 1>;
 370                         label = "A7 Icore";
 371                 };
 372
 373                 temp-dcc {
 374                         /* DCC internal temperature */
 375                         compatible = "arm,vexpress-temp";
 376                         arm,vexpress-sysreg,func = <4 0>;
 377                         label = "DCC";
 378                 };
 379
 380                 power-a15 {
 381                         /* Total power for the two A15 cores */
 382                         compatible = "arm,vexpress-power";
 383                         arm,vexpress-sysreg,func = <12 0>;
 384                         label = "A15 Pcore";
 385                 };
 386
 387                 power-a7 {
 388                         /* Total power for the three A7 cores */
 389                         compatible = "arm,vexpress-power";
 390                         arm,vexpress-sysreg,func = <12 1>;
 391                         label = "A7 Pcore";
 392                 };
 393
 394                 energy-a15 {
 395                         /* Total energy for the two A15 cores */
 396                         compatible = "arm,vexpress-energy";
 397                         arm,vexpress-sysreg,func = <13 0>, <13 1>;
 398                         label = "A15 Jcore";
 399                 };
 400
 401                 energy-a7 {
 402                         /* Total energy for the three A7 cores */
 403                         compatible = "arm,vexpress-energy";
 404                         arm,vexpress-sysreg,func = <13 2>, <13 3>;
 405                         label = "A7 Jcore";
 406                 };
 407         };
 408
 409         etb@20010000 {
 410                 compatible = "arm,coresight-etb10", "arm,primecell";
 411                 reg = <0 0x20010000 0 0x1000>;
 412
 413                 clocks = <&oscclk6a>;
 414                 clock-names = "apb_pclk";
 415                 in-ports {
 416                         port {
 417                                 etb_in_port: endpoint {
 418                                         remote-endpoint = <&replicator_out_port0>;
 419                                 };
 420                         };
 421                 };
 422         };
 423
 424         tpiu@20030000 {
 425                 compatible = "arm,coresight-tpiu", "arm,primecell";
 426                 reg = <0 0x20030000 0 0x1000>;
 427
 428                 clocks = <&oscclk6a>;
 429                 clock-names = "apb_pclk";
 430                 in-ports {
 431                         port {
 432                                 tpiu_in_port: endpoint {
 433                                         remote-endpoint = <&replicator_out_port1>;
 434                                 };
 435                         };
 436                 };
 437         };
 438
 439         replicator {
 440                 /* non-configurable replicators don't show up on the
 441                  * AMBA bus.  As such no need to add "arm,primecell".
 442                  */
 443                 compatible = "arm,coresight-replicator";
 444
 445                 out-ports {
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448
 449                         port@0 {
 450                                 reg = <0>;
 451                                 replicator_out_port0: endpoint {
 452                                         remote-endpoint = <&etb_in_port>;
 453                                 };
 454                         };
 455
 456                         port@1 {
 457                                 reg = <1>;
 458                                 replicator_out_port1: endpoint {
 459                                         remote-endpoint = <&tpiu_in_port>;
 460                                 };
 461                         };
 462                 };
 463
 464                 in-ports {
 465                         port {
 466                                 replicator_in_port0: endpoint {
 467                                         remote-endpoint = <&funnel_out_port0>;
 468                                 };
 469                         };
 470                 };
 471         };
 472
 473         funnel@20040000 {
 474                 compatible = "arm,coresight-funnel", "arm,primecell";
 475                 reg = <0 0x20040000 0 0x1000>;
 476
 477                 clocks = <&oscclk6a>;
 478                 clock-names = "apb_pclk";
 479                 out-ports {
 480                         port {
 481                                 funnel_out_port0: endpoint {
 482                                         remote-endpoint =
 483                                                 <&replicator_in_port0>;
 484                                 };
 485                         };
 486                 };
 487
 488                 in-ports {
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491
 492                         port@0 {
 493                                 reg = <0>;
 494                                 funnel_in_port0: endpoint {
 495                                         remote-endpoint = <&ptm0_out_port>;
 496                                 };
 497                         };
 498
 499                         port@1 {
 500                                 reg = <1>;
 501                                 funnel_in_port1: endpoint {
 502                                         remote-endpoint = <&ptm1_out_port>;
 503                                 };
 504                         };
 505
 506                         port@2 {
 507                                 reg = <2>;
 508                                 funnel_in_port2: endpoint {
 509                                         remote-endpoint = <&etm0_out_port>;
 510                                 };
 511                         };
 512
 513                         /* Input port #3 is for ITM, not supported here */
 514
 515                         port@4 {
 516                                 reg = <4>;
 517                                 funnel_in_port4: endpoint {
 518                                         remote-endpoint = <&etm1_out_port>;
 519                                 };
 520                         };
 521
 522                         port@5 {
 523                                 reg = <5>;
 524                                 funnel_in_port5: endpoint {
 525                                         remote-endpoint = <&etm2_out_port>;
 526                                 };
 527                         };
 528                 };
 529         };
 530
 531         ptm@2201c000 {
 532                 compatible = "arm,coresight-etm3x", "arm,primecell";
 533                 reg = <0 0x2201c000 0 0x1000>;
 534
 535                 cpu = <&cpu0>;
 536                 clocks = <&oscclk6a>;
 537                 clock-names = "apb_pclk";
 538                 out-ports {
 539                         port {
 540                                 ptm0_out_port: endpoint {
 541                                         remote-endpoint = <&funnel_in_port0>;
 542                                 };
 543                         };
 544                 };
 545         };
 546
 547         ptm@2201d000 {
 548                 compatible = "arm,coresight-etm3x", "arm,primecell";
 549                 reg = <0 0x2201d000 0 0x1000>;
 550
 551                 cpu = <&cpu1>;
 552                 clocks = <&oscclk6a>;
 553                 clock-names = "apb_pclk";
 554                 out-ports {
 555                         port {
 556                                 ptm1_out_port: endpoint {
 557                                         remote-endpoint = <&funnel_in_port1>;
 558                                 };
 559                         };
 560                 };
 561         };
 562
 563         etm@2203c000 {
 564                 compatible = "arm,coresight-etm3x", "arm,primecell";
 565                 reg = <0 0x2203c000 0 0x1000>;
 566
 567                 cpu = <&cpu2>;
 568                 clocks = <&oscclk6a>;
 569                 clock-names = "apb_pclk";
 570                 out-ports {
 571                         port {
 572                                 etm0_out_port: endpoint {
 573                                         remote-endpoint = <&funnel_in_port2>;
 574                                 };
 575                         };
 576                 };
 577         };
 578
 579         etm@2203d000 {
 580                 compatible = "arm,coresight-etm3x", "arm,primecell";
 581                 reg = <0 0x2203d000 0 0x1000>;
 582
 583                 cpu = <&cpu3>;
 584                 clocks = <&oscclk6a>;
 585                 clock-names = "apb_pclk";
 586                 out-ports {
 587                         port {
 588                                 etm1_out_port: endpoint {
 589                                         remote-endpoint = <&funnel_in_port4>;
 590                                 };
 591                         };
 592                 };
 593         };
 594
 595         etm@2203e000 {
 596                 compatible = "arm,coresight-etm3x", "arm,primecell";
 597                 reg = <0 0x2203e000 0 0x1000>;
 598
 599                 cpu = <&cpu4>;
 600                 clocks = <&oscclk6a>;
 601                 clock-names = "apb_pclk";
 602                 out-ports {
 603                         port {
 604                                 etm2_out_port: endpoint {
 605                                         remote-endpoint = <&funnel_in_port5>;
 606                                 };
 607                         };
 608                 };
 609         };
 610
 611         smb: smb@8000000 {
 612                 compatible = "simple-bus";
 613
 614                 #address-cells = <2>;
 615                 #size-cells = <1>;
 616                 ranges = <0 0 0 0x08000000 0x04000000>,
 617                          <1 0 0 0x14000000 0x04000000>,
 618                          <2 0 0 0x18000000 0x04000000>,
 619                          <3 0 0 0x1c000000 0x04000000>,
 620                          <4 0 0 0x0c000000 0x04000000>,
 621                          <5 0 0 0x10000000 0x04000000>;
 622
 623                 #interrupt-cells = <1>;
 624                 interrupt-map-mask = <0 0 63>;
 625                 interrupt-map = <0 0  0 &gic 0  0 4>,
 626                                 <0 0  1 &gic 0  1 4>,
 627                                 <0 0  2 &gic 0  2 4>,
 628                                 <0 0  3 &gic 0  3 4>,
 629                                 <0 0  4 &gic 0  4 4>,
 630                                 <0 0  5 &gic 0  5 4>,
 631                                 <0 0  6 &gic 0  6 4>,
 632                                 <0 0  7 &gic 0  7 4>,
 633                                 <0 0  8 &gic 0  8 4>,
 634                                 <0 0  9 &gic 0  9 4>,
 635                                 <0 0 10 &gic 0 10 4>,
 636                                 <0 0 11 &gic 0 11 4>,
 637                                 <0 0 12 &gic 0 12 4>,
 638                                 <0 0 13 &gic 0 13 4>,
 639                                 <0 0 14 &gic 0 14 4>,
 640                                 <0 0 15 &gic 0 15 4>,
 641                                 <0 0 16 &gic 0 16 4>,
 642                                 <0 0 17 &gic 0 17 4>,
 643                                 <0 0 18 &gic 0 18 4>,
 644                                 <0 0 19 &gic 0 19 4>,
 645                                 <0 0 20 &gic 0 20 4>,
 646                                 <0 0 21 &gic 0 21 4>,
 647                                 <0 0 22 &gic 0 22 4>,
 648                                 <0 0 23 &gic 0 23 4>,
 649                                 <0 0 24 &gic 0 24 4>,
 650                                 <0 0 25 &gic 0 25 4>,
 651                                 <0 0 26 &gic 0 26 4>,
 652                                 <0 0 27 &gic 0 27 4>,
 653                                 <0 0 28 &gic 0 28 4>,
 654                                 <0 0 29 &gic 0 29 4>,
 655                                 <0 0 30 &gic 0 30 4>,
 656                                 <0 0 31 &gic 0 31 4>,
 657                                 <0 0 32 &gic 0 32 4>,
 658                                 <0 0 33 &gic 0 33 4>,
 659                                 <0 0 34 &gic 0 34 4>,
 660                                 <0 0 35 &gic 0 35 4>,
 661                                 <0 0 36 &gic 0 36 4>,
 662                                 <0 0 37 &gic 0 37 4>,
 663                                 <0 0 38 &gic 0 38 4>,
 664                                 <0 0 39 &gic 0 39 4>,
 665                                 <0 0 40 &gic 0 40 4>,
 666                                 <0 0 41 &gic 0 41 4>,
 667                                 <0 0 42 &gic 0 42 4>;
 668         };
 669
 670         site2: hsb@40000000 {
 671                 compatible = "simple-bus";
 672                 #address-cells = <1>;
 673                 #size-cells = <1>;
 674                 ranges = <0 0 0x40000000 0x3fef0000>;
 675                 #interrupt-cells = <1>;
 676                 interrupt-map-mask = <0 3>;
 677                 interrupt-map = <0 0 &gic 0 36 4>,
 678                                 <0 1 &gic 0 37 4>,
 679                                 <0 2 &gic 0 38 4>,
 680                                 <0 3 &gic 0 39 4>;
 681         };
 682 };