arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Versatile Express
   4  *
   5  * Motherboard Express uATX
   6  * V2M-P1
   7  *
   8  * HBI-0190D
   9  *
  10  * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
  11  * Technical Reference Manual)
  12  *
  13  * WARNING! The hardware described in this file is independent from the
  14  * original variant (vexpress-v2m.dtsi), but there is a strong
  15  * correspondence between the two configurations.
  16  *
  17  * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  18  * CHANGES TO vexpress-v2m.dtsi!
  19  */
  20
  21 / {
  22         smb@8000000 {
  23                 motherboard {
  24                         model = "V2M-P1";
  25                         arm,hbi = <0x190>;
  26                         arm,vexpress,site = <0>;
  27                         arm,v2m-memory-map = "rs1";
  28                         compatible = "arm,vexpress,v2m-p1", "simple-bus";
  29                         #address-cells = <2>; /* SMB chipselect number and offset */
  30                         #size-cells = <1>;
  31                         #interrupt-cells = <1>;
  32                         ranges;
  33
  34                         nor_flash: flash@0,00000000 {
  35                                 compatible = "arm,vexpress-flash", "cfi-flash";
  36                                 reg = <0 0x00000000 0x04000000>,
  37                                       <4 0x00000000 0x04000000>;
  38                                 bank-width = <4>;
  39                                 partitions {
  40                                         compatible = "arm,arm-firmware-suite";
  41                                 };
  42                         };
  43
  44                         psram@1,00000000 {
  45                                 compatible = "arm,vexpress-psram", "mtd-ram";
  46                                 reg = <1 0x00000000 0x02000000>;
  47                                 bank-width = <4>;
  48                         };
  49
  50                         ethernet@2,02000000 {
  51                                 compatible = "smsc,lan9118", "smsc,lan9115";
  52                                 reg = <2 0x02000000 0x10000>;
  53                                 interrupts = <15>;
  54                                 phy-mode = "mii";
  55                                 reg-io-width = <4>;
  56                                 smsc,irq-active-high;
  57                                 smsc,irq-push-pull;
  58                                 vdd33a-supply = <&v2m_fixed_3v3>;
  59                                 vddvario-supply = <&v2m_fixed_3v3>;
  60                         };
  61
  62                         usb@2,03000000 {
  63                                 compatible = "nxp,usb-isp1761";
  64                                 reg = <2 0x03000000 0x20000>;
  65                                 interrupts = <16>;
  66                                 port1-otg;
  67                         };
  68
  69                         iofpga@3,00000000 {
  70                                 compatible = "simple-bus";
  71                                 #address-cells = <1>;
  72                                 #size-cells = <1>;
  73                                 ranges = <0 3 0 0x200000>;
  74
  75                                 v2m_sysreg: sysreg@10000 {
  76                                         compatible = "arm,vexpress-sysreg";
  77                                         reg = <0x010000 0x1000>;
  78                                         #address-cells = <1>;
  79                                         #size-cells = <1>;
  80                                         ranges = <0 0x10000 0x1000>;
  81
  82                                         v2m_led_gpios: gpio@8 {
  83                                                 compatible = "arm,vexpress-sysreg,sys_led";
  84                                                 reg = <0x008 4>;
  85                                                 gpio-controller;
  86                                                 #gpio-cells = <2>;
  87                                         };
  88
  89                                         v2m_mmc_gpios: gpio@48 {
  90                                                 compatible = "arm,vexpress-sysreg,sys_mci";
  91                                                 reg = <0x048 4>;
  92                                                 gpio-controller;
  93                                                 #gpio-cells = <2>;
  94                                         };
  95
  96                                         v2m_flash_gpios: gpio@4c {
  97                                                 compatible = "arm,vexpress-sysreg,sys_flash";
  98                                                 reg = <0x04c 4>;
  99                                                 gpio-controller;
 100                                                 #gpio-cells = <2>;
 101                                         };
 102                                 };
 103
 104                                 v2m_sysctl: sysctl@20000 {
 105                                         compatible = "arm,sp810", "arm,primecell";
 106                                         reg = <0x020000 0x1000>;
 107                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
 108                                         clock-names = "refclk", "timclk", "apb_pclk";
 109                                         #clock-cells = <1>;
 110                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 111                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 112                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 113                                 };
 114
 115                                 /* PCI-E I2C bus */
 116                                 v2m_i2c_pcie: i2c@30000 {
 117                                         compatible = "arm,versatile-i2c";
 118                                         reg = <0x030000 0x1000>;
 119
 120                                         #address-cells = <1>;
 121                                         #size-cells = <0>;
 122
 123                                         pcie-switch@60 {
 124                                                 compatible = "idt,89hpes32h8";
 125                                                 reg = <0x60>;
 126                                         };
 127                                 };
 128
 129                                 aaci@40000 {
 130                                         compatible = "arm,pl041", "arm,primecell";
 131                                         reg = <0x040000 0x1000>;
 132                                         interrupts = <11>;
 133                                         clocks = <&smbclk>;
 134                                         clock-names = "apb_pclk";
 135                                 };
 136
 137                                 mmci@50000 {
 138                                         compatible = "arm,pl180", "arm,primecell";
 139                                         reg = <0x050000 0x1000>;
 140                                         interrupts = <9>, <10>;
 141                                         cd-gpios = <&v2m_mmc_gpios 0 0>;
 142                                         wp-gpios = <&v2m_mmc_gpios 1 0>;
 143                                         max-frequency = <12000000>;
 144                                         vmmc-supply = <&v2m_fixed_3v3>;
 145                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 146                                         clock-names = "mclk", "apb_pclk";
 147                                 };
 148
 149                                 kmi@60000 {
 150                                         compatible = "arm,pl050", "arm,primecell";
 151                                         reg = <0x060000 0x1000>;
 152                                         interrupts = <12>;
 153                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 154                                         clock-names = "KMIREFCLK", "apb_pclk";
 155                                 };
 156
 157                                 kmi@70000 {
 158                                         compatible = "arm,pl050", "arm,primecell";
 159                                         reg = <0x070000 0x1000>;
 160                                         interrupts = <13>;
 161                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 162                                         clock-names = "KMIREFCLK", "apb_pclk";
 163                                 };
 164
 165                                 v2m_serial0: uart@90000 {
 166                                         compatible = "arm,pl011", "arm,primecell";
 167                                         reg = <0x090000 0x1000>;
 168                                         interrupts = <5>;
 169                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 170                                         clock-names = "uartclk", "apb_pclk";
 171                                 };
 172
 173                                 v2m_serial1: uart@a0000 {
 174                                         compatible = "arm,pl011", "arm,primecell";
 175                                         reg = <0x0a0000 0x1000>;
 176                                         interrupts = <6>;
 177                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 178                                         clock-names = "uartclk", "apb_pclk";
 179                                 };
 180
 181                                 v2m_serial2: uart@b0000 {
 182                                         compatible = "arm,pl011", "arm,primecell";
 183                                         reg = <0x0b0000 0x1000>;
 184                                         interrupts = <7>;
 185                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 186                                         clock-names = "uartclk", "apb_pclk";
 187                                 };
 188
 189                                 v2m_serial3: uart@c0000 {
 190                                         compatible = "arm,pl011", "arm,primecell";
 191                                         reg = <0x0c0000 0x1000>;
 192                                         interrupts = <8>;
 193                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 194                                         clock-names = "uartclk", "apb_pclk";
 195                                 };
 196
 197                                 wdt@f0000 {
 198                                         compatible = "arm,sp805", "arm,primecell";
 199                                         reg = <0x0f0000 0x1000>;
 200                                         interrupts = <0>;
 201                                         clocks = <&v2m_refclk32khz>, <&smbclk>;
 202                                         clock-names = "wdogclk", "apb_pclk";
 203                                 };
 204
 205                                 v2m_timer01: timer@110000 {
 206                                         compatible = "arm,sp804", "arm,primecell";
 207                                         reg = <0x110000 0x1000>;
 208                                         interrupts = <2>;
 209                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
 210                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 211                                 };
 212
 213                                 v2m_timer23: timer@120000 {
 214                                         compatible = "arm,sp804", "arm,primecell";
 215                                         reg = <0x120000 0x1000>;
 216                                         interrupts = <3>;
 217                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
 218                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 219                                 };
 220
 221                                 /* DVI I2C bus */
 222                                 v2m_i2c_dvi: i2c@160000 {
 223                                         compatible = "arm,versatile-i2c";
 224                                         reg = <0x160000 0x1000>;
 225                                         #address-cells = <1>;
 226                                         #size-cells = <0>;
 227
 228                                         dvi-transmitter@39 {
 229                                                 compatible = "sil,sii9022-tpi", "sil,sii9022";
 230                                                 reg = <0x39>;
 231
 232                                                 ports {
 233                                                         #address-cells = <1>;
 234                                                         #size-cells = <0>;
 235
 236                                                         port@0 {
 237                                                                 reg = <0>;
 238                                                                 dvi_bridge_in: endpoint {
 239                                                                         remote-endpoint = <&clcd_pads>;
 240                                                                 };
 241                                                         };
 242                                                 };
 243                                         };
 244
 245                                         dvi-transmitter@60 {
 246                                                 compatible = "sil,sii9022-cpi", "sil,sii9022";
 247                                                 reg = <0x60>;
 248                                         };
 249                                 };
 250
 251                                 rtc@170000 {
 252                                         compatible = "arm,pl031", "arm,primecell";
 253                                         reg = <0x170000 0x1000>;
 254                                         interrupts = <4>;
 255                                         clocks = <&smbclk>;
 256                                         clock-names = "apb_pclk";
 257                                 };
 258
 259                                 compact-flash@1a0000 {
 260                                         compatible = "arm,vexpress-cf", "ata-generic";
 261                                         reg = <0x1a0000 0x100
 262                                                0x1a0100 0xf00>;
 263                                         reg-shift = <2>;
 264                                 };
 265
 266                                 clcd@1f0000 {
 267                                         compatible = "arm,pl111", "arm,primecell";
 268                                         reg = <0x1f0000 0x1000>;
 269                                         interrupt-names = "combined";
 270                                         interrupts = <14>;
 271                                         clocks = <&v2m_oscclk1>, <&smbclk>;
 272                                         clock-names = "clcdclk", "apb_pclk";
 273                                         /* 800x600 16bpp @36MHz works fine */
 274                                         max-memory-bandwidth = <54000000>;
 275                                         memory-region = <&vram>;
 276
 277                                         port {
 278                                                 clcd_pads: endpoint {
 279                                                         remote-endpoint = <&dvi_bridge_in>;
 280                                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 281                                                 };
 282                                         };
 283                                 };
 284                         };
 285
 286                         v2m_fixed_3v3: fixed-regulator-0 {
 287                                 compatible = "regulator-fixed";
 288                                 regulator-name = "3V3";
 289                                 regulator-min-microvolt = <3300000>;
 290                                 regulator-max-microvolt = <3300000>;
 291                                 regulator-always-on;
 292                         };
 293
 294                         v2m_clk24mhz: clk24mhz {
 295                                 compatible = "fixed-clock";
 296                                 #clock-cells = <0>;
 297                                 clock-frequency = <24000000>;
 298                                 clock-output-names = "v2m:clk24mhz";
 299                         };
 300
 301                         v2m_refclk1mhz: refclk1mhz {
 302                                 compatible = "fixed-clock";
 303                                 #clock-cells = <0>;
 304                                 clock-frequency = <1000000>;
 305                                 clock-output-names = "v2m:refclk1mhz";
 306                         };
 307
 308                         v2m_refclk32khz: refclk32khz {
 309                                 compatible = "fixed-clock";
 310                                 #clock-cells = <0>;
 311                                 clock-frequency = <32768>;
 312                                 clock-output-names = "v2m:refclk32khz";
 313                         };
 314
 315                         leds {
 316                                 compatible = "gpio-leds";
 317
 318                                 user1 {
 319                                         label = "v2m:green:user1";
 320                                         gpios = <&v2m_led_gpios 0 0>;
 321                                         linux,default-trigger = "heartbeat";
 322                                 };
 323
 324                                 user2 {
 325                                         label = "v2m:green:user2";
 326                                         gpios = <&v2m_led_gpios 1 0>;
 327                                         linux,default-trigger = "mmc0";
 328                                 };
 329
 330                                 user3 {
 331                                         label = "v2m:green:user3";
 332                                         gpios = <&v2m_led_gpios 2 0>;
 333                                         linux,default-trigger = "cpu0";
 334                                 };
 335
 336                                 user4 {
 337                                         label = "v2m:green:user4";
 338                                         gpios = <&v2m_led_gpios 3 0>;
 339                                         linux,default-trigger = "cpu1";
 340                                 };
 341
 342                                 user5 {
 343                                         label = "v2m:green:user5";
 344                                         gpios = <&v2m_led_gpios 4 0>;
 345                                         linux,default-trigger = "cpu2";
 346                                 };
 347
 348                                 user6 {
 349                                         label = "v2m:green:user6";
 350                                         gpios = <&v2m_led_gpios 5 0>;
 351                                         linux,default-trigger = "cpu3";
 352                                 };
 353
 354                                 user7 {
 355                                         label = "v2m:green:user7";
 356                                         gpios = <&v2m_led_gpios 6 0>;
 357                                         linux,default-trigger = "cpu4";
 358                                 };
 359
 360                                 user8 {
 361                                         label = "v2m:green:user8";
 362                                         gpios = <&v2m_led_gpios 7 0>;
 363                                         linux,default-trigger = "cpu5";
 364                                 };
 365                         };
 366
 367                         mcc {
 368                                 compatible = "arm,vexpress,config-bus";
 369                                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 370
 371                                 oscclk0 {
 372                                         /* MCC static memory clock */
 373                                         compatible = "arm,vexpress-osc";
 374                                         arm,vexpress-sysreg,func = <1 0>;
 375                                         freq-range = <25000000 60000000>;
 376                                         #clock-cells = <0>;
 377                                         clock-output-names = "v2m:oscclk0";
 378                                 };
 379
 380                                 v2m_oscclk1: oscclk1 {
 381                                         /* CLCD clock */
 382                                         compatible = "arm,vexpress-osc";
 383                                         arm,vexpress-sysreg,func = <1 1>;
 384                                         freq-range = <23750000 65000000>;
 385                                         #clock-cells = <0>;
 386                                         clock-output-names = "v2m:oscclk1";
 387                                 };
 388
 389                                 v2m_oscclk2: oscclk2 {
 390                                         /* IO FPGA peripheral clock */
 391                                         compatible = "arm,vexpress-osc";
 392                                         arm,vexpress-sysreg,func = <1 2>;
 393                                         freq-range = <24000000 24000000>;
 394                                         #clock-cells = <0>;
 395                                         clock-output-names = "v2m:oscclk2";
 396                                 };
 397
 398                                 volt-vio {
 399                                         /* Logic level voltage */
 400                                         compatible = "arm,vexpress-volt";
 401                                         arm,vexpress-sysreg,func = <2 0>;
 402                                         regulator-name = "VIO";
 403                                         regulator-always-on;
 404                                         label = "VIO";
 405                                 };
 406
 407                                 temp-mcc {
 408                                         /* MCC internal operating temperature */
 409                                         compatible = "arm,vexpress-temp";
 410                                         arm,vexpress-sysreg,func = <4 0>;
 411                                         label = "MCC";
 412                                 };
 413
 414                                 reset {
 415                                         compatible = "arm,vexpress-reset";
 416                                         arm,vexpress-sysreg,func = <5 0>;
 417                                 };
 418
 419                                 muxfpga {
 420                                         compatible = "arm,vexpress-muxfpga";
 421                                         arm,vexpress-sysreg,func = <7 0>;
 422                                 };
 423
 424                                 shutdown {
 425                                         compatible = "arm,vexpress-shutdown";
 426                                         arm,vexpress-sysreg,func = <8 0>;
 427                                 };
 428
 429                                 reboot {
 430                                         compatible = "arm,vexpress-reboot";
 431                                         arm,vexpress-sysreg,func = <9 0>;
 432                                 };
 433
 434                                 dvimode {
 435                                         compatible = "arm,vexpress-dvimode";
 436                                         arm,vexpress-sysreg,func = <11 0>;
 437                                 };
 438                         };
 439                 };
 440         };
 441 };