2 * Device Tree Source for UniPhier sLD8 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/gpio/uniphier-gpio.h>
13 compatible = "socionext,uniphier-sld8";
23 compatible = "arm,cortex-a9";
25 enable-method = "psci";
26 next-level-cache = <&l2>;
31 compatible = "arm,psci-0.2";
37 compatible = "fixed-clock";
39 clock-frequency = <25000000>;
42 arm_timer_clk: arm-timer {
44 compatible = "fixed-clock";
45 clock-frequency = <50000000>;
50 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
56 l2: l2-cache@500c0000 {
57 compatible = "socionext,uniphier-system-cache";
58 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
60 interrupts = <0 174 4>, <0 175 4>;
62 cache-size = <(256 * 1024)>;
64 cache-line-size = <128>;
68 serial0: serial@54006800 {
69 compatible = "socionext,uniphier-uart";
71 reg = <0x54006800 0x40>;
72 interrupts = <0 33 4>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_uart0>;
75 clocks = <&peri_clk 0>;
76 resets = <&peri_rst 0>;
79 serial1: serial@54006900 {
80 compatible = "socionext,uniphier-uart";
82 reg = <0x54006900 0x40>;
83 interrupts = <0 35 4>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart1>;
86 clocks = <&peri_clk 1>;
87 resets = <&peri_rst 1>;
90 serial2: serial@54006a00 {
91 compatible = "socionext,uniphier-uart";
93 reg = <0x54006a00 0x40>;
94 interrupts = <0 37 4>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_uart2>;
97 clocks = <&peri_clk 2>;
98 resets = <&peri_rst 2>;
101 serial3: serial@54006b00 {
102 compatible = "socionext,uniphier-uart";
104 reg = <0x54006b00 0x40>;
105 interrupts = <0 29 4>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_uart3>;
108 clocks = <&peri_clk 3>;
109 resets = <&peri_rst 3>;
112 gpio: gpio@55000000 {
113 compatible = "socionext,uniphier-gpio";
114 reg = <0x55000000 0x200>;
115 interrupt-parent = <&aidet>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
120 gpio-ranges = <&pinctrl 0 0 0>,
123 gpio-ranges-group-names = "gpio_range0",
127 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
131 compatible = "socionext,uniphier-i2c";
133 reg = <0x58400000 0x40>;
134 #address-cells = <1>;
136 interrupts = <0 41 1>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c0>;
139 clocks = <&peri_clk 4>;
140 resets = <&peri_rst 4>;
141 clock-frequency = <100000>;
145 compatible = "socionext,uniphier-i2c";
147 reg = <0x58480000 0x40>;
148 #address-cells = <1>;
150 interrupts = <0 42 1>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c1>;
153 clocks = <&peri_clk 5>;
154 resets = <&peri_rst 5>;
155 clock-frequency = <100000>;
158 /* chip-internal connection for DMD */
160 compatible = "socionext,uniphier-i2c";
161 reg = <0x58500000 0x40>;
162 #address-cells = <1>;
164 interrupts = <0 43 1>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c2>;
167 clocks = <&peri_clk 6>;
168 resets = <&peri_rst 6>;
169 clock-frequency = <400000>;
173 compatible = "socionext,uniphier-i2c";
175 reg = <0x58580000 0x40>;
176 #address-cells = <1>;
178 interrupts = <0 44 1>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_i2c3>;
181 clocks = <&peri_clk 7>;
182 resets = <&peri_rst 7>;
183 clock-frequency = <100000>;
186 system_bus: system-bus@58c00000 {
187 compatible = "socionext,uniphier-system-bus";
189 reg = <0x58c00000 0x400>;
190 #address-cells = <2>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_system_bus>;
197 compatible = "socionext,uniphier-smpctrl";
198 reg = <0x59801000 0x400>;
202 compatible = "socionext,uniphier-sld8-mioctrl",
203 "simple-mfd", "syscon";
204 reg = <0x59810000 0x800>;
207 compatible = "socionext,uniphier-sld8-mio-clock";
212 compatible = "socionext,uniphier-sld8-mio-reset";
218 compatible = "socionext,uniphier-sld8-perictrl",
219 "simple-mfd", "syscon";
220 reg = <0x59820000 0x200>;
223 compatible = "socionext,uniphier-sld8-peri-clock";
228 compatible = "socionext,uniphier-sld8-peri-reset";
234 compatible = "socionext,uniphier-ehci", "generic-ehci";
236 reg = <0x5a800100 0x100>;
237 interrupts = <0 80 4>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_usb0>;
240 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
242 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
244 has-transaction-translator;
248 compatible = "socionext,uniphier-ehci", "generic-ehci";
250 reg = <0x5a810100 0x100>;
251 interrupts = <0 81 4>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_usb1>;
254 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
256 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
258 has-transaction-translator;
262 compatible = "socionext,uniphier-ehci", "generic-ehci";
264 reg = <0x5a820100 0x100>;
265 interrupts = <0 82 4>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_usb2>;
268 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
270 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
272 has-transaction-translator;
276 compatible = "socionext,uniphier-sld8-soc-glue",
277 "simple-mfd", "syscon";
278 reg = <0x5f800000 0x2000>;
281 compatible = "socionext,uniphier-sld8-pinctrl";
286 compatible = "socionext,uniphier-sld8-soc-glue-debug",
288 #address-cells = <1>;
290 ranges = <0 0x5f900000 0x2000>;
293 compatible = "socionext,uniphier-efuse";
298 compatible = "socionext,uniphier-efuse";
304 compatible = "arm,cortex-a9-global-timer";
305 reg = <0x60000200 0x20>;
306 interrupts = <1 11 0x104>;
307 clocks = <&arm_timer_clk>;
311 compatible = "arm,cortex-a9-twd-timer";
312 reg = <0x60000600 0x20>;
313 interrupts = <1 13 0x104>;
314 clocks = <&arm_timer_clk>;
317 intc: interrupt-controller@60001000 {
318 compatible = "arm,cortex-a9-gic";
319 reg = <0x60001000 0x1000>,
321 #interrupt-cells = <3>;
322 interrupt-controller;
325 aidet: aidet@61830000 {
326 compatible = "socionext,uniphier-sld8-aidet";
327 reg = <0x61830000 0x200>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
333 compatible = "socionext,uniphier-sld8-sysctrl",
334 "simple-mfd", "syscon";
335 reg = <0x61840000 0x10000>;
338 compatible = "socionext,uniphier-sld8-clock";
343 compatible = "socionext,uniphier-sld8-reset";
348 nand: nand@68000000 {
349 compatible = "socionext,uniphier-denali-nand-v5a";
351 reg-names = "nand_data", "denali_reg";
352 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
353 interrupts = <0 65 4>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_nand2cs>;
356 clocks = <&sys_clk 2>;
357 resets = <&sys_rst 2>;
362 #include "uniphier-pinctrl.dtsi"