arch/arm/boot/dts/uniphier-sld8.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD8 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-sld8";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <25000000>;
  38                 };
  39
  40                 arm_timer_clk: arm-timer {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: l2-cache@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(256 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 serial0: serial@54006800 {
  67                         compatible = "socionext,uniphier-uart";
  68                         status = "disabled";
  69                         reg = <0x54006800 0x40>;
  70                         interrupts = <0 33 4>;
  71                         pinctrl-names = "default";
  72                         pinctrl-0 = <&pinctrl_uart0>;
  73                         clocks = <&peri_clk 0>;
  74                         resets = <&peri_rst 0>;
  75                 };
  76
  77                 serial1: serial@54006900 {
  78                         compatible = "socionext,uniphier-uart";
  79                         status = "disabled";
  80                         reg = <0x54006900 0x40>;
  81                         interrupts = <0 35 4>;
  82                         pinctrl-names = "default";
  83                         pinctrl-0 = <&pinctrl_uart1>;
  84                         clocks = <&peri_clk 1>;
  85                         resets = <&peri_rst 1>;
  86                 };
  87
  88                 serial2: serial@54006a00 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006a00 0x40>;
  92                         interrupts = <0 37 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart2>;
  95                         clocks = <&peri_clk 2>;
  96                         resets = <&peri_rst 2>;
  97                 };
  98
  99                 serial3: serial@54006b00 {
 100                         compatible = "socionext,uniphier-uart";
 101                         status = "disabled";
 102                         reg = <0x54006b00 0x40>;
 103                         interrupts = <0 29 4>;
 104                         pinctrl-names = "default";
 105                         pinctrl-0 = <&pinctrl_uart3>;
 106                         clocks = <&peri_clk 3>;
 107                         resets = <&peri_rst 3>;
 108                 };
 109
 110                 gpio: gpio@55000000 {
 111                         compatible = "socionext,uniphier-gpio";
 112                         reg = <0x55000000 0x200>;
 113                         interrupt-parent = <&aidet>;
 114                         interrupt-controller;
 115                         #interrupt-cells = <2>;
 116                         gpio-controller;
 117                         #gpio-cells = <2>;
 118                         gpio-ranges = <&pinctrl 0 0 0>,
 119                                       <&pinctrl 104 0 0>,
 120                                       <&pinctrl 112 0 0>;
 121                         gpio-ranges-group-names = "gpio_range0",
 122                                                   "gpio_range1",
 123                                                   "gpio_range2";
 124                         ngpios = <136>;
 125                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 126                 };
 127
 128                 i2c0: i2c@58400000 {
 129                         compatible = "socionext,uniphier-i2c";
 130                         status = "disabled";
 131                         reg = <0x58400000 0x40>;
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                         interrupts = <0 41 1>;
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_i2c0>;
 137                         clocks = <&peri_clk 4>;
 138                         resets = <&peri_rst 4>;
 139                         clock-frequency = <100000>;
 140                 };
 141
 142                 i2c1: i2c@58480000 {
 143                         compatible = "socionext,uniphier-i2c";
 144                         status = "disabled";
 145                         reg = <0x58480000 0x40>;
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         interrupts = <0 42 1>;
 149                         pinctrl-names = "default";
 150                         pinctrl-0 = <&pinctrl_i2c1>;
 151                         clocks = <&peri_clk 5>;
 152                         resets = <&peri_rst 5>;
 153                         clock-frequency = <100000>;
 154                 };
 155
 156                 /* chip-internal connection for DMD */
 157                 i2c2: i2c@58500000 {
 158                         compatible = "socionext,uniphier-i2c";
 159                         reg = <0x58500000 0x40>;
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         interrupts = <0 43 1>;
 163                         pinctrl-names = "default";
 164                         pinctrl-0 = <&pinctrl_i2c2>;
 165                         clocks = <&peri_clk 6>;
 166                         resets = <&peri_rst 6>;
 167                         clock-frequency = <400000>;
 168                 };
 169
 170                 i2c3: i2c@58580000 {
 171                         compatible = "socionext,uniphier-i2c";
 172                         status = "disabled";
 173                         reg = <0x58580000 0x40>;
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         interrupts = <0 44 1>;
 177                         pinctrl-names = "default";
 178                         pinctrl-0 = <&pinctrl_i2c3>;
 179                         clocks = <&peri_clk 7>;
 180                         resets = <&peri_rst 7>;
 181                         clock-frequency = <100000>;
 182                 };
 183
 184                 system_bus: system-bus@58c00000 {
 185                         compatible = "socionext,uniphier-system-bus";
 186                         status = "disabled";
 187                         reg = <0x58c00000 0x400>;
 188                         #address-cells = <2>;
 189                         #size-cells = <1>;
 190                         pinctrl-names = "default";
 191                         pinctrl-0 = <&pinctrl_system_bus>;
 192                 };
 193
 194                 smpctrl@59801000 {
 195                         compatible = "socionext,uniphier-smpctrl";
 196                         reg = <0x59801000 0x400>;
 197                 };
 198
 199                 mioctrl@59810000 {
 200                         compatible = "socionext,uniphier-sld8-mioctrl",
 201                                      "simple-mfd", "syscon";
 202                         reg = <0x59810000 0x800>;
 203
 204                         mio_clk: clock {
 205                                 compatible = "socionext,uniphier-sld8-mio-clock";
 206                                 #clock-cells = <1>;
 207                         };
 208
 209                         mio_rst: reset {
 210                                 compatible = "socionext,uniphier-sld8-mio-reset";
 211                                 #reset-cells = <1>;
 212                         };
 213                 };
 214
 215                 perictrl@59820000 {
 216                         compatible = "socionext,uniphier-sld8-perictrl",
 217                                      "simple-mfd", "syscon";
 218                         reg = <0x59820000 0x200>;
 219
 220                         peri_clk: clock {
 221                                 compatible = "socionext,uniphier-sld8-peri-clock";
 222                                 #clock-cells = <1>;
 223                         };
 224
 225                         peri_rst: reset {
 226                                 compatible = "socionext,uniphier-sld8-peri-reset";
 227                                 #reset-cells = <1>;
 228                         };
 229                 };
 230
 231                 usb0: usb@5a800100 {
 232                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 233                         status = "disabled";
 234                         reg = <0x5a800100 0x100>;
 235                         interrupts = <0 80 4>;
 236                         pinctrl-names = "default";
 237                         pinctrl-0 = <&pinctrl_usb0>;
 238                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 239                                  <&mio_clk 12>;
 240                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 241                                  <&mio_rst 12>;
 242                 };
 243
 244                 usb1: usb@5a810100 {
 245                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 246                         status = "disabled";
 247                         reg = <0x5a810100 0x100>;
 248                         interrupts = <0 81 4>;
 249                         pinctrl-names = "default";
 250                         pinctrl-0 = <&pinctrl_usb1>;
 251                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 252                                  <&mio_clk 13>;
 253                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 254                                  <&mio_rst 13>;
 255                 };
 256
 257                 usb2: usb@5a820100 {
 258                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 259                         status = "disabled";
 260                         reg = <0x5a820100 0x100>;
 261                         interrupts = <0 82 4>;
 262                         pinctrl-names = "default";
 263                         pinctrl-0 = <&pinctrl_usb2>;
 264                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 265                                  <&mio_clk 14>;
 266                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 267                                  <&mio_rst 14>;
 268                 };
 269
 270                 soc-glue@5f800000 {
 271                         compatible = "socionext,uniphier-sld8-soc-glue",
 272                                      "simple-mfd", "syscon";
 273                         reg = <0x5f800000 0x2000>;
 274
 275                         pinctrl: pinctrl {
 276                                 compatible = "socionext,uniphier-sld8-pinctrl";
 277                         };
 278                 };
 279
 280                 timer@60000200 {
 281                         compatible = "arm,cortex-a9-global-timer";
 282                         reg = <0x60000200 0x20>;
 283                         interrupts = <1 11 0x104>;
 284                         clocks = <&arm_timer_clk>;
 285                 };
 286
 287                 timer@60000600 {
 288                         compatible = "arm,cortex-a9-twd-timer";
 289                         reg = <0x60000600 0x20>;
 290                         interrupts = <1 13 0x104>;
 291                         clocks = <&arm_timer_clk>;
 292                 };
 293
 294                 intc: interrupt-controller@60001000 {
 295                         compatible = "arm,cortex-a9-gic";
 296                         reg = <0x60001000 0x1000>,
 297                               <0x60000100 0x100>;
 298                         #interrupt-cells = <3>;
 299                         interrupt-controller;
 300                 };
 301
 302                 aidet: aidet@61830000 {
 303                         compatible = "socionext,uniphier-sld8-aidet";
 304                         reg = <0x61830000 0x200>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 sysctrl@61840000 {
 310                         compatible = "socionext,uniphier-sld8-sysctrl",
 311                                      "simple-mfd", "syscon";
 312                         reg = <0x61840000 0x10000>;
 313
 314                         sys_clk: clock {
 315                                 compatible = "socionext,uniphier-sld8-clock";
 316                                 #clock-cells = <1>;
 317                         };
 318
 319                         sys_rst: reset {
 320                                 compatible = "socionext,uniphier-sld8-reset";
 321                                 #reset-cells = <1>;
 322                         };
 323                 };
 324
 325                 nand: nand@68000000 {
 326                         compatible = "socionext,uniphier-denali-nand-v5a";
 327                         status = "disabled";
 328                         reg-names = "nand_data", "denali_reg";
 329                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 330                         interrupts = <0 65 4>;
 331                         pinctrl-names = "default";
 332                         pinctrl-0 = <&pinctrl_nand2cs>;
 333                         clocks = <&sys_clk 2>;
 334                         resets = <&sys_rst 2>;
 335                 };
 336         };
 337 };
 338
 339 #include "uniphier-pinctrl.dtsi"