arch/arm/boot/dts/uniphier-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD3 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-sld3";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         psci {
  37                 compatible = "arm,psci-0.2";
  38                 method = "smc";
  39         };
  40
  41         clocks {
  42                 refclk: ref {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <24576000>;
  46                 };
  47
  48                 arm_timer_clk: arm_timer_clk {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <50000000>;
  52                 };
  53         };
  54
  55         soc {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60                 interrupt-parent = <&intc>;
  61
  62                 timer@20000200 {
  63                         compatible = "arm,cortex-a9-global-timer";
  64                         reg = <0x20000200 0x20>;
  65                         interrupts = <1 11 0x304>;
  66                         clocks = <&arm_timer_clk>;
  67                 };
  68
  69                 timer@20000600 {
  70                         compatible = "arm,cortex-a9-twd-timer";
  71                         reg = <0x20000600 0x20>;
  72                         interrupts = <1 13 0x304>;
  73                         clocks = <&arm_timer_clk>;
  74                 };
  75
  76                 intc: interrupt-controller@20001000 {
  77                         compatible = "arm,cortex-a9-gic";
  78                         #interrupt-cells = <3>;
  79                         interrupt-controller;
  80                         reg = <0x20001000 0x1000>,
  81                               <0x20000100 0x100>;
  82                 };
  83
  84                 l2: l2-cache@500c0000 {
  85                         compatible = "socionext,uniphier-system-cache";
  86                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  87                               <0x506c0000 0x400>;
  88                         interrupts = <0 174 4>, <0 175 4>;
  89                         cache-unified;
  90                         cache-size = <(512 * 1024)>;
  91                         cache-sets = <256>;
  92                         cache-line-size = <128>;
  93                         cache-level = <2>;
  94                 };
  95
  96                 serial0: serial@54006800 {
  97                         compatible = "socionext,uniphier-uart";
  98                         status = "disabled";
  99                         reg = <0x54006800 0x40>;
 100                         interrupts = <0 33 4>;
 101                         clocks = <&sys_clk 0>;
 102                 };
 103
 104                 serial1: serial@54006900 {
 105                         compatible = "socionext,uniphier-uart";
 106                         status = "disabled";
 107                         reg = <0x54006900 0x40>;
 108                         interrupts = <0 35 4>;
 109                         clocks = <&sys_clk 0>;
 110                 };
 111
 112                 serial2: serial@54006a00 {
 113                         compatible = "socionext,uniphier-uart";
 114                         status = "disabled";
 115                         reg = <0x54006a00 0x40>;
 116                         interrupts = <0 37 4>;
 117                         clocks = <&sys_clk 0>;
 118                 };
 119
 120                 i2c0: i2c@58400000 {
 121                         compatible = "socionext,uniphier-i2c";
 122                         status = "disabled";
 123                         reg = <0x58400000 0x40>;
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         interrupts = <0 41 1>;
 127                         clocks = <&sys_clk 1>;
 128                         clock-frequency = <100000>;
 129                 };
 130
 131                 i2c1: i2c@58480000 {
 132                         compatible = "socionext,uniphier-i2c";
 133                         status = "disabled";
 134                         reg = <0x58480000 0x40>;
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         interrupts = <0 42 1>;
 138                         clocks = <&sys_clk 1>;
 139                         clock-frequency = <100000>;
 140                 };
 141
 142                 i2c2: i2c@58500000 {
 143                         compatible = "socionext,uniphier-i2c";
 144                         status = "disabled";
 145                         reg = <0x58500000 0x40>;
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         interrupts = <0 43 1>;
 149                         clocks = <&sys_clk 1>;
 150                         clock-frequency = <100000>;
 151                 };
 152
 153                 i2c3: i2c@58580000 {
 154                         compatible = "socionext,uniphier-i2c";
 155                         status = "disabled";
 156                         reg = <0x58580000 0x40>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         interrupts = <0 44 1>;
 160                         clocks = <&sys_clk 1>;
 161                         clock-frequency = <100000>;
 162                 };
 163
 164                 /* chip-internal connection for DMD */
 165                 i2c4: i2c@58600000 {
 166                         compatible = "socionext,uniphier-i2c";
 167                         reg = <0x58600000 0x40>;
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         interrupts = <0 45 1>;
 171                         clocks = <&sys_clk 1>;
 172                         clock-frequency = <400000>;
 173                 };
 174
 175                 system_bus: system-bus@58c00000 {
 176                         compatible = "socionext,uniphier-system-bus";
 177                         status = "disabled";
 178                         reg = <0x58c00000 0x400>;
 179                         #address-cells = <2>;
 180                         #size-cells = <1>;
 181                 };
 182
 183                 smpctrl@59801000 {
 184                         compatible = "socionext,uniphier-smpctrl";
 185                         reg = <0x59801000 0x400>;
 186                 };
 187
 188                 mioctrl@59810000 {
 189                         compatible = "socionext,uniphier-sld3-mioctrl",
 190                                      "simple-mfd", "syscon";
 191                         reg = <0x59810000 0x800>;
 192
 193                         mio_clk: clock {
 194                                 compatible = "socionext,uniphier-sld3-mio-clock";
 195                                 #clock-cells = <1>;
 196                         };
 197
 198                         mio_rst: reset {
 199                                 compatible = "socionext,uniphier-sld3-mio-reset";
 200                                 #reset-cells = <1>;
 201                         };
 202                 };
 203
 204                 usb0: usb@5a800100 {
 205                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 206                         status = "disabled";
 207                         reg = <0x5a800100 0x100>;
 208                         interrupts = <0 80 4>;
 209                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 210                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 211                                  <&mio_rst 12>;
 212                 };
 213
 214                 usb1: usb@5a810100 {
 215                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 216                         status = "disabled";
 217                         reg = <0x5a810100 0x100>;
 218                         interrupts = <0 81 4>;
 219                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 220                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 221                                  <&mio_rst 13>;
 222                 };
 223
 224                 usb2: usb@5a820100 {
 225                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 226                         status = "disabled";
 227                         reg = <0x5a820100 0x100>;
 228                         interrupts = <0 82 4>;
 229                         clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
 230                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 231                                  <&mio_rst 14>;
 232                 };
 233
 234                 usb3: usb@5a830100 {
 235                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 236                         status = "disabled";
 237                         reg = <0x5a830100 0x100>;
 238                         interrupts = <0 83 4>;
 239                         clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
 240                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
 241                                  <&mio_rst 15>;
 242                 };
 243
 244                 sysctrl@f1840000 {
 245                         compatible = "socionext,uniphier-sld3-sysctrl",
 246                                      "simple-mfd", "syscon";
 247                         reg = <0xf1840000 0x10000>;
 248
 249                         sys_clk: clock {
 250                                 compatible = "socionext,uniphier-sld3-clock";
 251                                 #clock-cells = <1>;
 252                         };
 253
 254                         sys_rst: reset {
 255                                 compatible = "socionext,uniphier-sld3-reset";
 256                                 #reset-cells = <1>;
 257                         };
 258                 };
 259         };
 260 };