arch/arm/boot/dts/uniphier-pxs2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs2 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 #include <dt-bindings/gpio/uniphier-gpio.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "socionext,uniphier-pxs2";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a9";
  25                         reg = <0>;
  26                         clocks = <&sys_clk 32>;
  27                         enable-method = "psci";
  28                         next-level-cache = <&l2>;
  29                         operating-points-v2 = <&cpu_opp>;
  30                         #cooling-cells = <2>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <1>;
  37                         clocks = <&sys_clk 32>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                         operating-points-v2 = <&cpu_opp>;
  41                 };
  42
  43                 cpu2: cpu@2 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a9";
  46                         reg = <2>;
  47                         clocks = <&sys_clk 32>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&l2>;
  50                         operating-points-v2 = <&cpu_opp>;
  51                 };
  52
  53                 cpu3: cpu@3 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a9";
  56                         reg = <3>;
  57                         clocks = <&sys_clk 32>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&l2>;
  60                         operating-points-v2 = <&cpu_opp>;
  61                 };
  62         };
  63
  64         cpu_opp: opp-table {
  65                 compatible = "operating-points-v2";
  66                 opp-shared;
  67
  68                 opp-100000000 {
  69                         opp-hz = /bits/ 64 <100000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp-150000000 {
  73                         opp-hz = /bits/ 64 <150000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp-200000000 {
  77                         opp-hz = /bits/ 64 <200000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp-300000000 {
  81                         opp-hz = /bits/ 64 <300000000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-400000000 {
  85                         opp-hz = /bits/ 64 <400000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-600000000 {
  89                         opp-hz = /bits/ 64 <600000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-1200000000 {
  97                         opp-hz = /bits/ 64 <1200000000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100         };
 101
 102         psci {
 103                 compatible = "arm,psci-0.2";
 104                 method = "smc";
 105         };
 106
 107         clocks {
 108                 refclk: ref {
 109                         compatible = "fixed-clock";
 110                         #clock-cells = <0>;
 111                         clock-frequency = <25000000>;
 112                 };
 113
 114                 arm_timer_clk: arm-timer {
 115                         #clock-cells = <0>;
 116                         compatible = "fixed-clock";
 117                         clock-frequency = <50000000>;
 118                 };
 119         };
 120
 121         thermal-zones {
 122                 cpu-thermal {
 123                         polling-delay-passive = <250>;  /* 250ms */
 124                         polling-delay = <1000>;         /* 1000ms */
 125                         thermal-sensors = <&pvtctl>;
 126
 127                         trips {
 128                                 cpu_crit: cpu-crit {
 129                                         temperature = <95000>;  /* 95C */
 130                                         hysteresis = <2000>;
 131                                         type = "critical";
 132                                 };
 133                                 cpu_alert: cpu-alert {
 134                                         temperature = <85000>;  /* 85C */
 135                                         hysteresis = <2000>;
 136                                         type = "passive";
 137                                 };
 138                         };
 139
 140                         cooling-maps {
 141                                 map {
 142                                         trip = <&cpu_alert>;
 143                                         cooling-device = <&cpu0
 144                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 145                                 };
 146                         };
 147                 };
 148         };
 149
 150         soc {
 151                 compatible = "simple-bus";
 152                 #address-cells = <1>;
 153                 #size-cells = <1>;
 154                 ranges;
 155                 interrupt-parent = <&intc>;
 156
 157                 l2: l2-cache@500c0000 {
 158                         compatible = "socionext,uniphier-system-cache";
 159                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 160                               <0x506c0000 0x400>;
 161                         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 162                         cache-unified;
 163                         cache-size = <(1280 * 1024)>;
 164                         cache-sets = <512>;
 165                         cache-line-size = <128>;
 166                         cache-level = <2>;
 167                 };
 168
 169                 serial0: serial@54006800 {
 170                         compatible = "socionext,uniphier-uart";
 171                         status = "disabled";
 172                         reg = <0x54006800 0x40>;
 173                         interrupts = <0 33 4>;
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&pinctrl_uart0>;
 176                         clocks = <&peri_clk 0>;
 177                         resets = <&peri_rst 0>;
 178                 };
 179
 180                 serial1: serial@54006900 {
 181                         compatible = "socionext,uniphier-uart";
 182                         status = "disabled";
 183                         reg = <0x54006900 0x40>;
 184                         interrupts = <0 35 4>;
 185                         pinctrl-names = "default";
 186                         pinctrl-0 = <&pinctrl_uart1>;
 187                         clocks = <&peri_clk 1>;
 188                         resets = <&peri_rst 1>;
 189                 };
 190
 191                 serial2: serial@54006a00 {
 192                         compatible = "socionext,uniphier-uart";
 193                         status = "disabled";
 194                         reg = <0x54006a00 0x40>;
 195                         interrupts = <0 37 4>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_uart2>;
 198                         clocks = <&peri_clk 2>;
 199                         resets = <&peri_rst 2>;
 200                 };
 201
 202                 serial3: serial@54006b00 {
 203                         compatible = "socionext,uniphier-uart";
 204                         status = "disabled";
 205                         reg = <0x54006b00 0x40>;
 206                         interrupts = <0 177 4>;
 207                         pinctrl-names = "default";
 208                         pinctrl-0 = <&pinctrl_uart3>;
 209                         clocks = <&peri_clk 3>;
 210                         resets = <&peri_rst 3>;
 211                 };
 212
 213                 gpio: gpio@55000000 {
 214                         compatible = "socionext,uniphier-gpio";
 215                         reg = <0x55000000 0x200>;
 216                         interrupt-parent = <&aidet>;
 217                         interrupt-controller;
 218                         #interrupt-cells = <2>;
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                         gpio-ranges = <&pinctrl 0 0 0>,
 222                                       <&pinctrl 96 0 0>;
 223                         gpio-ranges-group-names = "gpio_range0",
 224                                                   "gpio_range1";
 225                         ngpios = <232>;
 226                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 227                                                      <21 217 3>;
 228                 };
 229
 230                 i2c0: i2c@58780000 {
 231                         compatible = "socionext,uniphier-fi2c";
 232                         status = "disabled";
 233                         reg = <0x58780000 0x80>;
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         interrupts = <0 41 4>;
 237                         pinctrl-names = "default";
 238                         pinctrl-0 = <&pinctrl_i2c0>;
 239                         clocks = <&peri_clk 4>;
 240                         resets = <&peri_rst 4>;
 241                         clock-frequency = <100000>;
 242                 };
 243
 244                 i2c1: i2c@58781000 {
 245                         compatible = "socionext,uniphier-fi2c";
 246                         status = "disabled";
 247                         reg = <0x58781000 0x80>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         interrupts = <0 42 4>;
 251                         pinctrl-names = "default";
 252                         pinctrl-0 = <&pinctrl_i2c1>;
 253                         clocks = <&peri_clk 5>;
 254                         resets = <&peri_rst 5>;
 255                         clock-frequency = <100000>;
 256                 };
 257
 258                 i2c2: i2c@58782000 {
 259                         compatible = "socionext,uniphier-fi2c";
 260                         status = "disabled";
 261                         reg = <0x58782000 0x80>;
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         interrupts = <0 43 4>;
 265                         pinctrl-names = "default";
 266                         pinctrl-0 = <&pinctrl_i2c2>;
 267                         clocks = <&peri_clk 6>;
 268                         resets = <&peri_rst 6>;
 269                         clock-frequency = <100000>;
 270                 };
 271
 272                 i2c3: i2c@58783000 {
 273                         compatible = "socionext,uniphier-fi2c";
 274                         status = "disabled";
 275                         reg = <0x58783000 0x80>;
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         interrupts = <0 44 4>;
 279                         pinctrl-names = "default";
 280                         pinctrl-0 = <&pinctrl_i2c3>;
 281                         clocks = <&peri_clk 7>;
 282                         resets = <&peri_rst 7>;
 283                         clock-frequency = <100000>;
 284                 };
 285
 286                 /* chip-internal connection for DMD */
 287                 i2c4: i2c@58784000 {
 288                         compatible = "socionext,uniphier-fi2c";
 289                         reg = <0x58784000 0x80>;
 290                         #address-cells = <1>;
 291                         #size-cells = <0>;
 292                         interrupts = <0 45 4>;
 293                         clocks = <&peri_clk 8>;
 294                         resets = <&peri_rst 8>;
 295                         clock-frequency = <400000>;
 296                 };
 297
 298                 /* chip-internal connection for STM */
 299                 i2c5: i2c@58785000 {
 300                         compatible = "socionext,uniphier-fi2c";
 301                         reg = <0x58785000 0x80>;
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                         interrupts = <0 25 4>;
 305                         clocks = <&peri_clk 9>;
 306                         resets = <&peri_rst 9>;
 307                         clock-frequency = <400000>;
 308                 };
 309
 310                 /* chip-internal connection for HDMI */
 311                 i2c6: i2c@58786000 {
 312                         compatible = "socionext,uniphier-fi2c";
 313                         reg = <0x58786000 0x80>;
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                         interrupts = <0 26 4>;
 317                         clocks = <&peri_clk 10>;
 318                         resets = <&peri_rst 10>;
 319                         clock-frequency = <400000>;
 320                 };
 321
 322                 system_bus: system-bus@58c00000 {
 323                         compatible = "socionext,uniphier-system-bus";
 324                         status = "disabled";
 325                         reg = <0x58c00000 0x400>;
 326                         #address-cells = <2>;
 327                         #size-cells = <1>;
 328                         pinctrl-names = "default";
 329                         pinctrl-0 = <&pinctrl_system_bus>;
 330                 };
 331
 332                 smpctrl@59801000 {
 333                         compatible = "socionext,uniphier-smpctrl";
 334                         reg = <0x59801000 0x400>;
 335                 };
 336
 337                 sdctrl@59810000 {
 338                         compatible = "socionext,uniphier-pxs2-sdctrl",
 339                                      "simple-mfd", "syscon";
 340                         reg = <0x59810000 0x400>;
 341
 342                         sd_clk: clock {
 343                                 compatible = "socionext,uniphier-pxs2-sd-clock";
 344                                 #clock-cells = <1>;
 345                         };
 346
 347                         sd_rst: reset {
 348                                 compatible = "socionext,uniphier-pxs2-sd-reset";
 349                                 #reset-cells = <1>;
 350                         };
 351                 };
 352
 353                 perictrl@59820000 {
 354                         compatible = "socionext,uniphier-pxs2-perictrl",
 355                                      "simple-mfd", "syscon";
 356                         reg = <0x59820000 0x200>;
 357
 358                         peri_clk: clock {
 359                                 compatible = "socionext,uniphier-pxs2-peri-clock";
 360                                 #clock-cells = <1>;
 361                         };
 362
 363                         peri_rst: reset {
 364                                 compatible = "socionext,uniphier-pxs2-peri-reset";
 365                                 #reset-cells = <1>;
 366                         };
 367                 };
 368
 369                 soc-glue@5f800000 {
 370                         compatible = "socionext,uniphier-pxs2-soc-glue",
 371                                      "simple-mfd", "syscon";
 372                         reg = <0x5f800000 0x2000>;
 373
 374                         pinctrl: pinctrl {
 375                                 compatible = "socionext,uniphier-pxs2-pinctrl";
 376                         };
 377                 };
 378
 379                 soc-glue@5f900000 {
 380                         compatible = "socionext,uniphier-pxs2-soc-glue-debug",
 381                                      "simple-mfd";
 382                         #address-cells = <1>;
 383                         #size-cells = <1>;
 384                         ranges = <0 0x5f900000 0x2000>;
 385
 386                         efuse@100 {
 387                                 compatible = "socionext,uniphier-efuse";
 388                                 reg = <0x100 0x28>;
 389                         };
 390
 391                         efuse@200 {
 392                                 compatible = "socionext,uniphier-efuse";
 393                                 reg = <0x200 0x58>;
 394                         };
 395                 };
 396
 397                 aidet: aidet@5fc20000 {
 398                         compatible = "socionext,uniphier-pxs2-aidet";
 399                         reg = <0x5fc20000 0x200>;
 400                         interrupt-controller;
 401                         #interrupt-cells = <2>;
 402                 };
 403
 404                 timer@60000200 {
 405                         compatible = "arm,cortex-a9-global-timer";
 406                         reg = <0x60000200 0x20>;
 407                         interrupts = <1 11 0xf04>;
 408                         clocks = <&arm_timer_clk>;
 409                 };
 410
 411                 timer@60000600 {
 412                         compatible = "arm,cortex-a9-twd-timer";
 413                         reg = <0x60000600 0x20>;
 414                         interrupts = <1 13 0xf04>;
 415                         clocks = <&arm_timer_clk>;
 416                 };
 417
 418                 intc: interrupt-controller@60001000 {
 419                         compatible = "arm,cortex-a9-gic";
 420                         reg = <0x60001000 0x1000>,
 421                               <0x60000100 0x100>;
 422                         #interrupt-cells = <3>;
 423                         interrupt-controller;
 424                 };
 425
 426                 sysctrl@61840000 {
 427                         compatible = "socionext,uniphier-pxs2-sysctrl",
 428                                      "simple-mfd", "syscon";
 429                         reg = <0x61840000 0x10000>;
 430
 431                         sys_clk: clock {
 432                                 compatible = "socionext,uniphier-pxs2-clock";
 433                                 #clock-cells = <1>;
 434                         };
 435
 436                         sys_rst: reset {
 437                                 compatible = "socionext,uniphier-pxs2-reset";
 438                                 #reset-cells = <1>;
 439                         };
 440
 441                         pvtctl: pvtctl {
 442                                 compatible = "socionext,uniphier-pxs2-thermal";
 443                                 interrupts = <0 3 4>;
 444                                 #thermal-sensor-cells = <0>;
 445                                 socionext,tmod-calibration = <0x0f86 0x6844>;
 446                         };
 447                 };
 448
 449                 nand: nand@68000000 {
 450                         compatible = "socionext,uniphier-denali-nand-v5b";
 451                         status = "disabled";
 452                         reg-names = "nand_data", "denali_reg";
 453                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 454                         interrupts = <0 65 4>;
 455                         pinctrl-names = "default";
 456                         pinctrl-0 = <&pinctrl_nand2cs>;
 457                         clocks = <&sys_clk 2>;
 458                         resets = <&sys_rst 2>;
 459                 };
 460         };
 461 };
 462
 463 #include "uniphier-pinctrl.dtsi"