arch/arm/boot/dts/uniphier-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro5 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pro5";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         clocks = <&sys_clk 32>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                         operating-points-v2 = <&cpu_opp>;
  27                 };
  28
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                         clocks = <&sys_clk 32>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                         operating-points-v2 = <&cpu_opp>;
  37                 };
  38         };
  39
  40         cpu_opp: opp-table {
  41                 compatible = "operating-points-v2";
  42                 opp-shared;
  43
  44                 opp-100000000 {
  45                         opp-hz = /bits/ 64 <100000000>;
  46                         clock-latency-ns = <300>;
  47                 };
  48                 opp-116667000 {
  49                         opp-hz = /bits/ 64 <116667000>;
  50                         clock-latency-ns = <300>;
  51                 };
  52                 opp-150000000 {
  53                         opp-hz = /bits/ 64 <150000000>;
  54                         clock-latency-ns = <300>;
  55                 };
  56                 opp-175000000 {
  57                         opp-hz = /bits/ 64 <175000000>;
  58                         clock-latency-ns = <300>;
  59                 };
  60                 opp-200000000 {
  61                         opp-hz = /bits/ 64 <200000000>;
  62                         clock-latency-ns = <300>;
  63                 };
  64                 opp-233334000 {
  65                         opp-hz = /bits/ 64 <233334000>;
  66                         clock-latency-ns = <300>;
  67                 };
  68                 opp-300000000 {
  69                         opp-hz = /bits/ 64 <300000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp-350000000 {
  73                         opp-hz = /bits/ 64 <350000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp-400000000 {
  77                         opp-hz = /bits/ 64 <400000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp-466667000 {
  81                         opp-hz = /bits/ 64 <466667000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-600000000 {
  85                         opp-hz = /bits/ 64 <600000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-700000000 {
  89                         opp-hz = /bits/ 64 <700000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-933334000 {
  97                         opp-hz = /bits/ 64 <933334000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-1200000000 {
 101                         opp-hz = /bits/ 64 <1200000000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-1400000000 {
 105                         opp-hz = /bits/ 64 <1400000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-0.2";
 112                 method = "smc";
 113         };
 114
 115         clocks {
 116                 refclk: ref {
 117                         compatible = "fixed-clock";
 118                         #clock-cells = <0>;
 119                         clock-frequency = <20000000>;
 120                 };
 121
 122                 arm_timer_clk: arm-timer {
 123                         #clock-cells = <0>;
 124                         compatible = "fixed-clock";
 125                         clock-frequency = <50000000>;
 126                 };
 127         };
 128
 129         soc {
 130                 compatible = "simple-bus";
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges;
 134                 interrupt-parent = <&intc>;
 135
 136                 l2: l2-cache@500c0000 {
 137                         compatible = "socionext,uniphier-system-cache";
 138                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 139                               <0x506c0000 0x400>;
 140                         interrupts = <0 190 4>, <0 191 4>;
 141                         cache-unified;
 142                         cache-size = <(2 * 1024 * 1024)>;
 143                         cache-sets = <512>;
 144                         cache-line-size = <128>;
 145                         cache-level = <2>;
 146                         next-level-cache = <&l3>;
 147                 };
 148
 149                 l3: l3-cache@500c8000 {
 150                         compatible = "socionext,uniphier-system-cache";
 151                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 152                               <0x506c8000 0x400>;
 153                         interrupts = <0 174 4>, <0 175 4>;
 154                         cache-unified;
 155                         cache-size = <(2 * 1024 * 1024)>;
 156                         cache-sets = <512>;
 157                         cache-line-size = <256>;
 158                         cache-level = <3>;
 159                 };
 160
 161                 serial0: serial@54006800 {
 162                         compatible = "socionext,uniphier-uart";
 163                         status = "disabled";
 164                         reg = <0x54006800 0x40>;
 165                         interrupts = <0 33 4>;
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&pinctrl_uart0>;
 168                         clocks = <&peri_clk 0>;
 169                         resets = <&peri_rst 0>;
 170                 };
 171
 172                 serial1: serial@54006900 {
 173                         compatible = "socionext,uniphier-uart";
 174                         status = "disabled";
 175                         reg = <0x54006900 0x40>;
 176                         interrupts = <0 35 4>;
 177                         pinctrl-names = "default";
 178                         pinctrl-0 = <&pinctrl_uart1>;
 179                         clocks = <&peri_clk 1>;
 180                         resets = <&peri_rst 1>;
 181                 };
 182
 183                 serial2: serial@54006a00 {
 184                         compatible = "socionext,uniphier-uart";
 185                         status = "disabled";
 186                         reg = <0x54006a00 0x40>;
 187                         interrupts = <0 37 4>;
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&pinctrl_uart2>;
 190                         clocks = <&peri_clk 2>;
 191                         resets = <&peri_rst 2>;
 192                 };
 193
 194                 serial3: serial@54006b00 {
 195                         compatible = "socionext,uniphier-uart";
 196                         status = "disabled";
 197                         reg = <0x54006b00 0x40>;
 198                         interrupts = <0 177 4>;
 199                         pinctrl-names = "default";
 200                         pinctrl-0 = <&pinctrl_uart3>;
 201                         clocks = <&peri_clk 3>;
 202                         resets = <&peri_rst 3>;
 203                 };
 204
 205                 gpio: gpio@55000000 {
 206                         compatible = "socionext,uniphier-gpio";
 207                         reg = <0x55000000 0x200>;
 208                         interrupt-parent = <&aidet>;
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                         gpio-controller;
 212                         #gpio-cells = <2>;
 213                         gpio-ranges = <&pinctrl 0 0 0>;
 214                         gpio-ranges-group-names = "gpio_range";
 215                         ngpios = <248>;
 216                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
 217                 };
 218
 219                 i2c0: i2c@58780000 {
 220                         compatible = "socionext,uniphier-fi2c";
 221                         status = "disabled";
 222                         reg = <0x58780000 0x80>;
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         interrupts = <0 41 4>;
 226                         pinctrl-names = "default";
 227                         pinctrl-0 = <&pinctrl_i2c0>;
 228                         clocks = <&peri_clk 4>;
 229                         resets = <&peri_rst 4>;
 230                         clock-frequency = <100000>;
 231                 };
 232
 233                 i2c1: i2c@58781000 {
 234                         compatible = "socionext,uniphier-fi2c";
 235                         status = "disabled";
 236                         reg = <0x58781000 0x80>;
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         interrupts = <0 42 4>;
 240                         pinctrl-names = "default";
 241                         pinctrl-0 = <&pinctrl_i2c1>;
 242                         clocks = <&peri_clk 5>;
 243                         resets = <&peri_rst 5>;
 244                         clock-frequency = <100000>;
 245                 };
 246
 247                 i2c2: i2c@58782000 {
 248                         compatible = "socionext,uniphier-fi2c";
 249                         status = "disabled";
 250                         reg = <0x58782000 0x80>;
 251                         #address-cells = <1>;
 252                         #size-cells = <0>;
 253                         interrupts = <0 43 4>;
 254                         pinctrl-names = "default";
 255                         pinctrl-0 = <&pinctrl_i2c2>;
 256                         clocks = <&peri_clk 6>;
 257                         resets = <&peri_rst 6>;
 258                         clock-frequency = <100000>;
 259                 };
 260
 261                 i2c3: i2c@58783000 {
 262                         compatible = "socionext,uniphier-fi2c";
 263                         status = "disabled";
 264                         reg = <0x58783000 0x80>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         interrupts = <0 44 4>;
 268                         pinctrl-names = "default";
 269                         pinctrl-0 = <&pinctrl_i2c3>;
 270                         clocks = <&peri_clk 7>;
 271                         resets = <&peri_rst 7>;
 272                         clock-frequency = <100000>;
 273                 };
 274
 275                 /* i2c4 does not exist */
 276
 277                 /* chip-internal connection for DMD */
 278                 i2c5: i2c@58785000 {
 279                         compatible = "socionext,uniphier-fi2c";
 280                         reg = <0x58785000 0x80>;
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         interrupts = <0 25 4>;
 284                         clocks = <&peri_clk 9>;
 285                         resets = <&peri_rst 9>;
 286                         clock-frequency = <400000>;
 287                 };
 288
 289                 /* chip-internal connection for HDMI */
 290                 i2c6: i2c@58786000 {
 291                         compatible = "socionext,uniphier-fi2c";
 292                         reg = <0x58786000 0x80>;
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         interrupts = <0 26 4>;
 296                         clocks = <&peri_clk 10>;
 297                         resets = <&peri_rst 10>;
 298                         clock-frequency = <400000>;
 299                 };
 300
 301                 system_bus: system-bus@58c00000 {
 302                         compatible = "socionext,uniphier-system-bus";
 303                         status = "disabled";
 304                         reg = <0x58c00000 0x400>;
 305                         #address-cells = <2>;
 306                         #size-cells = <1>;
 307                         pinctrl-names = "default";
 308                         pinctrl-0 = <&pinctrl_system_bus>;
 309                 };
 310
 311                 smpctrl@59801000 {
 312                         compatible = "socionext,uniphier-smpctrl";
 313                         reg = <0x59801000 0x400>;
 314                 };
 315
 316                 sdctrl@59810000 {
 317                         compatible = "socionext,uniphier-pro5-sdctrl",
 318                                      "simple-mfd", "syscon";
 319                         reg = <0x59810000 0x400>;
 320
 321                         sd_clk: clock {
 322                                 compatible = "socionext,uniphier-pro5-sd-clock";
 323                                 #clock-cells = <1>;
 324                         };
 325
 326                         sd_rst: reset {
 327                                 compatible = "socionext,uniphier-pro5-sd-reset";
 328                                 #reset-cells = <1>;
 329                         };
 330                 };
 331
 332                 perictrl@59820000 {
 333                         compatible = "socionext,uniphier-pro5-perictrl",
 334                                      "simple-mfd", "syscon";
 335                         reg = <0x59820000 0x200>;
 336
 337                         peri_clk: clock {
 338                                 compatible = "socionext,uniphier-pro5-peri-clock";
 339                                 #clock-cells = <1>;
 340                         };
 341
 342                         peri_rst: reset {
 343                                 compatible = "socionext,uniphier-pro5-peri-reset";
 344                                 #reset-cells = <1>;
 345                         };
 346                 };
 347
 348                 soc-glue@5f800000 {
 349                         compatible = "socionext,uniphier-pro5-soc-glue",
 350                                      "simple-mfd", "syscon";
 351                         reg = <0x5f800000 0x2000>;
 352
 353                         pinctrl: pinctrl {
 354                                 compatible = "socionext,uniphier-pro5-pinctrl";
 355                         };
 356                 };
 357
 358                 aidet: aidet@5fc20000 {
 359                         compatible = "socionext,uniphier-pro5-aidet";
 360                         reg = <0x5fc20000 0x200>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                 };
 364
 365                 timer@60000200 {
 366                         compatible = "arm,cortex-a9-global-timer";
 367                         reg = <0x60000200 0x20>;
 368                         interrupts = <1 11 0x304>;
 369                         clocks = <&arm_timer_clk>;
 370                 };
 371
 372                 timer@60000600 {
 373                         compatible = "arm,cortex-a9-twd-timer";
 374                         reg = <0x60000600 0x20>;
 375                         interrupts = <1 13 0x304>;
 376                         clocks = <&arm_timer_clk>;
 377                 };
 378
 379                 intc: interrupt-controller@60001000 {
 380                         compatible = "arm,cortex-a9-gic";
 381                         reg = <0x60001000 0x1000>,
 382                               <0x60000100 0x100>;
 383                         #interrupt-cells = <3>;
 384                         interrupt-controller;
 385                 };
 386
 387                 sysctrl@61840000 {
 388                         compatible = "socionext,uniphier-pro5-sysctrl",
 389                                      "simple-mfd", "syscon";
 390                         reg = <0x61840000 0x10000>;
 391
 392                         sys_clk: clock {
 393                                 compatible = "socionext,uniphier-pro5-clock";
 394                                 #clock-cells = <1>;
 395                         };
 396
 397                         sys_rst: reset {
 398                                 compatible = "socionext,uniphier-pro5-reset";
 399                                 #reset-cells = <1>;
 400                         };
 401                 };
 402
 403                 nand: nand@68000000 {
 404                         compatible = "socionext,uniphier-denali-nand-v5b";
 405                         status = "disabled";
 406                         reg-names = "nand_data", "denali_reg";
 407                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 408                         interrupts = <0 65 4>;
 409                         pinctrl-names = "default";
 410                         pinctrl-0 = <&pinctrl_nand2cs>;
 411                         clocks = <&sys_clk 2>;
 412                         resets = <&sys_rst 2>;
 413                 };
 414         };
 415 };
 416
 417 #include "uniphier-pinctrl.dtsi"