arch/arm/boot/dts/uniphier-pro5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier Pro5 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 / {
   9         compatible = "socionext,uniphier-pro5";
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu@0 {
  18                         device_type = "cpu";
  19                         compatible = "arm,cortex-a9";
  20                         reg = <0>;
  21                         clocks = <&sys_clk 32>;
  22                         enable-method = "psci";
  23                         next-level-cache = <&l2>;
  24                         operating-points-v2 = <&cpu_opp>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         clocks = <&sys_clk 32>;
  32                         enable-method = "psci";
  33                         next-level-cache = <&l2>;
  34                         operating-points-v2 = <&cpu_opp>;
  35                 };
  36         };
  37
  38         cpu_opp: opp-table {
  39                 compatible = "operating-points-v2";
  40                 opp-shared;
  41
  42                 opp-100000000 {
  43                         opp-hz = /bits/ 64 <100000000>;
  44                         clock-latency-ns = <300>;
  45                 };
  46                 opp-116667000 {
  47                         opp-hz = /bits/ 64 <116667000>;
  48                         clock-latency-ns = <300>;
  49                 };
  50                 opp-150000000 {
  51                         opp-hz = /bits/ 64 <150000000>;
  52                         clock-latency-ns = <300>;
  53                 };
  54                 opp-175000000 {
  55                         opp-hz = /bits/ 64 <175000000>;
  56                         clock-latency-ns = <300>;
  57                 };
  58                 opp-200000000 {
  59                         opp-hz = /bits/ 64 <200000000>;
  60                         clock-latency-ns = <300>;
  61                 };
  62                 opp-233334000 {
  63                         opp-hz = /bits/ 64 <233334000>;
  64                         clock-latency-ns = <300>;
  65                 };
  66                 opp-300000000 {
  67                         opp-hz = /bits/ 64 <300000000>;
  68                         clock-latency-ns = <300>;
  69                 };
  70                 opp-350000000 {
  71                         opp-hz = /bits/ 64 <350000000>;
  72                         clock-latency-ns = <300>;
  73                 };
  74                 opp-400000000 {
  75                         opp-hz = /bits/ 64 <400000000>;
  76                         clock-latency-ns = <300>;
  77                 };
  78                 opp-466667000 {
  79                         opp-hz = /bits/ 64 <466667000>;
  80                         clock-latency-ns = <300>;
  81                 };
  82                 opp-600000000 {
  83                         opp-hz = /bits/ 64 <600000000>;
  84                         clock-latency-ns = <300>;
  85                 };
  86                 opp-700000000 {
  87                         opp-hz = /bits/ 64 <700000000>;
  88                         clock-latency-ns = <300>;
  89                 };
  90                 opp-800000000 {
  91                         opp-hz = /bits/ 64 <800000000>;
  92                         clock-latency-ns = <300>;
  93                 };
  94                 opp-933334000 {
  95                         opp-hz = /bits/ 64 <933334000>;
  96                         clock-latency-ns = <300>;
  97                 };
  98                 opp-1200000000 {
  99                         opp-hz = /bits/ 64 <1200000000>;
 100                         clock-latency-ns = <300>;
 101                 };
 102                 opp-1400000000 {
 103                         opp-hz = /bits/ 64 <1400000000>;
 104                         clock-latency-ns = <300>;
 105                 };
 106         };
 107
 108         psci {
 109                 compatible = "arm,psci-0.2";
 110                 method = "smc";
 111         };
 112
 113         clocks {
 114                 refclk: ref {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <20000000>;
 118                 };
 119
 120                 arm_timer_clk: arm-timer {
 121                         #clock-cells = <0>;
 122                         compatible = "fixed-clock";
 123                         clock-frequency = <50000000>;
 124                 };
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132                 interrupt-parent = <&intc>;
 133
 134                 l2: l2-cache@500c0000 {
 135                         compatible = "socionext,uniphier-system-cache";
 136                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 137                               <0x506c0000 0x400>;
 138                         interrupts = <0 190 4>, <0 191 4>;
 139                         cache-unified;
 140                         cache-size = <(2 * 1024 * 1024)>;
 141                         cache-sets = <512>;
 142                         cache-line-size = <128>;
 143                         cache-level = <2>;
 144                         next-level-cache = <&l3>;
 145                 };
 146
 147                 l3: l3-cache@500c8000 {
 148                         compatible = "socionext,uniphier-system-cache";
 149                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 150                               <0x506c8000 0x400>;
 151                         interrupts = <0 174 4>, <0 175 4>;
 152                         cache-unified;
 153                         cache-size = <(2 * 1024 * 1024)>;
 154                         cache-sets = <512>;
 155                         cache-line-size = <256>;
 156                         cache-level = <3>;
 157                 };
 158
 159                 spi0: spi@54006000 {
 160                         compatible = "socionext,uniphier-scssi";
 161                         status = "disabled";
 162                         reg = <0x54006000 0x100>;
 163                         interrupts = <0 39 4>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_spi0>;
 166                         clocks = <&peri_clk 11>;
 167                         resets = <&peri_rst 11>;
 168                 };
 169
 170                 spi1: spi@54006100 {
 171                         compatible = "socionext,uniphier-scssi";
 172                         status = "disabled";
 173                         reg = <0x54006100 0x100>;
 174                         interrupts = <0 216 4>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_spi1>;
 177                         clocks = <&peri_clk 11>;
 178                         resets = <&peri_rst 11>;
 179                 };
 180
 181                 serial0: serial@54006800 {
 182                         compatible = "socionext,uniphier-uart";
 183                         status = "disabled";
 184                         reg = <0x54006800 0x40>;
 185                         interrupts = <0 33 4>;
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&pinctrl_uart0>;
 188                         clocks = <&peri_clk 0>;
 189                         resets = <&peri_rst 0>;
 190                 };
 191
 192                 serial1: serial@54006900 {
 193                         compatible = "socionext,uniphier-uart";
 194                         status = "disabled";
 195                         reg = <0x54006900 0x40>;
 196                         interrupts = <0 35 4>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&pinctrl_uart1>;
 199                         clocks = <&peri_clk 1>;
 200                         resets = <&peri_rst 1>;
 201                 };
 202
 203                 serial2: serial@54006a00 {
 204                         compatible = "socionext,uniphier-uart";
 205                         status = "disabled";
 206                         reg = <0x54006a00 0x40>;
 207                         interrupts = <0 37 4>;
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&pinctrl_uart2>;
 210                         clocks = <&peri_clk 2>;
 211                         resets = <&peri_rst 2>;
 212                 };
 213
 214                 serial3: serial@54006b00 {
 215                         compatible = "socionext,uniphier-uart";
 216                         status = "disabled";
 217                         reg = <0x54006b00 0x40>;
 218                         interrupts = <0 177 4>;
 219                         pinctrl-names = "default";
 220                         pinctrl-0 = <&pinctrl_uart3>;
 221                         clocks = <&peri_clk 3>;
 222                         resets = <&peri_rst 3>;
 223                 };
 224
 225                 gpio: gpio@55000000 {
 226                         compatible = "socionext,uniphier-gpio";
 227                         reg = <0x55000000 0x200>;
 228                         interrupt-parent = <&aidet>;
 229                         interrupt-controller;
 230                         #interrupt-cells = <2>;
 231                         gpio-controller;
 232                         #gpio-cells = <2>;
 233                         gpio-ranges = <&pinctrl 0 0 0>;
 234                         gpio-ranges-group-names = "gpio_range";
 235                         ngpios = <248>;
 236                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
 237                 };
 238
 239                 i2c0: i2c@58780000 {
 240                         compatible = "socionext,uniphier-fi2c";
 241                         status = "disabled";
 242                         reg = <0x58780000 0x80>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         interrupts = <0 41 4>;
 246                         pinctrl-names = "default";
 247                         pinctrl-0 = <&pinctrl_i2c0>;
 248                         clocks = <&peri_clk 4>;
 249                         resets = <&peri_rst 4>;
 250                         clock-frequency = <100000>;
 251                 };
 252
 253                 i2c1: i2c@58781000 {
 254                         compatible = "socionext,uniphier-fi2c";
 255                         status = "disabled";
 256                         reg = <0x58781000 0x80>;
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         interrupts = <0 42 4>;
 260                         pinctrl-names = "default";
 261                         pinctrl-0 = <&pinctrl_i2c1>;
 262                         clocks = <&peri_clk 5>;
 263                         resets = <&peri_rst 5>;
 264                         clock-frequency = <100000>;
 265                 };
 266
 267                 i2c2: i2c@58782000 {
 268                         compatible = "socionext,uniphier-fi2c";
 269                         status = "disabled";
 270                         reg = <0x58782000 0x80>;
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         interrupts = <0 43 4>;
 274                         pinctrl-names = "default";
 275                         pinctrl-0 = <&pinctrl_i2c2>;
 276                         clocks = <&peri_clk 6>;
 277                         resets = <&peri_rst 6>;
 278                         clock-frequency = <100000>;
 279                 };
 280
 281                 i2c3: i2c@58783000 {
 282                         compatible = "socionext,uniphier-fi2c";
 283                         status = "disabled";
 284                         reg = <0x58783000 0x80>;
 285                         #address-cells = <1>;
 286                         #size-cells = <0>;
 287                         interrupts = <0 44 4>;
 288                         pinctrl-names = "default";
 289                         pinctrl-0 = <&pinctrl_i2c3>;
 290                         clocks = <&peri_clk 7>;
 291                         resets = <&peri_rst 7>;
 292                         clock-frequency = <100000>;
 293                 };
 294
 295                 /* i2c4 does not exist */
 296
 297                 /* chip-internal connection for DMD */
 298                 i2c5: i2c@58785000 {
 299                         compatible = "socionext,uniphier-fi2c";
 300                         reg = <0x58785000 0x80>;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         interrupts = <0 25 4>;
 304                         clocks = <&peri_clk 9>;
 305                         resets = <&peri_rst 9>;
 306                         clock-frequency = <400000>;
 307                 };
 308
 309                 /* chip-internal connection for HDMI */
 310                 i2c6: i2c@58786000 {
 311                         compatible = "socionext,uniphier-fi2c";
 312                         reg = <0x58786000 0x80>;
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         interrupts = <0 26 4>;
 316                         clocks = <&peri_clk 10>;
 317                         resets = <&peri_rst 10>;
 318                         clock-frequency = <400000>;
 319                 };
 320
 321                 system_bus: system-bus@58c00000 {
 322                         compatible = "socionext,uniphier-system-bus";
 323                         status = "disabled";
 324                         reg = <0x58c00000 0x400>;
 325                         #address-cells = <2>;
 326                         #size-cells = <1>;
 327                         pinctrl-names = "default";
 328                         pinctrl-0 = <&pinctrl_system_bus>;
 329                 };
 330
 331                 smpctrl@59801000 {
 332                         compatible = "socionext,uniphier-smpctrl";
 333                         reg = <0x59801000 0x400>;
 334                 };
 335
 336                 sdctrl@59810000 {
 337                         compatible = "socionext,uniphier-pro5-sdctrl",
 338                                      "simple-mfd", "syscon";
 339                         reg = <0x59810000 0x400>;
 340
 341                         sd_clk: clock {
 342                                 compatible = "socionext,uniphier-pro5-sd-clock";
 343                                 #clock-cells = <1>;
 344                         };
 345
 346                         sd_rst: reset {
 347                                 compatible = "socionext,uniphier-pro5-sd-reset";
 348                                 #reset-cells = <1>;
 349                         };
 350                 };
 351
 352                 perictrl@59820000 {
 353                         compatible = "socionext,uniphier-pro5-perictrl",
 354                                      "simple-mfd", "syscon";
 355                         reg = <0x59820000 0x200>;
 356
 357                         peri_clk: clock {
 358                                 compatible = "socionext,uniphier-pro5-peri-clock";
 359                                 #clock-cells = <1>;
 360                         };
 361
 362                         peri_rst: reset {
 363                                 compatible = "socionext,uniphier-pro5-peri-reset";
 364                                 #reset-cells = <1>;
 365                         };
 366                 };
 367
 368                 soc-glue@5f800000 {
 369                         compatible = "socionext,uniphier-pro5-soc-glue",
 370                                      "simple-mfd", "syscon";
 371                         reg = <0x5f800000 0x2000>;
 372
 373                         pinctrl: pinctrl {
 374                                 compatible = "socionext,uniphier-pro5-pinctrl";
 375                         };
 376                 };
 377
 378                 soc-glue@5f900000 {
 379                         compatible = "socionext,uniphier-pro5-soc-glue-debug",
 380                                      "simple-mfd";
 381                         #address-cells = <1>;
 382                         #size-cells = <1>;
 383                         ranges = <0 0x5f900000 0x2000>;
 384
 385                         efuse@100 {
 386                                 compatible = "socionext,uniphier-efuse";
 387                                 reg = <0x100 0x28>;
 388                         };
 389
 390                         efuse@130 {
 391                                 compatible = "socionext,uniphier-efuse";
 392                                 reg = <0x130 0x8>;
 393                         };
 394
 395                         efuse@200 {
 396                                 compatible = "socionext,uniphier-efuse";
 397                                 reg = <0x200 0x28>;
 398                         };
 399
 400                         efuse@300 {
 401                                 compatible = "socionext,uniphier-efuse";
 402                                 reg = <0x300 0x14>;
 403                         };
 404
 405                         efuse@400 {
 406                                 compatible = "socionext,uniphier-efuse";
 407                                 reg = <0x400 0x8>;
 408                         };
 409                 };
 410
 411                 aidet: aidet@5fc20000 {
 412                         compatible = "socionext,uniphier-pro5-aidet";
 413                         reg = <0x5fc20000 0x200>;
 414                         interrupt-controller;
 415                         #interrupt-cells = <2>;
 416                 };
 417
 418                 timer@60000200 {
 419                         compatible = "arm,cortex-a9-global-timer";
 420                         reg = <0x60000200 0x20>;
 421                         interrupts = <1 11 0x304>;
 422                         clocks = <&arm_timer_clk>;
 423                 };
 424
 425                 timer@60000600 {
 426                         compatible = "arm,cortex-a9-twd-timer";
 427                         reg = <0x60000600 0x20>;
 428                         interrupts = <1 13 0x304>;
 429                         clocks = <&arm_timer_clk>;
 430                 };
 431
 432                 intc: interrupt-controller@60001000 {
 433                         compatible = "arm,cortex-a9-gic";
 434                         reg = <0x60001000 0x1000>,
 435                               <0x60000100 0x100>;
 436                         #interrupt-cells = <3>;
 437                         interrupt-controller;
 438                 };
 439
 440                 sysctrl@61840000 {
 441                         compatible = "socionext,uniphier-pro5-sysctrl",
 442                                      "simple-mfd", "syscon";
 443                         reg = <0x61840000 0x10000>;
 444
 445                         sys_clk: clock {
 446                                 compatible = "socionext,uniphier-pro5-clock";
 447                                 #clock-cells = <1>;
 448                         };
 449
 450                         sys_rst: reset {
 451                                 compatible = "socionext,uniphier-pro5-reset";
 452                                 #reset-cells = <1>;
 453                         };
 454                 };
 455
 456                 nand: nand@68000000 {
 457                         compatible = "socionext,uniphier-denali-nand-v5b";
 458                         status = "disabled";
 459                         reg-names = "nand_data", "denali_reg";
 460                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 461                         interrupts = <0 65 4>;
 462                         pinctrl-names = "default";
 463                         pinctrl-0 = <&pinctrl_nand2cs>;
 464                         clock-names = "nand", "nand_x", "ecc";
 465                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 466                         resets = <&sys_rst 2>;
 467                 };
 468
 469                 emmc: sdhc@68400000 {
 470                         compatible = "socionext,uniphier-sd-v3.1";
 471                         status = "disabled";
 472                         reg = <0x68400000 0x800>;
 473                         interrupts = <0 78 4>;
 474                         pinctrl-names = "default";
 475                         pinctrl-0 = <&pinctrl_emmc>;
 476                         clocks = <&sd_clk 1>;
 477                         reset-names = "host", "hw";
 478                         resets = <&sd_rst 1>, <&sd_rst 6>;
 479                         bus-width = <8>;
 480                         cap-mmc-highspeed;
 481                         cap-mmc-hw-reset;
 482                         non-removable;
 483                 };
 484
 485                 sd: sdhc@68800000 {
 486                         compatible = "socionext,uniphier-sd-v3.1";
 487                         status = "disabled";
 488                         reg = <0x68800000 0x800>;
 489                         interrupts = <0 76 4>;
 490                         pinctrl-names = "default", "uhs";
 491                         pinctrl-0 = <&pinctrl_sd>;
 492                         pinctrl-1 = <&pinctrl_sd_uhs>;
 493                         clocks = <&sd_clk 0>;
 494                         reset-names = "host";
 495                         resets = <&sd_rst 0>;
 496                         bus-width = <4>;
 497                         cap-sd-highspeed;
 498                         sd-uhs-sdr12;
 499                         sd-uhs-sdr25;
 500                         sd-uhs-sdr50;
 501                 };
 502         };
 503 };
 504
 505 #include "uniphier-pinctrl.dtsi"