arch/arm/boot/dts/uniphier-ld4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD4 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9
  10 / {
  11         compatible = "socionext,uniphier-ld4";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <24576000>;
  38                 };
  39
  40                 arm_timer_clk: arm-timer {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: l2-cache@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(512 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 spi: spi@54006000 {
  67                         compatible = "socionext,uniphier-scssi";
  68                         status = "disabled";
  69                         reg = <0x54006000 0x100>;
  70                         interrupts = <0 39 4>;
  71                         pinctrl-names = "default";
  72                         pinctrl-0 = <&pinctrl_spi0>;
  73                         clocks = <&peri_clk 11>;
  74                         resets = <&peri_rst 11>;
  75                 };
  76
  77                 serial0: serial@54006800 {
  78                         compatible = "socionext,uniphier-uart";
  79                         status = "disabled";
  80                         reg = <0x54006800 0x40>;
  81                         interrupts = <0 33 4>;
  82                         pinctrl-names = "default";
  83                         pinctrl-0 = <&pinctrl_uart0>;
  84                         clocks = <&peri_clk 0>;
  85                         resets = <&peri_rst 0>;
  86                 };
  87
  88                 serial1: serial@54006900 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006900 0x40>;
  92                         interrupts = <0 35 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart1>;
  95                         clocks = <&peri_clk 1>;
  96                         resets = <&peri_rst 1>;
  97                 };
  98
  99                 serial2: serial@54006a00 {
 100                         compatible = "socionext,uniphier-uart";
 101                         status = "disabled";
 102                         reg = <0x54006a00 0x40>;
 103                         interrupts = <0 37 4>;
 104                         pinctrl-names = "default";
 105                         pinctrl-0 = <&pinctrl_uart2>;
 106                         clocks = <&peri_clk 2>;
 107                         resets = <&peri_rst 2>;
 108                 };
 109
 110                 serial3: serial@54006b00 {
 111                         compatible = "socionext,uniphier-uart";
 112                         status = "disabled";
 113                         reg = <0x54006b00 0x40>;
 114                         interrupts = <0 29 4>;
 115                         pinctrl-names = "default";
 116                         pinctrl-0 = <&pinctrl_uart3>;
 117                         clocks = <&peri_clk 3>;
 118                         resets = <&peri_rst 3>;
 119                 };
 120
 121                 gpio: gpio@55000000 {
 122                         compatible = "socionext,uniphier-gpio";
 123                         reg = <0x55000000 0x200>;
 124                         interrupt-parent = <&aidet>;
 125                         interrupt-controller;
 126                         #interrupt-cells = <2>;
 127                         gpio-controller;
 128                         #gpio-cells = <2>;
 129                         gpio-ranges = <&pinctrl 0 0 0>;
 130                         gpio-ranges-group-names = "gpio_range";
 131                         ngpios = <136>;
 132                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 133                 };
 134
 135                 i2c0: i2c@58400000 {
 136                         compatible = "socionext,uniphier-i2c";
 137                         status = "disabled";
 138                         reg = <0x58400000 0x40>;
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         interrupts = <0 41 1>;
 142                         pinctrl-names = "default";
 143                         pinctrl-0 = <&pinctrl_i2c0>;
 144                         clocks = <&peri_clk 4>;
 145                         resets = <&peri_rst 4>;
 146                         clock-frequency = <100000>;
 147                 };
 148
 149                 i2c1: i2c@58480000 {
 150                         compatible = "socionext,uniphier-i2c";
 151                         status = "disabled";
 152                         reg = <0x58480000 0x40>;
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         interrupts = <0 42 1>;
 156                         pinctrl-names = "default";
 157                         pinctrl-0 = <&pinctrl_i2c1>;
 158                         clocks = <&peri_clk 5>;
 159                         resets = <&peri_rst 5>;
 160                         clock-frequency = <100000>;
 161                 };
 162
 163                 /* chip-internal connection for DMD */
 164                 i2c2: i2c@58500000 {
 165                         compatible = "socionext,uniphier-i2c";
 166                         reg = <0x58500000 0x40>;
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         interrupts = <0 43 1>;
 170                         pinctrl-names = "default";
 171                         pinctrl-0 = <&pinctrl_i2c2>;
 172                         clocks = <&peri_clk 6>;
 173                         resets = <&peri_rst 6>;
 174                         clock-frequency = <400000>;
 175                 };
 176
 177                 i2c3: i2c@58580000 {
 178                         compatible = "socionext,uniphier-i2c";
 179                         status = "disabled";
 180                         reg = <0x58580000 0x40>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         interrupts = <0 44 1>;
 184                         pinctrl-names = "default";
 185                         pinctrl-0 = <&pinctrl_i2c3>;
 186                         clocks = <&peri_clk 7>;
 187                         resets = <&peri_rst 7>;
 188                         clock-frequency = <100000>;
 189                 };
 190
 191                 system_bus: system-bus@58c00000 {
 192                         compatible = "socionext,uniphier-system-bus";
 193                         status = "disabled";
 194                         reg = <0x58c00000 0x400>;
 195                         #address-cells = <2>;
 196                         #size-cells = <1>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&pinctrl_system_bus>;
 199                 };
 200
 201                 smpctrl@59801000 {
 202                         compatible = "socionext,uniphier-smpctrl";
 203                         reg = <0x59801000 0x400>;
 204                 };
 205
 206                 mioctrl@59810000 {
 207                         compatible = "socionext,uniphier-ld4-mioctrl",
 208                                      "simple-mfd", "syscon";
 209                         reg = <0x59810000 0x800>;
 210
 211                         mio_clk: clock {
 212                                 compatible = "socionext,uniphier-ld4-mio-clock";
 213                                 #clock-cells = <1>;
 214                         };
 215
 216                         mio_rst: reset {
 217                                 compatible = "socionext,uniphier-ld4-mio-reset";
 218                                 #reset-cells = <1>;
 219                         };
 220                 };
 221
 222                 perictrl@59820000 {
 223                         compatible = "socionext,uniphier-ld4-perictrl",
 224                                      "simple-mfd", "syscon";
 225                         reg = <0x59820000 0x200>;
 226
 227                         peri_clk: clock {
 228                                 compatible = "socionext,uniphier-ld4-peri-clock";
 229                                 #clock-cells = <1>;
 230                         };
 231
 232                         peri_rst: reset {
 233                                 compatible = "socionext,uniphier-ld4-peri-reset";
 234                                 #reset-cells = <1>;
 235                         };
 236                 };
 237
 238                 sd: sdhc@5a400000 {
 239                         compatible = "socionext,uniphier-sd-v2.91";
 240                         status = "disabled";
 241                         reg = <0x5a400000 0x200>;
 242                         interrupts = <0 76 4>;
 243                         pinctrl-names = "default", "uhs";
 244                         pinctrl-0 = <&pinctrl_sd>;
 245                         pinctrl-1 = <&pinctrl_sd_uhs>;
 246                         clocks = <&mio_clk 0>;
 247                         reset-names = "host", "bridge";
 248                         resets = <&mio_rst 0>, <&mio_rst 3>;
 249                         bus-width = <4>;
 250                         cap-sd-highspeed;
 251                         sd-uhs-sdr12;
 252                         sd-uhs-sdr25;
 253                         sd-uhs-sdr50;
 254                 };
 255
 256                 emmc: sdhc@5a500000 {
 257                         compatible = "socionext,uniphier-sd-v2.91";
 258                         status = "disabled";
 259                         reg = <0x5a500000 0x200>;
 260                         interrupts = <0 78 4>;
 261                         pinctrl-names = "default";
 262                         pinctrl-0 = <&pinctrl_emmc>;
 263                         clocks = <&mio_clk 1>;
 264                         reset-names = "host", "bridge", "hw";
 265                         resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
 266                         bus-width = <8>;
 267                         cap-mmc-highspeed;
 268                         cap-mmc-hw-reset;
 269                         non-removable;
 270                 };
 271
 272                 usb0: usb@5a800100 {
 273                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 274                         status = "disabled";
 275                         reg = <0x5a800100 0x100>;
 276                         interrupts = <0 80 4>;
 277                         pinctrl-names = "default";
 278                         pinctrl-0 = <&pinctrl_usb0>;
 279                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 280                                  <&mio_clk 12>;
 281                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 282                                  <&mio_rst 12>;
 283                         has-transaction-translator;
 284                 };
 285
 286                 usb1: usb@5a810100 {
 287                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 288                         status = "disabled";
 289                         reg = <0x5a810100 0x100>;
 290                         interrupts = <0 81 4>;
 291                         pinctrl-names = "default";
 292                         pinctrl-0 = <&pinctrl_usb1>;
 293                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 294                                  <&mio_clk 13>;
 295                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 296                                  <&mio_rst 13>;
 297                         has-transaction-translator;
 298                 };
 299
 300                 usb2: usb@5a820100 {
 301                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 302                         status = "disabled";
 303                         reg = <0x5a820100 0x100>;
 304                         interrupts = <0 82 4>;
 305                         pinctrl-names = "default";
 306                         pinctrl-0 = <&pinctrl_usb2>;
 307                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 308                                  <&mio_clk 14>;
 309                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 310                                  <&mio_rst 14>;
 311                         has-transaction-translator;
 312                 };
 313
 314                 soc-glue@5f800000 {
 315                         compatible = "socionext,uniphier-ld4-soc-glue",
 316                                      "simple-mfd", "syscon";
 317                         reg = <0x5f800000 0x2000>;
 318
 319                         pinctrl: pinctrl {
 320                                 compatible = "socionext,uniphier-ld4-pinctrl";
 321                         };
 322                 };
 323
 324                 soc-glue@5f900000 {
 325                         compatible = "socionext,uniphier-ld4-soc-glue-debug",
 326                                      "simple-mfd";
 327                         #address-cells = <1>;
 328                         #size-cells = <1>;
 329                         ranges = <0 0x5f900000 0x2000>;
 330
 331                         efuse@100 {
 332                                 compatible = "socionext,uniphier-efuse";
 333                                 reg = <0x100 0x28>;
 334                         };
 335
 336                         efuse@130 {
 337                                 compatible = "socionext,uniphier-efuse";
 338                                 reg = <0x130 0x8>;
 339                         };
 340                 };
 341
 342                 timer@60000200 {
 343                         compatible = "arm,cortex-a9-global-timer";
 344                         reg = <0x60000200 0x20>;
 345                         interrupts = <1 11 0x104>;
 346                         clocks = <&arm_timer_clk>;
 347                 };
 348
 349                 timer@60000600 {
 350                         compatible = "arm,cortex-a9-twd-timer";
 351                         reg = <0x60000600 0x20>;
 352                         interrupts = <1 13 0x104>;
 353                         clocks = <&arm_timer_clk>;
 354                 };
 355
 356                 intc: interrupt-controller@60001000 {
 357                         compatible = "arm,cortex-a9-gic";
 358                         reg = <0x60001000 0x1000>,
 359                               <0x60000100 0x100>;
 360                         #interrupt-cells = <3>;
 361                         interrupt-controller;
 362                 };
 363
 364                 aidet: aidet@61830000 {
 365                         compatible = "socionext,uniphier-ld4-aidet";
 366                         reg = <0x61830000 0x200>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                 };
 370
 371                 sysctrl@61840000 {
 372                         compatible = "socionext,uniphier-ld4-sysctrl",
 373                                      "simple-mfd", "syscon";
 374                         reg = <0x61840000 0x10000>;
 375
 376                         sys_clk: clock {
 377                                 compatible = "socionext,uniphier-ld4-clock";
 378                                 #clock-cells = <1>;
 379                         };
 380
 381                         sys_rst: reset {
 382                                 compatible = "socionext,uniphier-ld4-reset";
 383                                 #reset-cells = <1>;
 384                         };
 385                 };
 386
 387                 nand: nand@68000000 {
 388                         compatible = "socionext,uniphier-denali-nand-v5a";
 389                         status = "disabled";
 390                         reg-names = "nand_data", "denali_reg";
 391                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 392                         interrupts = <0 65 4>;
 393                         pinctrl-names = "default";
 394                         pinctrl-0 = <&pinctrl_nand2cs>;
 395                         clock-names = "nand", "nand_x", "ecc";
 396                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 397                         resets = <&sys_rst 2>;
 398                 };
 399         };
 400 };
 401
 402 #include "uniphier-pinctrl.dtsi"