arch/arm/boot/dts/uniphier-ld4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier LD4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-ld4";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <24576000>;
  38                 };
  39
  40                 arm_timer_clk: arm-timer {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: l2-cache@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(512 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 serial0: serial@54006800 {
  67                         compatible = "socionext,uniphier-uart";
  68                         status = "disabled";
  69                         reg = <0x54006800 0x40>;
  70                         interrupts = <0 33 4>;
  71                         pinctrl-names = "default";
  72                         pinctrl-0 = <&pinctrl_uart0>;
  73                         clocks = <&peri_clk 0>;
  74                         resets = <&peri_rst 0>;
  75                 };
  76
  77                 serial1: serial@54006900 {
  78                         compatible = "socionext,uniphier-uart";
  79                         status = "disabled";
  80                         reg = <0x54006900 0x40>;
  81                         interrupts = <0 35 4>;
  82                         pinctrl-names = "default";
  83                         pinctrl-0 = <&pinctrl_uart1>;
  84                         clocks = <&peri_clk 1>;
  85                         resets = <&peri_rst 1>;
  86                 };
  87
  88                 serial2: serial@54006a00 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006a00 0x40>;
  92                         interrupts = <0 37 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart2>;
  95                         clocks = <&peri_clk 2>;
  96                         resets = <&peri_rst 2>;
  97                 };
  98
  99                 serial3: serial@54006b00 {
 100                         compatible = "socionext,uniphier-uart";
 101                         status = "disabled";
 102                         reg = <0x54006b00 0x40>;
 103                         interrupts = <0 29 4>;
 104                         pinctrl-names = "default";
 105                         pinctrl-0 = <&pinctrl_uart3>;
 106                         clocks = <&peri_clk 3>;
 107                         resets = <&peri_rst 3>;
 108                 };
 109
 110                 gpio: gpio@55000000 {
 111                         compatible = "socionext,uniphier-gpio";
 112                         reg = <0x55000000 0x200>;
 113                         interrupt-parent = <&aidet>;
 114                         interrupt-controller;
 115                         #interrupt-cells = <2>;
 116                         gpio-controller;
 117                         #gpio-cells = <2>;
 118                         gpio-ranges = <&pinctrl 0 0 0>;
 119                         gpio-ranges-group-names = "gpio_range";
 120                         ngpios = <136>;
 121                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 122                 };
 123
 124                 i2c0: i2c@58400000 {
 125                         compatible = "socionext,uniphier-i2c";
 126                         status = "disabled";
 127                         reg = <0x58400000 0x40>;
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                         interrupts = <0 41 1>;
 131                         pinctrl-names = "default";
 132                         pinctrl-0 = <&pinctrl_i2c0>;
 133                         clocks = <&peri_clk 4>;
 134                         resets = <&peri_rst 4>;
 135                         clock-frequency = <100000>;
 136                 };
 137
 138                 i2c1: i2c@58480000 {
 139                         compatible = "socionext,uniphier-i2c";
 140                         status = "disabled";
 141                         reg = <0x58480000 0x40>;
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         interrupts = <0 42 1>;
 145                         pinctrl-names = "default";
 146                         pinctrl-0 = <&pinctrl_i2c1>;
 147                         clocks = <&peri_clk 5>;
 148                         resets = <&peri_rst 5>;
 149                         clock-frequency = <100000>;
 150                 };
 151
 152                 /* chip-internal connection for DMD */
 153                 i2c2: i2c@58500000 {
 154                         compatible = "socionext,uniphier-i2c";
 155                         reg = <0x58500000 0x40>;
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158                         interrupts = <0 43 1>;
 159                         pinctrl-names = "default";
 160                         pinctrl-0 = <&pinctrl_i2c2>;
 161                         clocks = <&peri_clk 6>;
 162                         resets = <&peri_rst 6>;
 163                         clock-frequency = <400000>;
 164                 };
 165
 166                 i2c3: i2c@58580000 {
 167                         compatible = "socionext,uniphier-i2c";
 168                         status = "disabled";
 169                         reg = <0x58580000 0x40>;
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         interrupts = <0 44 1>;
 173                         pinctrl-names = "default";
 174                         pinctrl-0 = <&pinctrl_i2c3>;
 175                         clocks = <&peri_clk 7>;
 176                         resets = <&peri_rst 7>;
 177                         clock-frequency = <100000>;
 178                 };
 179
 180                 system_bus: system-bus@58c00000 {
 181                         compatible = "socionext,uniphier-system-bus";
 182                         status = "disabled";
 183                         reg = <0x58c00000 0x400>;
 184                         #address-cells = <2>;
 185                         #size-cells = <1>;
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&pinctrl_system_bus>;
 188                 };
 189
 190                 smpctrl@59801000 {
 191                         compatible = "socionext,uniphier-smpctrl";
 192                         reg = <0x59801000 0x400>;
 193                 };
 194
 195                 mioctrl@59810000 {
 196                         compatible = "socionext,uniphier-ld4-mioctrl",
 197                                      "simple-mfd", "syscon";
 198                         reg = <0x59810000 0x800>;
 199
 200                         mio_clk: clock {
 201                                 compatible = "socionext,uniphier-ld4-mio-clock";
 202                                 #clock-cells = <1>;
 203                         };
 204
 205                         mio_rst: reset {
 206                                 compatible = "socionext,uniphier-ld4-mio-reset";
 207                                 #reset-cells = <1>;
 208                         };
 209                 };
 210
 211                 perictrl@59820000 {
 212                         compatible = "socionext,uniphier-ld4-perictrl",
 213                                      "simple-mfd", "syscon";
 214                         reg = <0x59820000 0x200>;
 215
 216                         peri_clk: clock {
 217                                 compatible = "socionext,uniphier-ld4-peri-clock";
 218                                 #clock-cells = <1>;
 219                         };
 220
 221                         peri_rst: reset {
 222                                 compatible = "socionext,uniphier-ld4-peri-reset";
 223                                 #reset-cells = <1>;
 224                         };
 225                 };
 226
 227                 usb0: usb@5a800100 {
 228                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 229                         status = "disabled";
 230                         reg = <0x5a800100 0x100>;
 231                         interrupts = <0 80 4>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&pinctrl_usb0>;
 234                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 235                                  <&mio_clk 12>;
 236                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 237                                  <&mio_rst 12>;
 238                 };
 239
 240                 usb1: usb@5a810100 {
 241                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 242                         status = "disabled";
 243                         reg = <0x5a810100 0x100>;
 244                         interrupts = <0 81 4>;
 245                         pinctrl-names = "default";
 246                         pinctrl-0 = <&pinctrl_usb1>;
 247                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 248                                  <&mio_clk 13>;
 249                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 250                                  <&mio_rst 13>;
 251                 };
 252
 253                 usb2: usb@5a820100 {
 254                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 255                         status = "disabled";
 256                         reg = <0x5a820100 0x100>;
 257                         interrupts = <0 82 4>;
 258                         pinctrl-names = "default";
 259                         pinctrl-0 = <&pinctrl_usb2>;
 260                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 261                                  <&mio_clk 14>;
 262                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 263                                  <&mio_rst 14>;
 264                 };
 265
 266                 soc-glue@5f800000 {
 267                         compatible = "socionext,uniphier-ld4-soc-glue",
 268                                      "simple-mfd", "syscon";
 269                         reg = <0x5f800000 0x2000>;
 270
 271                         pinctrl: pinctrl {
 272                                 compatible = "socionext,uniphier-ld4-pinctrl";
 273                         };
 274                 };
 275
 276                 timer@60000200 {
 277                         compatible = "arm,cortex-a9-global-timer";
 278                         reg = <0x60000200 0x20>;
 279                         interrupts = <1 11 0x104>;
 280                         clocks = <&arm_timer_clk>;
 281                 };
 282
 283                 timer@60000600 {
 284                         compatible = "arm,cortex-a9-twd-timer";
 285                         reg = <0x60000600 0x20>;
 286                         interrupts = <1 13 0x104>;
 287                         clocks = <&arm_timer_clk>;
 288                 };
 289
 290                 intc: interrupt-controller@60001000 {
 291                         compatible = "arm,cortex-a9-gic";
 292                         reg = <0x60001000 0x1000>,
 293                               <0x60000100 0x100>;
 294                         #interrupt-cells = <3>;
 295                         interrupt-controller;
 296                 };
 297
 298                 aidet: aidet@61830000 {
 299                         compatible = "socionext,uniphier-ld4-aidet";
 300                         reg = <0x61830000 0x200>;
 301                         interrupt-controller;
 302                         #interrupt-cells = <2>;
 303                 };
 304
 305                 sysctrl@61840000 {
 306                         compatible = "socionext,uniphier-ld4-sysctrl",
 307                                      "simple-mfd", "syscon";
 308                         reg = <0x61840000 0x10000>;
 309
 310                         sys_clk: clock {
 311                                 compatible = "socionext,uniphier-ld4-clock";
 312                                 #clock-cells = <1>;
 313                         };
 314
 315                         sys_rst: reset {
 316                                 compatible = "socionext,uniphier-ld4-reset";
 317                                 #reset-cells = <1>;
 318                         };
 319                 };
 320
 321                 nand: nand@68000000 {
 322                         compatible = "socionext,uniphier-denali-nand-v5a";
 323                         status = "disabled";
 324                         reg-names = "nand_data", "denali_reg";
 325                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 326                         interrupts = <0 65 4>;
 327                         pinctrl-names = "default";
 328                         pinctrl-0 = <&pinctrl_nand2cs>;
 329                         clocks = <&sys_clk 2>;
 330                         resets = <&sys_rst 2>;
 331                 };
 332         };
 333 };
 334
 335 #include "uniphier-pinctrl.dtsi"