arch/arm/boot/dts/uniphier-common32.dtsi

   1 /*
   2  * Device Tree Source commonly used by UniPhier ARM SoCs
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /include/ "skeleton.dtsi"
  47
  48 / {
  49         psci {
  50                 compatible = "arm,psci-0.2";
  51                 method = "smc";
  52         };
  53
  54         clocks {
  55                 refclk: ref {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                 };
  59         };
  60
  61         soc: soc {
  62                 compatible = "simple-bus";
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66                 interrupt-parent = <&intc>;
  67
  68                 serial0: serial@54006800 {
  69                         compatible = "socionext,uniphier-uart";
  70                         status = "disabled";
  71                         reg = <0x54006800 0x40>;
  72                         interrupts = <0 33 4>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&pinctrl_uart0>;
  75                         clocks = <&peri_clk 0>;
  76                 };
  77
  78                 serial1: serial@54006900 {
  79                         compatible = "socionext,uniphier-uart";
  80                         status = "disabled";
  81                         reg = <0x54006900 0x40>;
  82                         interrupts = <0 35 4>;
  83                         pinctrl-names = "default";
  84                         pinctrl-0 = <&pinctrl_uart1>;
  85                         clocks = <&peri_clk 1>;
  86                 };
  87
  88                 serial2: serial@54006a00 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006a00 0x40>;
  92                         interrupts = <0 37 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart2>;
  95                         clocks = <&peri_clk 2>;
  96                 };
  97
  98                 serial3: serial@54006b00 {
  99                         compatible = "socionext,uniphier-uart";
 100                         status = "disabled";
 101                         reg = <0x54006b00 0x40>;
 102                         interrupts = <0 177 4>;
 103                         pinctrl-names = "default";
 104                         pinctrl-0 = <&pinctrl_uart3>;
 105                         clocks = <&peri_clk 3>;
 106                 };
 107
 108                 system_bus: system-bus@58c00000 {
 109                         compatible = "socionext,uniphier-system-bus";
 110                         status = "disabled";
 111                         reg = <0x58c00000 0x400>;
 112                         #address-cells = <2>;
 113                         #size-cells = <1>;
 114                         pinctrl-names = "default";
 115                         pinctrl-0 = <&pinctrl_system_bus>;
 116                 };
 117
 118                 smpctrl@59800000 {
 119                         compatible = "socionext,uniphier-smpctrl";
 120                         reg = <0x59801000 0x400>;
 121                 };
 122
 123                 mioctrl@59810000 {
 124                         compatible = "socionext,uniphier-mioctrl",
 125                                      "simple-mfd", "syscon";
 126                         reg = <0x59810000 0x800>;
 127
 128                         mio_clk: clock {
 129                                 #clock-cells = <1>;
 130                         };
 131
 132                         mio_rst: reset {
 133                                 #reset-cells = <1>;
 134                         };
 135                 };
 136
 137                 perictrl@59820000 {
 138                         compatible = "socionext,uniphier-perictrl",
 139                                      "simple-mfd", "syscon";
 140                         reg = <0x59820000 0x200>;
 141
 142                         peri_clk: clock {
 143                                 #clock-cells = <1>;
 144                         };
 145
 146                         peri_rst: reset {
 147                                 #reset-cells = <1>;
 148                         };
 149                 };
 150
 151                 timer@60000200 {
 152                         compatible = "arm,cortex-a9-global-timer";
 153                         reg = <0x60000200 0x20>;
 154                         interrupts = <1 11 0x104>;
 155                         clocks = <&arm_timer_clk>;
 156                 };
 157
 158                 timer@60000600 {
 159                         compatible = "arm,cortex-a9-twd-timer";
 160                         reg = <0x60000600 0x20>;
 161                         interrupts = <1 13 0x104>;
 162                         clocks = <&arm_timer_clk>;
 163                 };
 164
 165                 intc: interrupt-controller@60001000 {
 166                         compatible = "arm,cortex-a9-gic";
 167                         reg = <0x60001000 0x1000>,
 168                               <0x60000100 0x100>;
 169                         #interrupt-cells = <3>;
 170                         interrupt-controller;
 171                 };
 172
 173                 soc-glue@5f800000 {
 174                         compatible = "socionext,uniphier-soc-glue",
 175                                      "simple-mfd", "syscon";
 176                         reg = <0x5f800000 0x2000>;
 177
 178                         pinctrl: pinctrl {
 179                                 /* specify compatible in each SoC DTSI */
 180                         };
 181                 };
 182
 183                 sysctrl@61840000 {
 184                         compatible = "socionext,uniphier-sysctrl",
 185                                      "simple-mfd", "syscon";
 186                         reg = <0x61840000 0x4000>;
 187
 188                         sys_clk: clock {
 189                                 #clock-cells = <1>;
 190                         };
 191
 192                         sys_rst: reset {
 193                                 #reset-cells = <1>;
 194                         };
 195                 };
 196         };
 197 };
 198
 199 /include/ "uniphier-pinctrl.dtsi"