arch/arm/boot/dts/tegra30.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra30-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra30-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "nvidia,tegra30";
  12         interrupt-parent = <&lic>;
  13
  14         pcie@3000 {
  15                 compatible = "nvidia,tegra30-pcie";
  16                 device_type = "pci";
  17                 reg = <0x00003000 0x00000800   /* PADS registers */
  18                        0x00003800 0x00000200   /* AFI registers */
  19                        0x10000000 0x10000000>; /* configuration space */
  20                 reg-names = "pads", "afi", "cs";
  21                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  22                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  23                 interrupt-names = "intr", "msi";
  24
  25                 #interrupt-cells = <1>;
  26                 interrupt-map-mask = <0 0 0 0>;
  27                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  28
  29                 bus-range = <0x00 0xff>;
  30                 #address-cells = <3>;
  31                 #size-cells = <2>;
  32
  33                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  34                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  35                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  36                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  37                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  38                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  39
  40                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  41                          <&tegra_car TEGRA30_CLK_AFI>,
  42                          <&tegra_car TEGRA30_CLK_PLL_E>,
  43                          <&tegra_car TEGRA30_CLK_CML0>;
  44                 clock-names = "pex", "afi", "pll_e", "cml";
  45                 resets = <&tegra_car 70>,
  46                          <&tegra_car 72>,
  47                          <&tegra_car 74>;
  48                 reset-names = "pex", "afi", "pcie_x";
  49                 status = "disabled";
  50
  51                 pci@1,0 {
  52                         device_type = "pci";
  53                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  54                         reg = <0x000800 0 0 0 0>;
  55                         bus-range = <0x00 0xff>;
  56                         status = "disabled";
  57
  58                         #address-cells = <3>;
  59                         #size-cells = <2>;
  60                         ranges;
  61
  62                         nvidia,num-lanes = <2>;
  63                 };
  64
  65                 pci@2,0 {
  66                         device_type = "pci";
  67                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  68                         reg = <0x001000 0 0 0 0>;
  69                         bus-range = <0x00 0xff>;
  70                         status = "disabled";
  71
  72                         #address-cells = <3>;
  73                         #size-cells = <2>;
  74                         ranges;
  75
  76                         nvidia,num-lanes = <2>;
  77                 };
  78
  79                 pci@3,0 {
  80                         device_type = "pci";
  81                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  82                         reg = <0x001800 0 0 0 0>;
  83                         bus-range = <0x00 0xff>;
  84                         status = "disabled";
  85
  86                         #address-cells = <3>;
  87                         #size-cells = <2>;
  88                         ranges;
  89
  90                         nvidia,num-lanes = <2>;
  91                 };
  92         };
  93
  94         host1x@50000000 {
  95                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  96                 reg = <0x50000000 0x00024000>;
  97                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  98                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  99                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 100                 resets = <&tegra_car 28>;
 101                 reset-names = "host1x";
 102
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105
 106                 ranges = <0x54000000 0x54000000 0x04000000>;
 107
 108                 mpe@54040000 {
 109                         compatible = "nvidia,tegra30-mpe";
 110                         reg = <0x54040000 0x00040000>;
 111                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 113                         resets = <&tegra_car 60>;
 114                         reset-names = "mpe";
 115                 };
 116
 117                 vi@54080000 {
 118                         compatible = "nvidia,tegra30-vi";
 119                         reg = <0x54080000 0x00040000>;
 120                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 121                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 122                         resets = <&tegra_car 20>;
 123                         reset-names = "vi";
 124                 };
 125
 126                 epp@540c0000 {
 127                         compatible = "nvidia,tegra30-epp";
 128                         reg = <0x540c0000 0x00040000>;
 129                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 130                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 131                         resets = <&tegra_car 19>;
 132                         reset-names = "epp";
 133                 };
 134
 135                 isp@54100000 {
 136                         compatible = "nvidia,tegra30-isp";
 137                         reg = <0x54100000 0x00040000>;
 138                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 140                         resets = <&tegra_car 23>;
 141                         reset-names = "isp";
 142                 };
 143
 144                 gr2d@54140000 {
 145                         compatible = "nvidia,tegra30-gr2d";
 146                         reg = <0x54140000 0x00040000>;
 147                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 148                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 149                         resets = <&tegra_car 21>;
 150                         reset-names = "2d";
 151                 };
 152
 153                 gr3d@54180000 {
 154                         compatible = "nvidia,tegra30-gr3d";
 155                         reg = <0x54180000 0x00040000>;
 156                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 157                                   &tegra_car TEGRA30_CLK_GR3D2>;
 158                         clock-names = "3d", "3d2";
 159                         resets = <&tegra_car 24>,
 160                                  <&tegra_car 98>;
 161                         reset-names = "3d", "3d2";
 162                 };
 163
 164                 dc@54200000 {
 165                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 166                         reg = <0x54200000 0x00040000>;
 167                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 169                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 170                         clock-names = "dc", "parent";
 171                         resets = <&tegra_car 27>;
 172                         reset-names = "dc";
 173
 174                         iommus = <&mc TEGRA_SWGROUP_DC>;
 175
 176                         nvidia,head = <0>;
 177
 178                         rgb {
 179                                 status = "disabled";
 180                         };
 181                 };
 182
 183                 dc@54240000 {
 184                         compatible = "nvidia,tegra30-dc";
 185                         reg = <0x54240000 0x00040000>;
 186                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 187                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 188                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 189                         clock-names = "dc", "parent";
 190                         resets = <&tegra_car 26>;
 191                         reset-names = "dc";
 192
 193                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 194
 195                         nvidia,head = <1>;
 196
 197                         rgb {
 198                                 status = "disabled";
 199                         };
 200                 };
 201
 202                 hdmi@54280000 {
 203                         compatible = "nvidia,tegra30-hdmi";
 204                         reg = <0x54280000 0x00040000>;
 205                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 206                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 207                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 208                         clock-names = "hdmi", "parent";
 209                         resets = <&tegra_car 51>;
 210                         reset-names = "hdmi";
 211                         status = "disabled";
 212                 };
 213
 214                 tvo@542c0000 {
 215                         compatible = "nvidia,tegra30-tvo";
 216                         reg = <0x542c0000 0x00040000>;
 217                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 219                         status = "disabled";
 220                 };
 221
 222                 dsi@54300000 {
 223                         compatible = "nvidia,tegra30-dsi";
 224                         reg = <0x54300000 0x00040000>;
 225                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 226                         resets = <&tegra_car 48>;
 227                         reset-names = "dsi";
 228                         status = "disabled";
 229                 };
 230         };
 231
 232         timer@50040600 {
 233                 compatible = "arm,cortex-a9-twd-timer";
 234                 reg = <0x50040600 0x20>;
 235                 interrupt-parent = <&intc>;
 236                 interrupts = <GIC_PPI 13
 237                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 238                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 239         };
 240
 241         intc: interrupt-controller@50041000 {
 242                 compatible = "arm,cortex-a9-gic";
 243                 reg = <0x50041000 0x1000
 244                        0x50040100 0x0100>;
 245                 interrupt-controller;
 246                 #interrupt-cells = <3>;
 247                 interrupt-parent = <&intc>;
 248         };
 249
 250         cache-controller@50043000 {
 251                 compatible = "arm,pl310-cache";
 252                 reg = <0x50043000 0x1000>;
 253                 arm,data-latency = <6 6 2>;
 254                 arm,tag-latency = <5 5 2>;
 255                 cache-unified;
 256                 cache-level = <2>;
 257         };
 258
 259         lic: interrupt-controller@60004000 {
 260                 compatible = "nvidia,tegra30-ictlr";
 261                 reg = <0x60004000 0x100>,
 262                       <0x60004100 0x50>,
 263                       <0x60004200 0x50>,
 264                       <0x60004300 0x50>,
 265                       <0x60004400 0x50>;
 266                 interrupt-controller;
 267                 #interrupt-cells = <3>;
 268                 interrupt-parent = <&intc>;
 269         };
 270
 271         timer@60005000 {
 272                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 273                 reg = <0x60005000 0x400>;
 274                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 281         };
 282
 283         tegra_car: clock@60006000 {
 284                 compatible = "nvidia,tegra30-car";
 285                 reg = <0x60006000 0x1000>;
 286                 #clock-cells = <1>;
 287                 #reset-cells = <1>;
 288         };
 289
 290         flow-controller@60007000 {
 291                 compatible = "nvidia,tegra30-flowctrl";
 292                 reg = <0x60007000 0x1000>;
 293         };
 294
 295         apbdma: dma@6000a000 {
 296                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 297                 reg = <0x6000a000 0x1400>;
 298                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 331                 resets = <&tegra_car 34>;
 332                 reset-names = "dma";
 333                 #dma-cells = <1>;
 334         };
 335
 336         ahb: ahb@6000c000 {
 337                 compatible = "nvidia,tegra30-ahb";
 338                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 339         };
 340
 341         gpio: gpio@6000d000 {
 342                 compatible = "nvidia,tegra30-gpio";
 343                 reg = <0x6000d000 0x1000>;
 344                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 351                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 352                 #gpio-cells = <2>;
 353                 gpio-controller;
 354                 #interrupt-cells = <2>;
 355                 interrupt-controller;
 356                 /*
 357                 gpio-ranges = <&pinmux 0 0 248>;
 358                 */
 359         };
 360
 361         apbmisc@70000800 {
 362                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 363                 reg = <0x70000800 0x64   /* Chip revision */
 364                        0x70000008 0x04>; /* Strapping options */
 365         };
 366
 367         pinmux: pinmux@70000868 {
 368                 compatible = "nvidia,tegra30-pinmux";
 369                 reg = <0x70000868 0xd4    /* Pad control registers */
 370                        0x70003000 0x3e4>; /* Mux registers */
 371         };
 372
 373         /*
 374          * There are two serial driver i.e. 8250 based simple serial
 375          * driver and APB DMA based serial driver for higher baudrate
 376          * and performace. To enable the 8250 based driver, the compatible
 377          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 378          * the APB DMA based serial driver, the compatible is
 379          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 380          */
 381         uarta: serial@70006000 {
 382                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 383                 reg = <0x70006000 0x40>;
 384                 reg-shift = <2>;
 385                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 387                 resets = <&tegra_car 6>;
 388                 reset-names = "serial";
 389                 dmas = <&apbdma 8>, <&apbdma 8>;
 390                 dma-names = "rx", "tx";
 391                 status = "disabled";
 392         };
 393
 394         uartb: serial@70006040 {
 395                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 396                 reg = <0x70006040 0x40>;
 397                 reg-shift = <2>;
 398                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 400                 resets = <&tegra_car 7>;
 401                 reset-names = "serial";
 402                 dmas = <&apbdma 9>, <&apbdma 9>;
 403                 dma-names = "rx", "tx";
 404                 status = "disabled";
 405         };
 406
 407         uartc: serial@70006200 {
 408                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 409                 reg = <0x70006200 0x100>;
 410                 reg-shift = <2>;
 411                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 413                 resets = <&tegra_car 55>;
 414                 reset-names = "serial";
 415                 dmas = <&apbdma 10>, <&apbdma 10>;
 416                 dma-names = "rx", "tx";
 417                 status = "disabled";
 418         };
 419
 420         uartd: serial@70006300 {
 421                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 422                 reg = <0x70006300 0x100>;
 423                 reg-shift = <2>;
 424                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 426                 resets = <&tegra_car 65>;
 427                 reset-names = "serial";
 428                 dmas = <&apbdma 19>, <&apbdma 19>;
 429                 dma-names = "rx", "tx";
 430                 status = "disabled";
 431         };
 432
 433         uarte: serial@70006400 {
 434                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 435                 reg = <0x70006400 0x100>;
 436                 reg-shift = <2>;
 437                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 438                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 439                 resets = <&tegra_car 66>;
 440                 reset-names = "serial";
 441                 dmas = <&apbdma 20>, <&apbdma 20>;
 442                 dma-names = "rx", "tx";
 443                 status = "disabled";
 444         };
 445
 446         gmi@70009000 {
 447                 compatible = "nvidia,tegra30-gmi";
 448                 reg = <0x70009000 0x1000>;
 449                 #address-cells = <2>;
 450                 #size-cells = <1>;
 451                 ranges = <0 0 0x48000000 0x7ffffff>;
 452                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 453                 clock-names = "gmi";
 454                 resets = <&tegra_car 42>;
 455                 reset-names = "gmi";
 456                 status = "disabled";
 457         };
 458
 459         pwm: pwm@7000a000 {
 460                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 461                 reg = <0x7000a000 0x100>;
 462                 #pwm-cells = <2>;
 463                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 464                 resets = <&tegra_car 17>;
 465                 reset-names = "pwm";
 466                 status = "disabled";
 467         };
 468
 469         rtc@7000e000 {
 470                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 471                 reg = <0x7000e000 0x100>;
 472                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 474         };
 475
 476         i2c@7000c000 {
 477                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 478                 reg = <0x7000c000 0x100>;
 479                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 480                 #address-cells = <1>;
 481                 #size-cells = <0>;
 482                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 483                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 484                 clock-names = "div-clk", "fast-clk";
 485                 resets = <&tegra_car 12>;
 486                 reset-names = "i2c";
 487                 dmas = <&apbdma 21>, <&apbdma 21>;
 488                 dma-names = "rx", "tx";
 489                 status = "disabled";
 490         };
 491
 492         i2c@7000c400 {
 493                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 494                 reg = <0x7000c400 0x100>;
 495                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 499                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 500                 clock-names = "div-clk", "fast-clk";
 501                 resets = <&tegra_car 54>;
 502                 reset-names = "i2c";
 503                 dmas = <&apbdma 22>, <&apbdma 22>;
 504                 dma-names = "rx", "tx";
 505                 status = "disabled";
 506         };
 507
 508         i2c@7000c500 {
 509                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 510                 reg = <0x7000c500 0x100>;
 511                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 515                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 516                 clock-names = "div-clk", "fast-clk";
 517                 resets = <&tegra_car 67>;
 518                 reset-names = "i2c";
 519                 dmas = <&apbdma 23>, <&apbdma 23>;
 520                 dma-names = "rx", "tx";
 521                 status = "disabled";
 522         };
 523
 524         i2c@7000c700 {
 525                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 526                 reg = <0x7000c700 0x100>;
 527                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 531                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 532                 resets = <&tegra_car 103>;
 533                 reset-names = "i2c";
 534                 clock-names = "div-clk", "fast-clk";
 535                 dmas = <&apbdma 26>, <&apbdma 26>;
 536                 dma-names = "rx", "tx";
 537                 status = "disabled";
 538         };
 539
 540         i2c@7000d000 {
 541                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 542                 reg = <0x7000d000 0x100>;
 543                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 547                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 548                 clock-names = "div-clk", "fast-clk";
 549                 resets = <&tegra_car 47>;
 550                 reset-names = "i2c";
 551                 dmas = <&apbdma 24>, <&apbdma 24>;
 552                 dma-names = "rx", "tx";
 553                 status = "disabled";
 554         };
 555
 556         spi@7000d400 {
 557                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 558                 reg = <0x7000d400 0x200>;
 559                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 563                 resets = <&tegra_car 41>;
 564                 reset-names = "spi";
 565                 dmas = <&apbdma 15>, <&apbdma 15>;
 566                 dma-names = "rx", "tx";
 567                 status = "disabled";
 568         };
 569
 570         spi@7000d600 {
 571                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 572                 reg = <0x7000d600 0x200>;
 573                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 577                 resets = <&tegra_car 44>;
 578                 reset-names = "spi";
 579                 dmas = <&apbdma 16>, <&apbdma 16>;
 580                 dma-names = "rx", "tx";
 581                 status = "disabled";
 582         };
 583
 584         spi@7000d800 {
 585                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 586                 reg = <0x7000d800 0x200>;
 587                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 591                 resets = <&tegra_car 46>;
 592                 reset-names = "spi";
 593                 dmas = <&apbdma 17>, <&apbdma 17>;
 594                 dma-names = "rx", "tx";
 595                 status = "disabled";
 596         };
 597
 598         spi@7000da00 {
 599                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 600                 reg = <0x7000da00 0x200>;
 601                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 605                 resets = <&tegra_car 68>;
 606                 reset-names = "spi";
 607                 dmas = <&apbdma 18>, <&apbdma 18>;
 608                 dma-names = "rx", "tx";
 609                 status = "disabled";
 610         };
 611
 612         spi@7000dc00 {
 613                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 614                 reg = <0x7000dc00 0x200>;
 615                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 616                 #address-cells = <1>;
 617                 #size-cells = <0>;
 618                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 619                 resets = <&tegra_car 104>;
 620                 reset-names = "spi";
 621                 dmas = <&apbdma 27>, <&apbdma 27>;
 622                 dma-names = "rx", "tx";
 623                 status = "disabled";
 624         };
 625
 626         spi@7000de00 {
 627                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 628                 reg = <0x7000de00 0x200>;
 629                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 633                 resets = <&tegra_car 106>;
 634                 reset-names = "spi";
 635                 dmas = <&apbdma 28>, <&apbdma 28>;
 636                 dma-names = "rx", "tx";
 637                 status = "disabled";
 638         };
 639
 640         kbc@7000e200 {
 641                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 642                 reg = <0x7000e200 0x100>;
 643                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 645                 resets = <&tegra_car 36>;
 646                 reset-names = "kbc";
 647                 status = "disabled";
 648         };
 649
 650         pmc@7000e400 {
 651                 compatible = "nvidia,tegra30-pmc";
 652                 reg = <0x7000e400 0x400>;
 653                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 654                 clock-names = "pclk", "clk32k_in";
 655         };
 656
 657         mc: memory-controller@7000f000 {
 658                 compatible = "nvidia,tegra30-mc";
 659                 reg = <0x7000f000 0x400>;
 660                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 661                 clock-names = "mc";
 662
 663                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 664
 665                 #iommu-cells = <1>;
 666         };
 667
 668         fuse@7000f800 {
 669                 compatible = "nvidia,tegra30-efuse";
 670                 reg = <0x7000f800 0x400>;
 671                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 672                 clock-names = "fuse";
 673                 resets = <&tegra_car 39>;
 674                 reset-names = "fuse";
 675         };
 676
 677         hda@70030000 {
 678                 compatible = "nvidia,tegra30-hda";
 679                 reg = <0x70030000 0x10000>;
 680                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 681                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 682                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 683                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 684                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 685                 resets = <&tegra_car 125>, /* hda */
 686                          <&tegra_car 128>, /* hda2hdmi */
 687                          <&tegra_car 111>; /* hda2codec_2x */
 688                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 689                 status = "disabled";
 690         };
 691
 692         ahub@70080000 {
 693                 compatible = "nvidia,tegra30-ahub";
 694                 reg = <0x70080000 0x200
 695                        0x70080200 0x100>;
 696                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 697                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 698                          <&tegra_car TEGRA30_CLK_APBIF>;
 699                 clock-names = "d_audio", "apbif";
 700                 resets = <&tegra_car 106>, /* d_audio */
 701                          <&tegra_car 107>, /* apbif */
 702                          <&tegra_car 30>,  /* i2s0 */
 703                          <&tegra_car 11>,  /* i2s1 */
 704                          <&tegra_car 18>,  /* i2s2 */
 705                          <&tegra_car 101>, /* i2s3 */
 706                          <&tegra_car 102>, /* i2s4 */
 707                          <&tegra_car 108>, /* dam0 */
 708                          <&tegra_car 109>, /* dam1 */
 709                          <&tegra_car 110>, /* dam2 */
 710                          <&tegra_car 10>;  /* spdif */
 711                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 712                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 713                               "spdif";
 714                 dmas = <&apbdma 1>, <&apbdma 1>,
 715                        <&apbdma 2>, <&apbdma 2>,
 716                        <&apbdma 3>, <&apbdma 3>,
 717                        <&apbdma 4>, <&apbdma 4>;
 718                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 719                             "rx3", "tx3";
 720                 ranges;
 721                 #address-cells = <1>;
 722                 #size-cells = <1>;
 723
 724                 tegra_i2s0: i2s@70080300 {
 725                         compatible = "nvidia,tegra30-i2s";
 726                         reg = <0x70080300 0x100>;
 727                         nvidia,ahub-cif-ids = <4 4>;
 728                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 729                         resets = <&tegra_car 30>;
 730                         reset-names = "i2s";
 731                         status = "disabled";
 732                 };
 733
 734                 tegra_i2s1: i2s@70080400 {
 735                         compatible = "nvidia,tegra30-i2s";
 736                         reg = <0x70080400 0x100>;
 737                         nvidia,ahub-cif-ids = <5 5>;
 738                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 739                         resets = <&tegra_car 11>;
 740                         reset-names = "i2s";
 741                         status = "disabled";
 742                 };
 743
 744                 tegra_i2s2: i2s@70080500 {
 745                         compatible = "nvidia,tegra30-i2s";
 746                         reg = <0x70080500 0x100>;
 747                         nvidia,ahub-cif-ids = <6 6>;
 748                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 749                         resets = <&tegra_car 18>;
 750                         reset-names = "i2s";
 751                         status = "disabled";
 752                 };
 753
 754                 tegra_i2s3: i2s@70080600 {
 755                         compatible = "nvidia,tegra30-i2s";
 756                         reg = <0x70080600 0x100>;
 757                         nvidia,ahub-cif-ids = <7 7>;
 758                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 759                         resets = <&tegra_car 101>;
 760                         reset-names = "i2s";
 761                         status = "disabled";
 762                 };
 763
 764                 tegra_i2s4: i2s@70080700 {
 765                         compatible = "nvidia,tegra30-i2s";
 766                         reg = <0x70080700 0x100>;
 767                         nvidia,ahub-cif-ids = <8 8>;
 768                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 769                         resets = <&tegra_car 102>;
 770                         reset-names = "i2s";
 771                         status = "disabled";
 772                 };
 773         };
 774
 775         sdhci@78000000 {
 776                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 777                 reg = <0x78000000 0x200>;
 778                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 779                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 780                 resets = <&tegra_car 14>;
 781                 reset-names = "sdhci";
 782                 status = "disabled";
 783         };
 784
 785         sdhci@78000200 {
 786                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 787                 reg = <0x78000200 0x200>;
 788                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 789                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 790                 resets = <&tegra_car 9>;
 791                 reset-names = "sdhci";
 792                 status = "disabled";
 793         };
 794
 795         sdhci@78000400 {
 796                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 797                 reg = <0x78000400 0x200>;
 798                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 799                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 800                 resets = <&tegra_car 69>;
 801                 reset-names = "sdhci";
 802                 status = "disabled";
 803         };
 804
 805         sdhci@78000600 {
 806                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 807                 reg = <0x78000600 0x200>;
 808                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 809                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 810                 resets = <&tegra_car 15>;
 811                 reset-names = "sdhci";
 812                 status = "disabled";
 813         };
 814
 815         usb@7d000000 {
 816                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 817                 reg = <0x7d000000 0x4000>;
 818                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 819                 phy_type = "utmi";
 820                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 821                 resets = <&tegra_car 22>;
 822                 reset-names = "usb";
 823                 nvidia,needs-double-reset;
 824                 nvidia,phy = <&phy1>;
 825                 status = "disabled";
 826         };
 827
 828         phy1: usb-phy@7d000000 {
 829                 compatible = "nvidia,tegra30-usb-phy";
 830                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 831                 phy_type = "utmi";
 832                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 833                          <&tegra_car TEGRA30_CLK_PLL_U>,
 834                          <&tegra_car TEGRA30_CLK_USBD>;
 835                 clock-names = "reg", "pll_u", "utmi-pads";
 836                 resets = <&tegra_car 22>, <&tegra_car 22>;
 837                 reset-names = "usb", "utmi-pads";
 838                 nvidia,hssync-start-delay = <9>;
 839                 nvidia,idle-wait-delay = <17>;
 840                 nvidia,elastic-limit = <16>;
 841                 nvidia,term-range-adj = <6>;
 842                 nvidia,xcvr-setup = <51>;
 843                 nvidia.xcvr-setup-use-fuses;
 844                 nvidia,xcvr-lsfslew = <1>;
 845                 nvidia,xcvr-lsrslew = <1>;
 846                 nvidia,xcvr-hsslew = <32>;
 847                 nvidia,hssquelch-level = <2>;
 848                 nvidia,hsdiscon-level = <5>;
 849                 nvidia,has-utmi-pad-registers;
 850                 status = "disabled";
 851         };
 852
 853         usb@7d004000 {
 854                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 855                 reg = <0x7d004000 0x4000>;
 856                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 857                 phy_type = "utmi";
 858                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 859                 resets = <&tegra_car 58>;
 860                 reset-names = "usb";
 861                 nvidia,phy = <&phy2>;
 862                 status = "disabled";
 863         };
 864
 865         phy2: usb-phy@7d004000 {
 866                 compatible = "nvidia,tegra30-usb-phy";
 867                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 868                 phy_type = "utmi";
 869                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 870                          <&tegra_car TEGRA30_CLK_PLL_U>,
 871                          <&tegra_car TEGRA30_CLK_USBD>;
 872                 clock-names = "reg", "pll_u", "utmi-pads";
 873                 resets = <&tegra_car 58>, <&tegra_car 22>;
 874                 reset-names = "usb", "utmi-pads";
 875                 nvidia,hssync-start-delay = <9>;
 876                 nvidia,idle-wait-delay = <17>;
 877                 nvidia,elastic-limit = <16>;
 878                 nvidia,term-range-adj = <6>;
 879                 nvidia,xcvr-setup = <51>;
 880                 nvidia.xcvr-setup-use-fuses;
 881                 nvidia,xcvr-lsfslew = <2>;
 882                 nvidia,xcvr-lsrslew = <2>;
 883                 nvidia,xcvr-hsslew = <32>;
 884                 nvidia,hssquelch-level = <2>;
 885                 nvidia,hsdiscon-level = <5>;
 886                 status = "disabled";
 887         };
 888
 889         usb@7d008000 {
 890                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 891                 reg = <0x7d008000 0x4000>;
 892                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 893                 phy_type = "utmi";
 894                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 895                 resets = <&tegra_car 59>;
 896                 reset-names = "usb";
 897                 nvidia,phy = <&phy3>;
 898                 status = "disabled";
 899         };
 900
 901         phy3: usb-phy@7d008000 {
 902                 compatible = "nvidia,tegra30-usb-phy";
 903                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 904                 phy_type = "utmi";
 905                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 906                          <&tegra_car TEGRA30_CLK_PLL_U>,
 907                          <&tegra_car TEGRA30_CLK_USBD>;
 908                 clock-names = "reg", "pll_u", "utmi-pads";
 909                 resets = <&tegra_car 59>, <&tegra_car 22>;
 910                 reset-names = "usb", "utmi-pads";
 911                 nvidia,hssync-start-delay = <0>;
 912                 nvidia,idle-wait-delay = <17>;
 913                 nvidia,elastic-limit = <16>;
 914                 nvidia,term-range-adj = <6>;
 915                 nvidia,xcvr-setup = <51>;
 916                 nvidia.xcvr-setup-use-fuses;
 917                 nvidia,xcvr-lsfslew = <2>;
 918                 nvidia,xcvr-lsrslew = <2>;
 919                 nvidia,xcvr-hsslew = <32>;
 920                 nvidia,hssquelch-level = <2>;
 921                 nvidia,hsdiscon-level = <5>;
 922                 status = "disabled";
 923         };
 924
 925         cpus {
 926                 #address-cells = <1>;
 927                 #size-cells = <0>;
 928
 929                 cpu@0 {
 930                         device_type = "cpu";
 931                         compatible = "arm,cortex-a9";
 932                         reg = <0>;
 933                 };
 934
 935                 cpu@1 {
 936                         device_type = "cpu";
 937                         compatible = "arm,cortex-a9";
 938                         reg = <1>;
 939                 };
 940
 941                 cpu@2 {
 942                         device_type = "cpu";
 943                         compatible = "arm,cortex-a9";
 944                         reg = <2>;
 945                 };
 946
 947                 cpu@3 {
 948                         device_type = "cpu";
 949                         compatible = "arm,cortex-a9";
 950                         reg = <3>;
 951                 };
 952         };
 953
 954         pmu {
 955                 compatible = "arm,cortex-a9-pmu";
 956                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 957                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 958                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 959                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 960         };
 961 };