arch/arm/boot/dts/tegra30-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "tegra30.dtsi"
   3
   4 /*
   5  * Toradex Colibri T30 Module Device Tree
   6  * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
   7  */
   8 / {
   9         memory@80000000 {
  10                 reg = <0x80000000 0x40000000>;
  11         };
  12
  13         host1x@50000000 {
  14                 hdmi@54280000 {
  15                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  16                         nvidia,hpd-gpio =
  17                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  18                         pll-supply = <&reg_1v8_avdd_hdmi_pll>;
  19                         vdd-supply = <&reg_3v3_avdd_hdmi>;
  20                 };
  21         };
  22
  23         pinmux@70000868 {
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&state_default>;
  26
  27                 state_default: pinmux {
  28                         /* Analogue Audio (On-module) */
  29                         clk1-out-pw4 {
  30                                 nvidia,pins = "clk1_out_pw4";
  31                                 nvidia,function = "extperiph1";
  32                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  33                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  34                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  35                         };
  36                         dap3-fs-pp0 {
  37                                 nvidia,pins = "dap3_fs_pp0",
  38                                               "dap3_sclk_pp3",
  39                                               "dap3_din_pp1",
  40                                               "dap3_dout_pp2";
  41                                 nvidia,function = "i2s2";
  42                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  43                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  44                         };
  45
  46                         /* Colibri Address/Data Bus (GMI) */
  47                         gmi-ad0-pg0 {
  48                                 nvidia,pins = "gmi_ad0_pg0",
  49                                               "gmi_ad2_pg2",
  50                                               "gmi_ad3_pg3",
  51                                               "gmi_ad4_pg4",
  52                                               "gmi_ad5_pg5",
  53                                               "gmi_ad6_pg6",
  54                                               "gmi_ad7_pg7",
  55                                               "gmi_ad8_ph0",
  56                                               "gmi_ad9_ph1",
  57                                               "gmi_ad10_ph2",
  58                                               "gmi_ad11_ph3",
  59                                               "gmi_ad12_ph4",
  60                                               "gmi_ad13_ph5",
  61                                               "gmi_ad14_ph6",
  62                                               "gmi_ad15_ph7",
  63                                               "gmi_adv_n_pk0",
  64                                               "gmi_clk_pk1",
  65                                               "gmi_cs4_n_pk2",
  66                                               "gmi_cs2_n_pk3",
  67                                               "gmi_iordy_pi5",
  68                                               "gmi_oe_n_pi1",
  69                                               "gmi_wait_pi7",
  70                                               "gmi_wr_n_pi0",
  71                                               "dap1_fs_pn0",
  72                                               "dap1_din_pn1",
  73                                               "dap1_dout_pn2",
  74                                               "dap1_sclk_pn3",
  75                                               "dap2_fs_pa2",
  76                                               "dap2_sclk_pa3",
  77                                               "dap2_din_pa4",
  78                                               "dap2_dout_pa5",
  79                                               "spi1_sck_px5",
  80                                               "spi1_mosi_px4",
  81                                               "spi1_cs0_n_px6",
  82                                               "spi2_cs0_n_px3",
  83                                               "spi2_miso_px1",
  84                                               "spi2_mosi_px0",
  85                                               "spi2_sck_px2",
  86                                               "uart2_cts_n_pj5",
  87                                               "uart2_rts_n_pj6";
  88                                 nvidia,function = "gmi";
  89                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  90                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  92                         };
  93                         /* Further pins may be used as GPIOs */
  94                         dap4-din-pp5 {
  95                                 nvidia,pins = "dap4_din_pp5",
  96                                               "dap4_dout_pp6",
  97                                               "dap4_fs_pp4",
  98                                               "dap4_sclk_pp7",
  99                                               "pbb7",
 100                                               "sdmmc1_clk_pz0",
 101                                               "sdmmc1_cmd_pz1",
 102                                               "sdmmc1_dat0_py7",
 103                                               "sdmmc1_dat1_py6",
 104                                               "sdmmc1_dat3_py4",
 105                                               "uart3_cts_n_pa1",
 106                                               "uart3_txd_pw6",
 107                                               "uart3_rxd_pw7";
 108                                 nvidia,function = "rsvd2";
 109                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 110                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 111                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 112                         };
 113                         lcd-d18-pm2 {
 114                                 nvidia,pins = "lcd_d18_pm2",
 115                                               "lcd_d19_pm3",
 116                                               "lcd_d20_pm4",
 117                                               "lcd_d21_pm5",
 118                                               "lcd_d22_pm6",
 119                                               "lcd_d23_pm7",
 120                                               "lcd_dc0_pn6",
 121                                               "pex_l2_clkreq_n_pcc7";
 122                                 nvidia,function = "rsvd3";
 123                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 124                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 125                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 126                         };
 127                         lcd-cs0-n-pn4 {
 128                                 nvidia,pins = "lcd_cs0_n_pn4",
 129                                               "lcd_sdin_pz2",
 130                                               "pu0",
 131                                               "pu1",
 132                                               "pu2",
 133                                               "pu3",
 134                                               "pu4",
 135                                               "pu5",
 136                                               "pu6",
 137                                               "spi1_miso_px7",
 138                                               "uart3_rts_n_pc0";
 139                                 nvidia,function = "rsvd4";
 140                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 141                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 142                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 143                         };
 144                         lcd-pwr0-pb2 {
 145                                 nvidia,pins = "lcd_pwr0_pb2",
 146                                               "lcd_sck_pz4",
 147                                               "lcd_sdout_pn5",
 148                                               "lcd_wr_n_pz3";
 149                                 nvidia,function = "hdcp";
 150                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 151                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 152                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 153                         };
 154                         pbb4 {
 155                                 nvidia,pins = "pbb4",
 156                                               "pbb5",
 157                                               "pbb6";
 158                                 nvidia,function = "displayb";
 159                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 160                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 161                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 162                         };
 163                         /* Multiplexed RDnWR and therefore disabled */
 164                         lcd-cs1-n-pw0 {
 165                                 nvidia,pins = "lcd_cs1_n_pw0";
 166                                 nvidia,function = "rsvd4";
 167                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 168                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 169                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 170                         };
 171                         /* Multiplexed GMI_CLK and therefore disabled */
 172                         owr {
 173                                 nvidia,pins = "owr";
 174                                 nvidia,function = "rsvd3";
 175                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 176                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 177                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 178                         };
 179                         /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
 180                         sdmmc3-dat4-pd1 {
 181                                 nvidia,pins = "sdmmc3_dat4_pd1";
 182                                 nvidia,function = "sdmmc3";
 183                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 184                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 185                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 186                         };
 187                         /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
 188                         sdmmc3-dat5-pd0 {
 189                                 nvidia,pins = "sdmmc3_dat5_pd0";
 190                                 nvidia,function = "sdmmc3";
 191                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 192                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 193                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 194                         };
 195
 196                         /* Colibri BL_ON */
 197                         pv2 {
 198                                 nvidia,pins = "pv2";
 199                                 nvidia,function = "rsvd4";
 200                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 201                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 202                         };
 203
 204                         /* Colibri Backlight PWM<A> */
 205                         sdmmc3-dat3-pb4 {
 206                                 nvidia,pins = "sdmmc3_dat3_pb4";
 207                                 nvidia,function = "pwm0";
 208                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 209                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 210                         };
 211
 212                         /* Colibri CAN_INT */
 213                         kb-row8-ps0 {
 214                                 nvidia,pins = "kb_row8_ps0";
 215                                 nvidia,function = "kbc";
 216                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 217                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 218                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 219                         };
 220
 221                         /* Colibri DDC */
 222                         ddc-scl-pv4 {
 223                                 nvidia,pins = "ddc_scl_pv4",
 224                                               "ddc_sda_pv5";
 225                                 nvidia,function = "i2c4";
 226                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 227                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 228                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 229                         };
 230
 231                         /* Colibri EXT_IO* */
 232                         gen2-i2c-scl-pt5 {
 233                                 nvidia,pins = "gen2_i2c_scl_pt5",
 234                                               "gen2_i2c_sda_pt6";
 235                                 nvidia,function = "rsvd4";
 236                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 237                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 238                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 239                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 240                         };
 241                         spdif-in-pk6 {
 242                                 nvidia,pins =   "spdif_in_pk6";
 243                                 nvidia,function = "hda";
 244                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 245                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 246                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 247                         };
 248
 249                         /* Colibri GPIO */
 250                         clk2-out-pw5 {
 251                                 nvidia,pins = "clk2_out_pw5",
 252                                               "pcc2",
 253                                               "pv3",
 254                                               "sdmmc1_dat2_py5";
 255                                 nvidia,function = "rsvd2";
 256                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 257                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 258                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 259                         };
 260                         lcd-pwr1-pc1 {
 261                                 nvidia,pins = "lcd_pwr1_pc1",
 262                                               "pex_l1_clkreq_n_pdd6",
 263                                               "pex_l1_rst_n_pdd5";
 264                                 nvidia,function = "rsvd3";
 265                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 266                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 267                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 268                         };
 269                         pv1 {
 270                                 nvidia,pins = "pv1",
 271                                               "sdmmc3_dat0_pb7",
 272                                               "sdmmc3_dat1_pb6";
 273                                 nvidia,function = "rsvd1";
 274                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 275                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 276                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 277                         };
 278
 279                         /* Colibri HOTPLUG_DETECT (HDMI) */
 280                         hdmi-int-pn7 {
 281                                 nvidia,pins = "hdmi_int_pn7";
 282                                 nvidia,function = "hdmi";
 283                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 284                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 285                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 286                         };
 287
 288                         /* Colibri I2C */
 289                         gen1-i2c-scl-pc4 {
 290                                 nvidia,pins = "gen1_i2c_scl_pc4",
 291                                               "gen1_i2c_sda_pc5";
 292                                 nvidia,function = "i2c1";
 293                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 294                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 295                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 296                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 297                         };
 298
 299                         /* Colibri LCD (L_* resp. LDD<*>) */
 300                         lcd-d0-pe0 {
 301                                 nvidia,pins = "lcd_d0_pe0",
 302                                               "lcd_d1_pe1",
 303                                               "lcd_d2_pe2",
 304                                               "lcd_d3_pe3",
 305                                               "lcd_d4_pe4",
 306                                               "lcd_d5_pe5",
 307                                               "lcd_d6_pe6",
 308                                               "lcd_d7_pe7",
 309                                               "lcd_d8_pf0",
 310                                               "lcd_d9_pf1",
 311                                               "lcd_d10_pf2",
 312                                               "lcd_d11_pf3",
 313                                               "lcd_d12_pf4",
 314                                               "lcd_d13_pf5",
 315                                               "lcd_d14_pf6",
 316                                               "lcd_d15_pf7",
 317                                               "lcd_d16_pm0",
 318                                               "lcd_d17_pm1",
 319                                               "lcd_de_pj1",
 320                                               "lcd_hsync_pj3",
 321                                               "lcd_pclk_pb3",
 322                                               "lcd_vsync_pj4";
 323                                 nvidia,function = "displaya";
 324                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 325                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 326                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 327                         };
 328                         /*
 329                          * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
 330                          * today's display need DE, disable LCD_M1
 331                          */
 332                         lcd-m1-pw1 {
 333                                 nvidia,pins = "lcd_m1_pw1";
 334                                 nvidia,function = "rsvd3";
 335                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 336                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 337                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 338                         };
 339
 340                         /* Colibri MMC */
 341                         kb-row10-ps2 {
 342                                 nvidia,pins = "kb_row10_ps2";
 343                                 nvidia,function = "sdmmc2";
 344                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 345                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 346                         };
 347                         kb-row11-ps3 {
 348                                 nvidia,pins = "kb_row11_ps3",
 349                                               "kb_row12_ps4",
 350                                               "kb_row13_ps5",
 351                                               "kb_row14_ps6",
 352                                               "kb_row15_ps7";
 353                                 nvidia,function = "sdmmc2";
 354                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 355                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 356                         };
 357                         /* Colibri MMC_CD */
 358                         gmi-wp-n-pc7 {
 359                                 nvidia,pins = "gmi_wp_n_pc7";
 360                                 nvidia,function = "rsvd1";
 361                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 362                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 363                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 364                         };
 365                         /* Multiplexed and therefore disabled */
 366                         cam-mclk-pcc0 {
 367                                 nvidia,pins =   "cam_mclk_pcc0";
 368                                 nvidia,function = "vi_alt3";
 369                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 370                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 371                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 372                         };
 373                         cam-i2c-scl-pbb1 {
 374                                 nvidia,pins = "cam_i2c_scl_pbb1",
 375                                               "cam_i2c_sda_pbb2";
 376                                 nvidia,function = "rsvd3";
 377                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 378                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 379                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 380                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 381                         };
 382                         pbb0 {
 383                                 nvidia,pins = "pbb0",
 384                                               "pcc1";
 385                                 nvidia,function = "rsvd2";
 386                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 387                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 388                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 389                         };
 390                         pbb3 {
 391                                 nvidia,pins = "pbb3";
 392                                 nvidia,function = "displayb";
 393                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 394                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 395                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 396                         };
 397
 398                         /* Colibri nRESET_OUT */
 399                         gmi-rst-n-pi4 {
 400                                 nvidia,pins = "gmi_rst_n_pi4";
 401                                 nvidia,function = "gmi";
 402                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 403                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 404                         };
 405
 406                         /*
 407                          * Colibri Parallel Camera (Optional)
 408                          * pins multiplexed with others and therefore disabled
 409                          */
 410                         vi-vsync-pd6 {
 411                                 nvidia,pins = "vi_d0_pt4",
 412                                               "vi_d1_pd5",
 413                                               "vi_d2_pl0",
 414                                               "vi_d3_pl1",
 415                                               "vi_d4_pl2",
 416                                               "vi_d5_pl3",
 417                                               "vi_d6_pl4",
 418                                               "vi_d7_pl5",
 419                                               "vi_d8_pl6",
 420                                               "vi_d9_pl7",
 421                                               "vi_d10_pt2",
 422                                               "vi_d11_pt3",
 423                                               "vi_hsync_pd7",
 424                                               "vi_mclk_pt1",
 425                                               "vi_pclk_pt0",
 426                                               "vi_vsync_pd6";
 427                                 nvidia,function = "vi";
 428                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 429                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 430                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 431                         };
 432
 433                         /* Colibri PWM<B> */
 434                         sdmmc3-dat2-pb5 {
 435                                 nvidia,pins = "sdmmc3_dat2_pb5";
 436                                 nvidia,function = "pwm1";
 437                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 438                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 439                         };
 440
 441                         /* Colibri PWM<C> */
 442                         sdmmc3-clk-pa6 {
 443                                 nvidia,pins = "sdmmc3_clk_pa6";
 444                                 nvidia,function = "pwm2";
 445                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 446                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 447                         };
 448
 449                         /* Colibri PWM<D> */
 450                         sdmmc3-cmd-pa7 {
 451                                 nvidia,pins = "sdmmc3_cmd_pa7";
 452                                 nvidia,function = "pwm3";
 453                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 454                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 455                         };
 456
 457                         /* Colibri SSP */
 458                         ulpi-clk-py0 {
 459                                 nvidia,pins = "ulpi_clk_py0",
 460                                               "ulpi_dir_py1",
 461                                               "ulpi_nxt_py2",
 462                                               "ulpi_stp_py3";
 463                                 nvidia,function = "spi1";
 464                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 465                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 466                         };
 467                         /* Multiplexed SSPFRM, SSPTXD and therefore disabled */
 468                         sdmmc3-dat6-pd3 {
 469                                 nvidia,pins = "sdmmc3_dat6_pd3",
 470                                               "sdmmc3_dat7_pd4";
 471                                 nvidia,function = "spdif";
 472                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 473                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 474                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 475                         };
 476
 477                         /* Colibri UART-A */
 478                         ulpi-data0 {
 479                                 nvidia,pins = "ulpi_data0_po1",
 480                                               "ulpi_data1_po2",
 481                                               "ulpi_data2_po3",
 482                                               "ulpi_data3_po4",
 483                                               "ulpi_data4_po5",
 484                                               "ulpi_data5_po6",
 485                                               "ulpi_data6_po7",
 486                                               "ulpi_data7_po0";
 487                                 nvidia,function = "uarta";
 488                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 489                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 490                         };
 491
 492                         /* Colibri UART-B */
 493                         gmi-a16-pj7 {
 494                                 nvidia,pins = "gmi_a16_pj7",
 495                                               "gmi_a17_pb0",
 496                                               "gmi_a18_pb1",
 497                                               "gmi_a19_pk7";
 498                                 nvidia,function = "uartd";
 499                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 500                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 501                         };
 502
 503                         /* Colibri UART-C */
 504                         uart2-rxd {
 505                                 nvidia,pins = "uart2_rxd_pc3",
 506                                               "uart2_txd_pc2";
 507                                 nvidia,function = "uartb";
 508                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 509                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 510                         };
 511
 512                         /* Colibri USBC_DET */
 513                         spdif-out-pk5 {
 514                                 nvidia,pins =   "spdif_out_pk5";
 515                                 nvidia,function = "rsvd2";
 516                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 517                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 518                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 519                         };
 520
 521                         /* Colibri USBH_PEN */
 522                         spi2-cs1-n-pw2 {
 523                                 nvidia,pins = "spi2_cs1_n_pw2";
 524                                 nvidia,function = "spi2_alt";
 525                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 526                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 527                         };
 528
 529                         /* Colibri USBH_OC */
 530                         spi2-cs2-n-pw3, {
 531                                 nvidia,pins = "spi2_cs2_n_pw3";
 532                                 nvidia,function = "spi2_alt";
 533                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 534                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 535                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 536                         };
 537
 538                         /* Colibri VGA not supported and therefore disabled */
 539                         crt-hsync-pv6 {
 540                                 nvidia,pins = "crt_hsync_pv6",
 541                                               "crt_vsync_pv7";
 542                                 nvidia,function = "rsvd2";
 543                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 544                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 545                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 546                         };
 547
 548                         /* eMMC (On-module) */
 549                         sdmmc4-clk-pcc4 {
 550                                 nvidia,pins = "sdmmc4_clk_pcc4",
 551                                               "sdmmc4_cmd_pt7",
 552                                               "sdmmc4_rst_n_pcc3";
 553                                 nvidia,function = "sdmmc4";
 554                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 555                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 556                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 557                         };
 558                         sdmmc4-dat0-paa0 {
 559                                 nvidia,pins = "sdmmc4_dat0_paa0",
 560                                               "sdmmc4_dat1_paa1",
 561                                               "sdmmc4_dat2_paa2",
 562                                               "sdmmc4_dat3_paa3",
 563                                               "sdmmc4_dat4_paa4",
 564                                               "sdmmc4_dat5_paa5",
 565                                               "sdmmc4_dat6_paa6",
 566                                               "sdmmc4_dat7_paa7";
 567                                 nvidia,function = "sdmmc4";
 568                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 569                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 570                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 571                         };
 572
 573                         /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
 574                         pex-l0-rst-n-pdd1 {
 575                                 nvidia,pins = "pex_l0_rst_n_pdd1",
 576                                               "pex_wake_n_pdd3";
 577                                 nvidia,function = "rsvd3";
 578                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 579                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 580                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 581                         };
 582                         /* LAN_V_BUS, LAN_RESET# (On-module) */
 583                         pex-l0-clkreq-n-pdd2 {
 584                                 nvidia,pins = "pex_l0_clkreq_n_pdd2",
 585                                               "pex_l0_prsnt_n_pdd0";
 586                                 nvidia,function = "rsvd3";
 587                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 588                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 589                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 590                         };
 591
 592                         /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
 593                         pex-l2-rst-n-pcc6 {
 594                                 nvidia,pins = "pex_l2_rst_n_pcc6",
 595                                               "pex_l2_prsnt_n_pdd7";
 596                                 nvidia,function = "rsvd3";
 597                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 598                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 599                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 600                         };
 601
 602                         /* Not connected and therefore disabled */
 603                         clk1-req-pee2 {
 604                                 nvidia,pins = "clk1_req_pee2",
 605                                               "pex_l1_prsnt_n_pdd4";
 606                                 nvidia,function = "rsvd3";
 607                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 608                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 609                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 610                         };
 611                         clk2-req-pcc5 {
 612                                 nvidia,pins = "clk2_req_pcc5",
 613                                               "clk3_out_pee0",
 614                                               "clk3_req_pee1",
 615                                               "clk_32k_out_pa0",
 616                                               "hdmi_cec_pee3",
 617                                               "sys_clk_req_pz5";
 618                                 nvidia,function = "rsvd2";
 619                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 620                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 621                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 622                         };
 623                         gmi-dqs-pi2 {
 624                                 nvidia,pins = "gmi_dqs_pi2",
 625                                               "kb_col2_pq2",
 626                                               "kb_col3_pq3",
 627                                               "kb_col4_pq4",
 628                                               "kb_col5_pq5",
 629                                               "kb_row4_pr4";
 630                                 nvidia,function = "rsvd4";
 631                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 632                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 633                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 634                         };
 635                         kb-col0-pq0 {
 636                                 nvidia,pins = "kb_col0_pq0",
 637                                               "kb_col1_pq1",
 638                                               "kb_col6_pq6",
 639                                               "kb_col7_pq7",
 640                                               "kb_row5_pr5",
 641                                               "kb_row6_pr6",
 642                                               "kb_row7_pr7",
 643                                               "kb_row9_ps1";
 644                                 nvidia,function = "kbc";
 645                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 646                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 647                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 648                         };
 649                         kb-row0-pr0 {
 650                                 nvidia,pins = "kb_row0_pr0",
 651                                               "kb_row1_pr1",
 652                                               "kb_row2_pr2",
 653                                               "kb_row3_pr3";
 654                                 nvidia,function = "rsvd3";
 655                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 656                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 657                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 658                         };
 659                         lcd-pwr2-pc6 {
 660                                 nvidia,pins = "lcd_pwr2_pc6";
 661                                 nvidia,function = "hdcp";
 662                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 663                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 664                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 665                         };
 666
 667                         /* Power I2C (On-module) */
 668                         pwr-i2c-scl-pz6 {
 669                                 nvidia,pins = "pwr_i2c_scl_pz6",
 670                                               "pwr_i2c_sda_pz7";
 671                                 nvidia,function = "i2cpwr";
 672                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 673                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 674                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 675                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 676                         };
 677
 678                         /*
 679                          * THERMD_ALERT#, unlatched I2C address pin of LM95245
 680                          * temperature sensor therefore requires disabling for
 681                          * now
 682                          */
 683                         lcd-dc1-pd2 {
 684                                 nvidia,pins = "lcd_dc1_pd2";
 685                                 nvidia,function = "rsvd3";
 686                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 687                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 688                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 689                         };
 690
 691                         /* TOUCH_PEN_INT# (On-module) */
 692                         pv0 {
 693                                 nvidia,pins = "pv0";
 694                                 nvidia,function = "rsvd1";
 695                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 696                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 697                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 698                         };
 699                 };
 700         };
 701
 702         serial@70006040 {
 703                 compatible = "nvidia,tegra30-hsuart";
 704         };
 705
 706         serial@70006300 {
 707                 compatible = "nvidia,tegra30-hsuart";
 708         };
 709
 710         hdmi_ddc: i2c@7000c700 {
 711                 clock-frequency = <10000>;
 712         };
 713
 714         /*
 715          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 716          * touch screen controller (On-module)
 717          */
 718         i2c@7000d000 {
 719                 status = "okay";
 720                 clock-frequency = <100000>;
 721
 722                 /* SGTL5000 audio codec */
 723                 sgtl5000: codec@a {
 724                         compatible = "fsl,sgtl5000";
 725                         reg = <0x0a>;
 726                         VDDA-supply = <&reg_module_3v3_audio>;
 727                         VDDD-supply = <&reg_1v8_vio>;
 728                         VDDIO-supply = <&reg_module_3v3>;
 729                         clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
 730                 };
 731
 732                 pmic: pmic@2d {
 733                         compatible = "ti,tps65911";
 734                         reg = <0x2d>;
 735
 736                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 737                         #interrupt-cells = <2>;
 738                         interrupt-controller;
 739
 740                         ti,system-power-controller;
 741
 742                         #gpio-cells = <2>;
 743                         gpio-controller;
 744
 745                         vcc1-supply = <&reg_module_3v3>;
 746                         vcc2-supply = <&reg_module_3v3>;
 747                         vcc3-supply = <&reg_1v8_vio>;
 748                         vcc4-supply = <&reg_module_3v3>;
 749                         vcc5-supply = <&reg_module_3v3>;
 750                         vcc6-supply = <&reg_1v8_vio>;
 751                         vcc7-supply = <&reg_5v0_charge_pump>;
 752                         vccio-supply = <&reg_module_3v3>;
 753
 754                         regulators {
 755                                 vdd1_reg: vdd1 {
 756                                         regulator-name = "+V1.35_VDDIO_DDR";
 757                                         regulator-min-microvolt = <1350000>;
 758                                         regulator-max-microvolt = <1350000>;
 759                                         regulator-always-on;
 760                                 };
 761
 762                                 /* SW2: unused */
 763
 764                                 vddctrl_reg: vddctrl {
 765                                         regulator-name = "+V1.0_VDD_CPU";
 766                                         regulator-min-microvolt = <1150000>;
 767                                         regulator-max-microvolt = <1150000>;
 768                                         regulator-always-on;
 769                                 };
 770
 771                                 reg_1v8_vio: vio {
 772                                         regulator-name = "+V1.8";
 773                                         regulator-min-microvolt = <1800000>;
 774                                         regulator-max-microvolt = <1800000>;
 775                                         regulator-always-on;
 776                                 };
 777
 778                                 /* LDO1: unused */
 779
 780                                 /*
 781                                  * EN_+V3.3 switching via FET:
 782                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
 783                                  * see also +V3.3 fixed supply
 784                                  */
 785                                 ldo2_reg: ldo2 {
 786                                         regulator-name = "EN_+V3.3";
 787                                         regulator-min-microvolt = <3300000>;
 788                                         regulator-max-microvolt = <3300000>;
 789                                         regulator-always-on;
 790                                 };
 791
 792                                 /* LDO3: unused */
 793
 794                                 ldo4_reg: ldo4 {
 795                                         regulator-name = "+V1.2_VDD_RTC";
 796                                         regulator-min-microvolt = <1200000>;
 797                                         regulator-max-microvolt = <1200000>;
 798                                         regulator-always-on;
 799                                 };
 800
 801                                 /*
 802                                  * +V2.8_AVDD_VDAC:
 803                                  * only required for (unsupported) analog RGB
 804                                  */
 805                                 ldo5_reg: ldo5 {
 806                                         regulator-name = "+V2.8_AVDD_VDAC";
 807                                         regulator-min-microvolt = <2800000>;
 808                                         regulator-max-microvolt = <2800000>;
 809                                         regulator-always-on;
 810                                 };
 811
 812                                 /*
 813                                  * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
 814                                  * but LDO6 can't set voltage in 50mV
 815                                  * granularity
 816                                  */
 817                                 ldo6_reg: ldo6 {
 818                                         regulator-name = "+V1.05_AVDD_PLLE";
 819                                         regulator-min-microvolt = <1100000>;
 820                                         regulator-max-microvolt = <1100000>;
 821                                 };
 822
 823                                 ldo7_reg: ldo7 {
 824                                         regulator-name = "+V1.2_AVDD_PLL";
 825                                         regulator-min-microvolt = <1200000>;
 826                                         regulator-max-microvolt = <1200000>;
 827                                         regulator-always-on;
 828                                 };
 829
 830                                 ldo8_reg: ldo8 {
 831                                         regulator-name = "+V1.0_VDD_DDR_HS";
 832                                         regulator-min-microvolt = <1000000>;
 833                                         regulator-max-microvolt = <1000000>;
 834                                         regulator-always-on;
 835                                 };
 836                         };
 837                 };
 838
 839                 /* STMPE811 touch screen controller */
 840                 touchscreen@41 {
 841                         compatible = "st,stmpe811";
 842                         reg = <0x41>;
 843                         irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 844                         interrupt-controller;
 845                         id = <0>;
 846                         blocks = <0x5>;
 847                         irq-trigger = <0x1>;
 848
 849                         stmpe_touchscreen {
 850                                 compatible = "st,stmpe-ts";
 851                                 /* 3.25 MHz ADC clock speed */
 852                                 st,adc-freq = <1>;
 853                                 /* 8 sample average control */
 854                                 st,ave-ctrl = <3>;
 855                                 /* 7 length fractional part in z */
 856                                 st,fraction-z = <7>;
 857                                 /*
 858                                  * 50 mA typical 80 mA max touchscreen drivers
 859                                  * current limit value
 860                                  */
 861                                 st,i-drive = <1>;
 862                                 /* 12-bit ADC */
 863                                 st,mod-12b = <1>;
 864                                 /* internal ADC reference */
 865                                 st,ref-sel = <0>;
 866                                 /* ADC converstion time: 80 clocks */
 867                                 st,sample-time = <4>;
 868                                 /* 1 ms panel driver settling time */
 869                                 st,settling = <3>;
 870                                 /* 5 ms touch detect interrupt delay */
 871                                 st,touch-det-delay = <5>;
 872                         };
 873                 };
 874
 875                 /*
 876                  * LM95245 temperature sensor
 877                  * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
 878                  */
 879                 temp-sensor@4c {
 880                         compatible = "national,lm95245";
 881                         reg = <0x4c>;
 882                 };
 883
 884                 /* SW: +V1.2_VDD_CORE */
 885                 regulator@60 {
 886                         compatible = "ti,tps62362";
 887                         reg = <0x60>;
 888
 889                         regulator-name = "tps62362-vout";
 890                         regulator-min-microvolt = <900000>;
 891                         regulator-max-microvolt = <1400000>;
 892                         regulator-boot-on;
 893                         regulator-always-on;
 894                         ti,vsel0-state-low;
 895                         /* VSEL1: EN_CORE_DVFS_N low for DVFS */
 896                         ti,vsel1-state-low;
 897                 };
 898         };
 899
 900         pmc@7000e400 {
 901                 nvidia,invert-interrupt;
 902                 nvidia,suspend-mode = <1>;
 903                 nvidia,cpu-pwr-good-time = <5000>;
 904                 nvidia,cpu-pwr-off-time = <5000>;
 905                 nvidia,core-pwr-good-time = <3845 3845>;
 906                 nvidia,core-pwr-off-time = <0>;
 907                 nvidia,core-power-req-active-high;
 908                 nvidia,sys-clock-req-active-high;
 909
 910                 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
 911                 i2c-thermtrip {
 912                         nvidia,i2c-controller-id = <4>;
 913                         nvidia,bus-addr = <0x2d>;
 914                         nvidia,reg-addr = <0x3f>;
 915                         nvidia,reg-data = <0x1>;
 916                 };
 917         };
 918
 919         hda@70030000 {
 920                 status = "okay";
 921         };
 922
 923         ahub@70080000 {
 924                 i2s@70080500 {
 925                         status = "okay";
 926                 };
 927         };
 928
 929         /* eMMC */
 930         sdhci@78000600 {
 931                 status = "okay";
 932                 bus-width = <8>;
 933                 non-removable;
 934                 vmmc-supply = <&reg_module_3v3>; /* VCC */
 935                 vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
 936                 mmc-ddr-1_8v;
 937         };
 938
 939         /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
 940         usb@7d004000 {
 941                 status = "okay";
 942                 #address-cells = <1>;
 943                 #size-cells = <0>;
 944
 945                 asix@1 {
 946                         reg = <1>;
 947                         local-mac-address = [00 00 00 00 00 00];
 948                 };
 949         };
 950
 951         usb-phy@7d004000 {
 952                 status = "okay";
 953                 vbus-supply = <&reg_lan_v_bus>;
 954         };
 955
 956         clk32k_in: xtal1 {
 957                 compatible = "fixed-clock";
 958                 #clock-cells = <0>;
 959                 clock-frequency = <32768>;
 960         };
 961
 962         reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
 963                 compatible = "regulator-fixed";
 964                 regulator-name = "+V1.8_AVDD_HDMI_PLL";
 965                 regulator-min-microvolt = <1800000>;
 966                 regulator-max-microvolt = <1800000>;
 967                 enable-active-high;
 968                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 969                 vin-supply = <&reg_1v8_vio>;
 970         };
 971
 972         reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
 973                 compatible = "regulator-fixed";
 974                 regulator-name = "+V3.3_AVDD_HDMI";
 975                 regulator-min-microvolt = <3300000>;
 976                 regulator-max-microvolt = <3300000>;
 977                 enable-active-high;
 978                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 979                 vin-supply = <&reg_module_3v3>;
 980         };
 981
 982         reg_5v0_charge_pump: regulator-5v0-charge-pump {
 983                 compatible = "regulator-fixed";
 984                 regulator-name = "+V5.0";
 985                 regulator-min-microvolt = <5000000>;
 986                 regulator-max-microvolt = <5000000>;
 987                 regulator-always-on;
 988         };
 989
 990         reg_lan_v_bus: regulator-lan-v-bus {
 991                 compatible = "regulator-fixed";
 992                 regulator-name = "LAN_V_BUS";
 993                 regulator-min-microvolt = <5000000>;
 994                 regulator-max-microvolt = <5000000>;
 995                 enable-active-high;
 996                 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
 997         };
 998
 999         reg_module_3v3: regulator-module-3v3 {
1000                 compatible = "regulator-fixed";
1001                 regulator-name = "+V3.3";
1002                 regulator-min-microvolt = <3300000>;
1003                 regulator-max-microvolt = <3300000>;
1004                 regulator-always-on;
1005         };
1006
1007         reg_module_3v3_audio: regulator-module-3v3-audio {
1008                 compatible = "regulator-fixed";
1009                 regulator-name = "+V3.3_AUDIO_AVDD_S";
1010                 regulator-min-microvolt = <3300000>;
1011                 regulator-max-microvolt = <3300000>;
1012                 regulator-always-on;
1013         };
1014
1015         sound {
1016                 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
1017                              "nvidia,tegra-audio-sgtl5000";
1018                 nvidia,model = "Toradex Colibri T30";
1019                 nvidia,audio-routing =
1020                         "Headphone Jack", "HP_OUT",
1021                         "LINE_IN", "Line In Jack",
1022                         "MIC_IN", "Mic Jack";
1023                 nvidia,i2s-controller = <&tegra_i2s2>;
1024                 nvidia,audio-codec = <&sgtl5000>;
1025                 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1026                          <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1027                          <&tegra_car TEGRA30_CLK_EXTERN1>;
1028                 clock-names = "pll_a", "pll_a_out0", "mclk";
1029         };
1030 };
1031
1032 &gpio {
1033         lan-reset-n {
1034                 gpio-hog;
1035                 gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
1036                 output-high;
1037                 line-name = "LAN_RESET#";
1038         };
1039 };