arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/clock/tegra20-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra20";
  10         interrupt-parent = <&intc>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17                 serial4 = &uarte;
  18         };
  19
  20         host1x@50000000 {
  21                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  22                 reg = <0x50000000 0x00024000>;
  23                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  24                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  25                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  26                 resets = <&tegra_car 28>;
  27                 reset-names = "host1x";
  28
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31
  32                 ranges = <0x54000000 0x54000000 0x04000000>;
  33
  34                 mpe@54040000 {
  35                         compatible = "nvidia,tegra20-mpe";
  36                         reg = <0x54040000 0x00040000>;
  37                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  38                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  39                         resets = <&tegra_car 60>;
  40                         reset-names = "mpe";
  41                 };
  42
  43                 vi@54080000 {
  44                         compatible = "nvidia,tegra20-vi";
  45                         reg = <0x54080000 0x00040000>;
  46                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  47                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  48                         resets = <&tegra_car 20>;
  49                         reset-names = "vi";
  50                 };
  51
  52                 epp@540c0000 {
  53                         compatible = "nvidia,tegra20-epp";
  54                         reg = <0x540c0000 0x00040000>;
  55                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  56                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  57                         resets = <&tegra_car 19>;
  58                         reset-names = "epp";
  59                 };
  60
  61                 isp@54100000 {
  62                         compatible = "nvidia,tegra20-isp";
  63                         reg = <0x54100000 0x00040000>;
  64                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  65                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  66                         resets = <&tegra_car 23>;
  67                         reset-names = "isp";
  68                 };
  69
  70                 gr2d@54140000 {
  71                         compatible = "nvidia,tegra20-gr2d";
  72                         reg = <0x54140000 0x00040000>;
  73                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  74                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  75                         resets = <&tegra_car 21>;
  76                         reset-names = "2d";
  77                 };
  78
  79                 gr3d@54140000 {
  80                         compatible = "nvidia,tegra20-gr3d";
  81                         reg = <0x54140000 0x00040000>;
  82                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  83                         resets = <&tegra_car 24>;
  84                         reset-names = "3d";
  85                 };
  86
  87                 dc@54200000 {
  88                         compatible = "nvidia,tegra20-dc";
  89                         reg = <0x54200000 0x00040000>;
  90                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  91                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  92                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  93                         clock-names = "dc", "parent";
  94                         resets = <&tegra_car 27>;
  95                         reset-names = "dc";
  96
  97                         nvidia,head = <0>;
  98
  99                         rgb {
 100                                 status = "disabled";
 101                         };
 102                 };
 103
 104                 dc@54240000 {
 105                         compatible = "nvidia,tegra20-dc";
 106                         reg = <0x54240000 0x00040000>;
 107                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 109                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 110                         clock-names = "dc", "parent";
 111                         resets = <&tegra_car 26>;
 112                         reset-names = "dc";
 113
 114                         nvidia,head = <1>;
 115
 116                         rgb {
 117                                 status = "disabled";
 118                         };
 119                 };
 120
 121                 hdmi@54280000 {
 122                         compatible = "nvidia,tegra20-hdmi";
 123                         reg = <0x54280000 0x00040000>;
 124                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 125                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 126                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 127                         clock-names = "hdmi", "parent";
 128                         resets = <&tegra_car 51>;
 129                         reset-names = "hdmi";
 130                         status = "disabled";
 131                 };
 132
 133                 tvo@542c0000 {
 134                         compatible = "nvidia,tegra20-tvo";
 135                         reg = <0x542c0000 0x00040000>;
 136                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 138                         status = "disabled";
 139                 };
 140
 141                 dsi@542c0000 {
 142                         compatible = "nvidia,tegra20-dsi";
 143                         reg = <0x542c0000 0x00040000>;
 144                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 145                         resets = <&tegra_car 48>;
 146                         reset-names = "dsi";
 147                         status = "disabled";
 148                 };
 149         };
 150
 151         timer@50004600 {
 152                 compatible = "arm,cortex-a9-twd-timer";
 153                 reg = <0x50040600 0x20>;
 154                 interrupts = <GIC_PPI 13
 155                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 156                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 157         };
 158
 159         intc: interrupt-controller@50041000 {
 160                 compatible = "arm,cortex-a9-gic";
 161                 reg = <0x50041000 0x1000
 162                        0x50040100 0x0100>;
 163                 interrupt-controller;
 164                 #interrupt-cells = <3>;
 165         };
 166
 167         cache-controller@50043000 {
 168                 compatible = "arm,pl310-cache";
 169                 reg = <0x50043000 0x1000>;
 170                 arm,data-latency = <5 5 2>;
 171                 arm,tag-latency = <4 4 2>;
 172                 cache-unified;
 173                 cache-level = <2>;
 174         };
 175
 176         timer@60005000 {
 177                 compatible = "nvidia,tegra20-timer";
 178                 reg = <0x60005000 0x60>;
 179                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 184         };
 185
 186         tegra_car: clock@60006000 {
 187                 compatible = "nvidia,tegra20-car";
 188                 reg = <0x60006000 0x1000>;
 189                 #clock-cells = <1>;
 190                 #reset-cells = <1>;
 191         };
 192
 193         flow-controller@60007000 {
 194                 compatible = "nvidia,tegra20-flowctrl";
 195                 reg = <0x60007000 0x1000>;
 196         };
 197
 198         apbdma: dma@6000a000 {
 199                 compatible = "nvidia,tegra20-apbdma";
 200                 reg = <0x6000a000 0x1200>;
 201                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 218                 resets = <&tegra_car 34>;
 219                 reset-names = "dma";
 220                 #dma-cells = <1>;
 221         };
 222
 223         ahb@6000c004 {
 224                 compatible = "nvidia,tegra20-ahb";
 225                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 226         };
 227
 228         gpio: gpio@6000d000 {
 229                 compatible = "nvidia,tegra20-gpio";
 230                 reg = <0x6000d000 0x1000>;
 231                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 238                 #gpio-cells = <2>;
 239                 gpio-controller;
 240                 #interrupt-cells = <2>;
 241                 interrupt-controller;
 242         };
 243
 244         apbmisc@70000800 {
 245                 compatible = "nvidia,tegra20-apbmisc";
 246                 reg = <0x70000800 0x64   /* Chip revision */
 247                        0x70000008 0x04>; /* Strapping options */
 248         };
 249
 250         pinmux: pinmux@70000014 {
 251                 compatible = "nvidia,tegra20-pinmux";
 252                 reg = <0x70000014 0x10   /* Tri-state registers */
 253                        0x70000080 0x20   /* Mux registers */
 254                        0x700000a0 0x14   /* Pull-up/down registers */
 255                        0x70000868 0xa8>; /* Pad control registers */
 256         };
 257
 258         das@70000c00 {
 259                 compatible = "nvidia,tegra20-das";
 260                 reg = <0x70000c00 0x80>;
 261         };
 262
 263         tegra_ac97: ac97@70002000 {
 264                 compatible = "nvidia,tegra20-ac97";
 265                 reg = <0x70002000 0x200>;
 266                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 268                 resets = <&tegra_car 3>;
 269                 reset-names = "ac97";
 270                 dmas = <&apbdma 12>, <&apbdma 12>;
 271                 dma-names = "rx", "tx";
 272                 status = "disabled";
 273         };
 274
 275         tegra_i2s1: i2s@70002800 {
 276                 compatible = "nvidia,tegra20-i2s";
 277                 reg = <0x70002800 0x200>;
 278                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 280                 resets = <&tegra_car 11>;
 281                 reset-names = "i2s";
 282                 dmas = <&apbdma 2>, <&apbdma 2>;
 283                 dma-names = "rx", "tx";
 284                 status = "disabled";
 285         };
 286
 287         tegra_i2s2: i2s@70002a00 {
 288                 compatible = "nvidia,tegra20-i2s";
 289                 reg = <0x70002a00 0x200>;
 290                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 291                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 292                 resets = <&tegra_car 18>;
 293                 reset-names = "i2s";
 294                 dmas = <&apbdma 1>, <&apbdma 1>;
 295                 dma-names = "rx", "tx";
 296                 status = "disabled";
 297         };
 298
 299         /*
 300          * There are two serial driver i.e. 8250 based simple serial
 301          * driver and APB DMA based serial driver for higher baudrate
 302          * and performace. To enable the 8250 based driver, the compatible
 303          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 304          * driver, the comptible is "nvidia,tegra20-hsuart".
 305          */
 306         uarta: serial@70006000 {
 307                 compatible = "nvidia,tegra20-uart";
 308                 reg = <0x70006000 0x40>;
 309                 reg-shift = <2>;
 310                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 311                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 312                 resets = <&tegra_car 6>;
 313                 reset-names = "serial";
 314                 dmas = <&apbdma 8>, <&apbdma 8>;
 315                 dma-names = "rx", "tx";
 316                 status = "disabled";
 317         };
 318
 319         uartb: serial@70006040 {
 320                 compatible = "nvidia,tegra20-uart";
 321                 reg = <0x70006040 0x40>;
 322                 reg-shift = <2>;
 323                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 325                 resets = <&tegra_car 7>;
 326                 reset-names = "serial";
 327                 dmas = <&apbdma 9>, <&apbdma 9>;
 328                 dma-names = "rx", "tx";
 329                 status = "disabled";
 330         };
 331
 332         uartc: serial@70006200 {
 333                 compatible = "nvidia,tegra20-uart";
 334                 reg = <0x70006200 0x100>;
 335                 reg-shift = <2>;
 336                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 337                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 338                 resets = <&tegra_car 55>;
 339                 reset-names = "serial";
 340                 dmas = <&apbdma 10>, <&apbdma 10>;
 341                 dma-names = "rx", "tx";
 342                 status = "disabled";
 343         };
 344
 345         uartd: serial@70006300 {
 346                 compatible = "nvidia,tegra20-uart";
 347                 reg = <0x70006300 0x100>;
 348                 reg-shift = <2>;
 349                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 350                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 351                 resets = <&tegra_car 65>;
 352                 reset-names = "serial";
 353                 dmas = <&apbdma 19>, <&apbdma 19>;
 354                 dma-names = "rx", "tx";
 355                 status = "disabled";
 356         };
 357
 358         uarte: serial@70006400 {
 359                 compatible = "nvidia,tegra20-uart";
 360                 reg = <0x70006400 0x100>;
 361                 reg-shift = <2>;
 362                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 364                 resets = <&tegra_car 66>;
 365                 reset-names = "serial";
 366                 dmas = <&apbdma 20>, <&apbdma 20>;
 367                 dma-names = "rx", "tx";
 368                 status = "disabled";
 369         };
 370
 371         pwm: pwm@7000a000 {
 372                 compatible = "nvidia,tegra20-pwm";
 373                 reg = <0x7000a000 0x100>;
 374                 #pwm-cells = <2>;
 375                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 376                 resets = <&tegra_car 17>;
 377                 reset-names = "pwm";
 378                 status = "disabled";
 379         };
 380
 381         rtc@7000e000 {
 382                 compatible = "nvidia,tegra20-rtc";
 383                 reg = <0x7000e000 0x100>;
 384                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 385                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 386         };
 387
 388         i2c@7000c000 {
 389                 compatible = "nvidia,tegra20-i2c";
 390                 reg = <0x7000c000 0x100>;
 391                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 395                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 396                 clock-names = "div-clk", "fast-clk";
 397                 resets = <&tegra_car 12>;
 398                 reset-names = "i2c";
 399                 dmas = <&apbdma 21>, <&apbdma 21>;
 400                 dma-names = "rx", "tx";
 401                 status = "disabled";
 402         };
 403
 404         spi@7000c380 {
 405                 compatible = "nvidia,tegra20-sflash";
 406                 reg = <0x7000c380 0x80>;
 407                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 411                 resets = <&tegra_car 43>;
 412                 reset-names = "spi";
 413                 dmas = <&apbdma 11>, <&apbdma 11>;
 414                 dma-names = "rx", "tx";
 415                 status = "disabled";
 416         };
 417
 418         i2c@7000c400 {
 419                 compatible = "nvidia,tegra20-i2c";
 420                 reg = <0x7000c400 0x100>;
 421                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 425                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 426                 clock-names = "div-clk", "fast-clk";
 427                 resets = <&tegra_car 54>;
 428                 reset-names = "i2c";
 429                 dmas = <&apbdma 22>, <&apbdma 22>;
 430                 dma-names = "rx", "tx";
 431                 status = "disabled";
 432         };
 433
 434         i2c@7000c500 {
 435                 compatible = "nvidia,tegra20-i2c";
 436                 reg = <0x7000c500 0x100>;
 437                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 441                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 442                 clock-names = "div-clk", "fast-clk";
 443                 resets = <&tegra_car 67>;
 444                 reset-names = "i2c";
 445                 dmas = <&apbdma 23>, <&apbdma 23>;
 446                 dma-names = "rx", "tx";
 447                 status = "disabled";
 448         };
 449
 450         i2c@7000d000 {
 451                 compatible = "nvidia,tegra20-i2c-dvc";
 452                 reg = <0x7000d000 0x200>;
 453                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 457                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 458                 clock-names = "div-clk", "fast-clk";
 459                 resets = <&tegra_car 47>;
 460                 reset-names = "i2c";
 461                 dmas = <&apbdma 24>, <&apbdma 24>;
 462                 dma-names = "rx", "tx";
 463                 status = "disabled";
 464         };
 465
 466         spi@7000d400 {
 467                 compatible = "nvidia,tegra20-slink";
 468                 reg = <0x7000d400 0x200>;
 469                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 473                 resets = <&tegra_car 41>;
 474                 reset-names = "spi";
 475                 dmas = <&apbdma 15>, <&apbdma 15>;
 476                 dma-names = "rx", "tx";
 477                 status = "disabled";
 478         };
 479
 480         spi@7000d600 {
 481                 compatible = "nvidia,tegra20-slink";
 482                 reg = <0x7000d600 0x200>;
 483                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 484                 #address-cells = <1>;
 485                 #size-cells = <0>;
 486                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 487                 resets = <&tegra_car 44>;
 488                 reset-names = "spi";
 489                 dmas = <&apbdma 16>, <&apbdma 16>;
 490                 dma-names = "rx", "tx";
 491                 status = "disabled";
 492         };
 493
 494         spi@7000d800 {
 495                 compatible = "nvidia,tegra20-slink";
 496                 reg = <0x7000d800 0x200>;
 497                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 501                 resets = <&tegra_car 46>;
 502                 reset-names = "spi";
 503                 dmas = <&apbdma 17>, <&apbdma 17>;
 504                 dma-names = "rx", "tx";
 505                 status = "disabled";
 506         };
 507
 508         spi@7000da00 {
 509                 compatible = "nvidia,tegra20-slink";
 510                 reg = <0x7000da00 0x200>;
 511                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 515                 resets = <&tegra_car 68>;
 516                 reset-names = "spi";
 517                 dmas = <&apbdma 18>, <&apbdma 18>;
 518                 dma-names = "rx", "tx";
 519                 status = "disabled";
 520         };
 521
 522         kbc@7000e200 {
 523                 compatible = "nvidia,tegra20-kbc";
 524                 reg = <0x7000e200 0x100>;
 525                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 526                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 527                 resets = <&tegra_car 36>;
 528                 reset-names = "kbc";
 529                 status = "disabled";
 530         };
 531
 532         pmc@7000e400 {
 533                 compatible = "nvidia,tegra20-pmc";
 534                 reg = <0x7000e400 0x400>;
 535                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 536                 clock-names = "pclk", "clk32k_in";
 537         };
 538
 539         memory-controller@7000f000 {
 540                 compatible = "nvidia,tegra20-mc";
 541                 reg = <0x7000f000 0x024
 542                        0x7000f03c 0x3c4>;
 543                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 544         };
 545
 546         iommu@7000f024 {
 547                 compatible = "nvidia,tegra20-gart";
 548                 reg = <0x7000f024 0x00000018    /* controller registers */
 549                        0x58000000 0x02000000>;  /* GART aperture */
 550         };
 551
 552         memory-controller@7000f400 {
 553                 compatible = "nvidia,tegra20-emc";
 554                 reg = <0x7000f400 0x200>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557         };
 558
 559         fuse@7000f800 {
 560                 compatible = "nvidia,tegra20-efuse";
 561                 reg = <0x7000F800 0x400>;
 562                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 563                 clock-names = "fuse";
 564                 resets = <&tegra_car 39>;
 565                 reset-names = "fuse";
 566         };
 567
 568         pcie-controller@80003000 {
 569                 compatible = "nvidia,tegra20-pcie";
 570                 device_type = "pci";
 571                 reg = <0x80003000 0x00000800   /* PADS registers */
 572                        0x80003800 0x00000200   /* AFI registers */
 573                        0x90000000 0x10000000>; /* configuration space */
 574                 reg-names = "pads", "afi", "cs";
 575                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 576                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 577                 interrupt-names = "intr", "msi";
 578
 579                 #interrupt-cells = <1>;
 580                 interrupt-map-mask = <0 0 0 0>;
 581                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 582
 583                 bus-range = <0x00 0xff>;
 584                 #address-cells = <3>;
 585                 #size-cells = <2>;
 586
 587                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 588                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 589                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 590                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 591                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 592
 593                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 594                          <&tegra_car TEGRA20_CLK_AFI>,
 595                          <&tegra_car TEGRA20_CLK_PLL_E>;
 596                 clock-names = "pex", "afi", "pll_e";
 597                 resets = <&tegra_car 70>,
 598                          <&tegra_car 72>,
 599                          <&tegra_car 74>;
 600                 reset-names = "pex", "afi", "pcie_x";
 601                 status = "disabled";
 602
 603                 pci@1,0 {
 604                         device_type = "pci";
 605                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 606                         reg = <0x000800 0 0 0 0>;
 607                         status = "disabled";
 608
 609                         #address-cells = <3>;
 610                         #size-cells = <2>;
 611                         ranges;
 612
 613                         nvidia,num-lanes = <2>;
 614                 };
 615
 616                 pci@2,0 {
 617                         device_type = "pci";
 618                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 619                         reg = <0x001000 0 0 0 0>;
 620                         status = "disabled";
 621
 622                         #address-cells = <3>;
 623                         #size-cells = <2>;
 624                         ranges;
 625
 626                         nvidia,num-lanes = <2>;
 627                 };
 628         };
 629
 630         usb@c5000000 {
 631                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 632                 reg = <0xc5000000 0x4000>;
 633                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 634                 phy_type = "utmi";
 635                 nvidia,has-legacy-mode;
 636                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 637                 resets = <&tegra_car 22>;
 638                 reset-names = "usb";
 639                 nvidia,needs-double-reset;
 640                 nvidia,phy = <&phy1>;
 641                 status = "disabled";
 642         };
 643
 644         phy1: usb-phy@c5000000 {
 645                 compatible = "nvidia,tegra20-usb-phy";
 646                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 647                 phy_type = "utmi";
 648                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 649                          <&tegra_car TEGRA20_CLK_PLL_U>,
 650                          <&tegra_car TEGRA20_CLK_CLK_M>,
 651                          <&tegra_car TEGRA20_CLK_USBD>;
 652                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 653                 resets = <&tegra_car 22>, <&tegra_car 22>;
 654                 reset-names = "usb", "utmi-pads";
 655                 nvidia,has-legacy-mode;
 656                 nvidia,hssync-start-delay = <9>;
 657                 nvidia,idle-wait-delay = <17>;
 658                 nvidia,elastic-limit = <16>;
 659                 nvidia,term-range-adj = <6>;
 660                 nvidia,xcvr-setup = <9>;
 661                 nvidia,xcvr-lsfslew = <1>;
 662                 nvidia,xcvr-lsrslew = <1>;
 663                 nvidia,has-utmi-pad-registers;
 664                 status = "disabled";
 665         };
 666
 667         usb@c5004000 {
 668                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 669                 reg = <0xc5004000 0x4000>;
 670                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 671                 phy_type = "ulpi";
 672                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 673                 resets = <&tegra_car 58>;
 674                 reset-names = "usb";
 675                 nvidia,phy = <&phy2>;
 676                 status = "disabled";
 677         };
 678
 679         phy2: usb-phy@c5004000 {
 680                 compatible = "nvidia,tegra20-usb-phy";
 681                 reg = <0xc5004000 0x4000>;
 682                 phy_type = "ulpi";
 683                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 684                          <&tegra_car TEGRA20_CLK_PLL_U>,
 685                          <&tegra_car TEGRA20_CLK_CDEV2>;
 686                 clock-names = "reg", "pll_u", "ulpi-link";
 687                 resets = <&tegra_car 58>, <&tegra_car 22>;
 688                 reset-names = "usb", "utmi-pads";
 689                 status = "disabled";
 690         };
 691
 692         usb@c5008000 {
 693                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 694                 reg = <0xc5008000 0x4000>;
 695                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 696                 phy_type = "utmi";
 697                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 698                 resets = <&tegra_car 59>;
 699                 reset-names = "usb";
 700                 nvidia,phy = <&phy3>;
 701                 status = "disabled";
 702         };
 703
 704         phy3: usb-phy@c5008000 {
 705                 compatible = "nvidia,tegra20-usb-phy";
 706                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 707                 phy_type = "utmi";
 708                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 709                          <&tegra_car TEGRA20_CLK_PLL_U>,
 710                          <&tegra_car TEGRA20_CLK_CLK_M>,
 711                          <&tegra_car TEGRA20_CLK_USBD>;
 712                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 713                 resets = <&tegra_car 59>, <&tegra_car 22>;
 714                 reset-names = "usb", "utmi-pads";
 715                 nvidia,hssync-start-delay = <9>;
 716                 nvidia,idle-wait-delay = <17>;
 717                 nvidia,elastic-limit = <16>;
 718                 nvidia,term-range-adj = <6>;
 719                 nvidia,xcvr-setup = <9>;
 720                 nvidia,xcvr-lsfslew = <2>;
 721                 nvidia,xcvr-lsrslew = <2>;
 722                 status = "disabled";
 723         };
 724
 725         sdhci@c8000000 {
 726                 compatible = "nvidia,tegra20-sdhci";
 727                 reg = <0xc8000000 0x200>;
 728                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 730                 resets = <&tegra_car 14>;
 731                 reset-names = "sdhci";
 732                 status = "disabled";
 733         };
 734
 735         sdhci@c8000200 {
 736                 compatible = "nvidia,tegra20-sdhci";
 737                 reg = <0xc8000200 0x200>;
 738                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 740                 resets = <&tegra_car 9>;
 741                 reset-names = "sdhci";
 742                 status = "disabled";
 743         };
 744
 745         sdhci@c8000400 {
 746                 compatible = "nvidia,tegra20-sdhci";
 747                 reg = <0xc8000400 0x200>;
 748                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 750                 resets = <&tegra_car 69>;
 751                 reset-names = "sdhci";
 752                 status = "disabled";
 753         };
 754
 755         sdhci@c8000600 {
 756                 compatible = "nvidia,tegra20-sdhci";
 757                 reg = <0xc8000600 0x200>;
 758                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 759                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 760                 resets = <&tegra_car 15>;
 761                 reset-names = "sdhci";
 762                 status = "disabled";
 763         };
 764
 765         cpus {
 766                 #address-cells = <1>;
 767                 #size-cells = <0>;
 768
 769                 cpu@0 {
 770                         device_type = "cpu";
 771                         compatible = "arm,cortex-a9";
 772                         reg = <0>;
 773                 };
 774
 775                 cpu@1 {
 776                         device_type = "cpu";
 777                         compatible = "arm,cortex-a9";
 778                         reg = <1>;
 779                 };
 780         };
 781
 782         pmu {
 783                 compatible = "arm,cortex-a9-pmu";
 784                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 785                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 786         };
 787 };