Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / tegra124.dtsi
1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/reset/tegra124-car.h>
7 #include <dt-bindings/thermal/tegra124-soctherm.h>
8
9 #include "skeleton.dtsi"
10
11 / {
12         compatible = "nvidia,tegra124";
13         interrupt-parent = <&lic>;
14         #address-cells = <2>;
15         #size-cells = <2>;
16
17         pcie-controller@0,01003000 {
18                 compatible = "nvidia,tegra124-pcie";
19                 device_type = "pci";
20                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
21                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
22                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23                 reg-names = "pads", "afi", "cs";
24                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26                 interrupt-names = "intr", "msi";
27
28                 #interrupt-cells = <1>;
29                 interrupt-map-mask = <0 0 0 0>;
30                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
31
32                 bus-range = <0x00 0xff>;
33                 #address-cells = <3>;
34                 #size-cells = <2>;
35
36                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
37                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
38                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
39                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
40                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
41
42                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43                          <&tegra_car TEGRA124_CLK_AFI>,
44                          <&tegra_car TEGRA124_CLK_PLL_E>,
45                          <&tegra_car TEGRA124_CLK_CML0>;
46                 clock-names = "pex", "afi", "pll_e", "cml";
47                 resets = <&tegra_car 70>,
48                          <&tegra_car 72>,
49                          <&tegra_car 74>;
50                 reset-names = "pex", "afi", "pcie_x";
51                 status = "disabled";
52
53                 pci@1,0 {
54                         device_type = "pci";
55                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56                         reg = <0x000800 0 0 0 0>;
57                         status = "disabled";
58
59                         #address-cells = <3>;
60                         #size-cells = <2>;
61                         ranges;
62
63                         nvidia,num-lanes = <2>;
64                 };
65
66                 pci@2,0 {
67                         device_type = "pci";
68                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
69                         reg = <0x001000 0 0 0 0>;
70                         status = "disabled";
71
72                         #address-cells = <3>;
73                         #size-cells = <2>;
74                         ranges;
75
76                         nvidia,num-lanes = <1>;
77                 };
78         };
79
80         host1x@0,50000000 {
81                 compatible = "nvidia,tegra124-host1x", "simple-bus";
82                 reg = <0x0 0x50000000 0x0 0x00034000>;
83                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
84                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
85                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
86                 resets = <&tegra_car 28>;
87                 reset-names = "host1x";
88
89                 #address-cells = <2>;
90                 #size-cells = <2>;
91
92                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
93
94                 dc@0,54200000 {
95                         compatible = "nvidia,tegra124-dc";
96                         reg = <0x0 0x54200000 0x0 0x00040000>;
97                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
98                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
99                                  <&tegra_car TEGRA124_CLK_PLL_P>;
100                         clock-names = "dc", "parent";
101                         resets = <&tegra_car 27>;
102                         reset-names = "dc";
103
104                         iommus = <&mc TEGRA_SWGROUP_DC>;
105
106                         nvidia,head = <0>;
107                 };
108
109                 dc@0,54240000 {
110                         compatible = "nvidia,tegra124-dc";
111                         reg = <0x0 0x54240000 0x0 0x00040000>;
112                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
113                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
114                                  <&tegra_car TEGRA124_CLK_PLL_P>;
115                         clock-names = "dc", "parent";
116                         resets = <&tegra_car 26>;
117                         reset-names = "dc";
118
119                         iommus = <&mc TEGRA_SWGROUP_DCB>;
120
121                         nvidia,head = <1>;
122                 };
123
124                 hdmi@0,54280000 {
125                         compatible = "nvidia,tegra124-hdmi";
126                         reg = <0x0 0x54280000 0x0 0x00040000>;
127                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
128                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
129                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
130                         clock-names = "hdmi", "parent";
131                         resets = <&tegra_car 51>;
132                         reset-names = "hdmi";
133                         status = "disabled";
134                 };
135
136                 sor@0,54540000 {
137                         compatible = "nvidia,tegra124-sor";
138                         reg = <0x0 0x54540000 0x0 0x00040000>;
139                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
140                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
141                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
142                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
143                                  <&tegra_car TEGRA124_CLK_CLK_M>;
144                         clock-names = "sor", "parent", "dp", "safe";
145                         resets = <&tegra_car 182>;
146                         reset-names = "sor";
147                         status = "disabled";
148                 };
149
150                 dpaux: dpaux@0,545c0000 {
151                         compatible = "nvidia,tegra124-dpaux";
152                         reg = <0x0 0x545c0000 0x0 0x00040000>;
153                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
154                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
155                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
156                         clock-names = "dpaux", "parent";
157                         resets = <&tegra_car 181>;
158                         reset-names = "dpaux";
159                         status = "disabled";
160                 };
161         };
162
163         gic: interrupt-controller@0,50041000 {
164                 compatible = "arm,cortex-a15-gic";
165                 #interrupt-cells = <3>;
166                 interrupt-controller;
167                 reg = <0x0 0x50041000 0x0 0x1000>,
168                       <0x0 0x50042000 0x0 0x1000>,
169                       <0x0 0x50044000 0x0 0x2000>,
170                       <0x0 0x50046000 0x0 0x2000>;
171                 interrupts = <GIC_PPI 9
172                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173                 interrupt-parent = <&gic>;
174         };
175
176         gpu@0,57000000 {
177                 compatible = "nvidia,gk20a";
178                 reg = <0x0 0x57000000 0x0 0x01000000>,
179                       <0x0 0x58000000 0x0 0x01000000>;
180                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
181                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
182                 interrupt-names = "stall", "nonstall";
183                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
184                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
185                 clock-names = "gpu", "pwr";
186                 resets = <&tegra_car 184>;
187                 reset-names = "gpu";
188
189                 iommus = <&mc TEGRA_SWGROUP_GPU>;
190
191                 status = "disabled";
192         };
193
194         lic: interrupt-controller@60004000 {
195                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
196                 reg = <0x0 0x60004000 0x0 0x100>,
197                       <0x0 0x60004100 0x0 0x100>,
198                       <0x0 0x60004200 0x0 0x100>,
199                       <0x0 0x60004300 0x0 0x100>,
200                       <0x0 0x60004400 0x0 0x100>;
201                 interrupt-controller;
202                 #interrupt-cells = <3>;
203                 interrupt-parent = <&gic>;
204         };
205
206         timer@0,60005000 {
207                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
208                 reg = <0x0 0x60005000 0x0 0x400>;
209                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
210                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
211                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
212                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
213                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
214                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
215                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
216         };
217
218         tegra_car: clock@0,60006000 {
219                 compatible = "nvidia,tegra124-car";
220                 reg = <0x0 0x60006000 0x0 0x1000>;
221                 #clock-cells = <1>;
222                 #reset-cells = <1>;
223                 nvidia,external-memory-controller = <&emc>;
224         };
225
226         flow-controller@0,60007000 {
227                 compatible = "nvidia,tegra124-flowctrl";
228                 reg = <0x0 0x60007000 0x0 0x1000>;
229         };
230
231         actmon@0,6000c800 {
232                 compatible = "nvidia,tegra124-actmon";
233                 reg = <0x0 0x6000c800 0x0 0x400>;
234                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
235                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
236                          <&tegra_car TEGRA124_CLK_EMC>;
237                 clock-names = "actmon", "emc";
238                 resets = <&tegra_car 119>;
239                 reset-names = "actmon";
240         };
241
242         gpio: gpio@0,6000d000 {
243                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
244                 reg = <0x0 0x6000d000 0x0 0x1000>;
245                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
246                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
247                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
248                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
249                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
250                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
251                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
252                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
253                 #gpio-cells = <2>;
254                 gpio-controller;
255                 #interrupt-cells = <2>;
256                 interrupt-controller;
257                 /*
258                 gpio-ranges = <&pinmux 0 0 251>;
259                 */
260         };
261
262         apbdma: dma@0,60020000 {
263                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
264                 reg = <0x0 0x60020000 0x0 0x1400>;
265                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
266                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
267                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
268                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
269                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
270                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
271                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
272                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
273                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
274                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
275                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
276                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
277                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
278                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
279                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
280                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
281                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
282                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
283                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
284                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
285                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
286                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
287                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
288                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
289                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
290                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
291                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
292                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
293                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
294                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
295                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
296                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
297                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
298                 resets = <&tegra_car 34>;
299                 reset-names = "dma";
300                 #dma-cells = <1>;
301         };
302
303         apbmisc@0,70000800 {
304                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
305                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
306                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
307         };
308
309         pinmux: pinmux@0,70000868 {
310                 compatible = "nvidia,tegra124-pinmux";
311                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
312                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
313                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
314         };
315
316         /*
317          * There are two serial driver i.e. 8250 based simple serial
318          * driver and APB DMA based serial driver for higher baudrate
319          * and performace. To enable the 8250 based driver, the compatible
320          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
321          * the APB DMA based serial driver, the compatible is
322          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
323          */
324         uarta: serial@0,70006000 {
325                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
326                 reg = <0x0 0x70006000 0x0 0x40>;
327                 reg-shift = <2>;
328                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
329                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
330                 resets = <&tegra_car 6>;
331                 reset-names = "serial";
332                 dmas = <&apbdma 8>, <&apbdma 8>;
333                 dma-names = "rx", "tx";
334                 status = "disabled";
335         };
336
337         uartb: serial@0,70006040 {
338                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
339                 reg = <0x0 0x70006040 0x0 0x40>;
340                 reg-shift = <2>;
341                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
342                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
343                 resets = <&tegra_car 7>;
344                 reset-names = "serial";
345                 dmas = <&apbdma 9>, <&apbdma 9>;
346                 dma-names = "rx", "tx";
347                 status = "disabled";
348         };
349
350         uartc: serial@0,70006200 {
351                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
352                 reg = <0x0 0x70006200 0x0 0x40>;
353                 reg-shift = <2>;
354                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
355                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
356                 resets = <&tegra_car 55>;
357                 reset-names = "serial";
358                 dmas = <&apbdma 10>, <&apbdma 10>;
359                 dma-names = "rx", "tx";
360                 status = "disabled";
361         };
362
363         uartd: serial@0,70006300 {
364                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
365                 reg = <0x0 0x70006300 0x0 0x40>;
366                 reg-shift = <2>;
367                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
368                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
369                 resets = <&tegra_car 65>;
370                 reset-names = "serial";
371                 dmas = <&apbdma 19>, <&apbdma 19>;
372                 dma-names = "rx", "tx";
373                 status = "disabled";
374         };
375
376         pwm: pwm@0,7000a000 {
377                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
378                 reg = <0x0 0x7000a000 0x0 0x100>;
379                 #pwm-cells = <2>;
380                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
381                 resets = <&tegra_car 17>;
382                 reset-names = "pwm";
383                 status = "disabled";
384         };
385
386         i2c@0,7000c000 {
387                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
388                 reg = <0x0 0x7000c000 0x0 0x100>;
389                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
390                 #address-cells = <1>;
391                 #size-cells = <0>;
392                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
393                 clock-names = "div-clk";
394                 resets = <&tegra_car 12>;
395                 reset-names = "i2c";
396                 dmas = <&apbdma 21>, <&apbdma 21>;
397                 dma-names = "rx", "tx";
398                 status = "disabled";
399         };
400
401         i2c@0,7000c400 {
402                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
403                 reg = <0x0 0x7000c400 0x0 0x100>;
404                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
405                 #address-cells = <1>;
406                 #size-cells = <0>;
407                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
408                 clock-names = "div-clk";
409                 resets = <&tegra_car 54>;
410                 reset-names = "i2c";
411                 dmas = <&apbdma 22>, <&apbdma 22>;
412                 dma-names = "rx", "tx";
413                 status = "disabled";
414         };
415
416         i2c@0,7000c500 {
417                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
418                 reg = <0x0 0x7000c500 0x0 0x100>;
419                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
420                 #address-cells = <1>;
421                 #size-cells = <0>;
422                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
423                 clock-names = "div-clk";
424                 resets = <&tegra_car 67>;
425                 reset-names = "i2c";
426                 dmas = <&apbdma 23>, <&apbdma 23>;
427                 dma-names = "rx", "tx";
428                 status = "disabled";
429         };
430
431         i2c@0,7000c700 {
432                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
433                 reg = <0x0 0x7000c700 0x0 0x100>;
434                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
435                 #address-cells = <1>;
436                 #size-cells = <0>;
437                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
438                 clock-names = "div-clk";
439                 resets = <&tegra_car 103>;
440                 reset-names = "i2c";
441                 dmas = <&apbdma 26>, <&apbdma 26>;
442                 dma-names = "rx", "tx";
443                 status = "disabled";
444         };
445
446         i2c@0,7000d000 {
447                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
448                 reg = <0x0 0x7000d000 0x0 0x100>;
449                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
450                 #address-cells = <1>;
451                 #size-cells = <0>;
452                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
453                 clock-names = "div-clk";
454                 resets = <&tegra_car 47>;
455                 reset-names = "i2c";
456                 dmas = <&apbdma 24>, <&apbdma 24>;
457                 dma-names = "rx", "tx";
458                 status = "disabled";
459         };
460
461         i2c@0,7000d100 {
462                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
463                 reg = <0x0 0x7000d100 0x0 0x100>;
464                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
465                 #address-cells = <1>;
466                 #size-cells = <0>;
467                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
468                 clock-names = "div-clk";
469                 resets = <&tegra_car 166>;
470                 reset-names = "i2c";
471                 dmas = <&apbdma 30>, <&apbdma 30>;
472                 dma-names = "rx", "tx";
473                 status = "disabled";
474         };
475
476         spi@0,7000d400 {
477                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
478                 reg = <0x0 0x7000d400 0x0 0x200>;
479                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
480                 #address-cells = <1>;
481                 #size-cells = <0>;
482                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
483                 clock-names = "spi";
484                 resets = <&tegra_car 41>;
485                 reset-names = "spi";
486                 dmas = <&apbdma 15>, <&apbdma 15>;
487                 dma-names = "rx", "tx";
488                 status = "disabled";
489         };
490
491         spi@0,7000d600 {
492                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
493                 reg = <0x0 0x7000d600 0x0 0x200>;
494                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
495                 #address-cells = <1>;
496                 #size-cells = <0>;
497                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
498                 clock-names = "spi";
499                 resets = <&tegra_car 44>;
500                 reset-names = "spi";
501                 dmas = <&apbdma 16>, <&apbdma 16>;
502                 dma-names = "rx", "tx";
503                 status = "disabled";
504         };
505
506         spi@0,7000d800 {
507                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
508                 reg = <0x0 0x7000d800 0x0 0x200>;
509                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
510                 #address-cells = <1>;
511                 #size-cells = <0>;
512                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
513                 clock-names = "spi";
514                 resets = <&tegra_car 46>;
515                 reset-names = "spi";
516                 dmas = <&apbdma 17>, <&apbdma 17>;
517                 dma-names = "rx", "tx";
518                 status = "disabled";
519         };
520
521         spi@0,7000da00 {
522                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
523                 reg = <0x0 0x7000da00 0x0 0x200>;
524                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
525                 #address-cells = <1>;
526                 #size-cells = <0>;
527                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
528                 clock-names = "spi";
529                 resets = <&tegra_car 68>;
530                 reset-names = "spi";
531                 dmas = <&apbdma 18>, <&apbdma 18>;
532                 dma-names = "rx", "tx";
533                 status = "disabled";
534         };
535
536         spi@0,7000dc00 {
537                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
538                 reg = <0x0 0x7000dc00 0x0 0x200>;
539                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
540                 #address-cells = <1>;
541                 #size-cells = <0>;
542                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
543                 clock-names = "spi";
544                 resets = <&tegra_car 104>;
545                 reset-names = "spi";
546                 dmas = <&apbdma 27>, <&apbdma 27>;
547                 dma-names = "rx", "tx";
548                 status = "disabled";
549         };
550
551         spi@0,7000de00 {
552                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
553                 reg = <0x0 0x7000de00 0x0 0x200>;
554                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
555                 #address-cells = <1>;
556                 #size-cells = <0>;
557                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
558                 clock-names = "spi";
559                 resets = <&tegra_car 105>;
560                 reset-names = "spi";
561                 dmas = <&apbdma 28>, <&apbdma 28>;
562                 dma-names = "rx", "tx";
563                 status = "disabled";
564         };
565
566         rtc@0,7000e000 {
567                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
568                 reg = <0x0 0x7000e000 0x0 0x100>;
569                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
570                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
571         };
572
573         pmc@0,7000e400 {
574                 compatible = "nvidia,tegra124-pmc";
575                 reg = <0x0 0x7000e400 0x0 0x400>;
576                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
577                 clock-names = "pclk", "clk32k_in";
578         };
579
580         fuse@0,7000f800 {
581                 compatible = "nvidia,tegra124-efuse";
582                 reg = <0x0 0x7000f800 0x0 0x400>;
583                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
584                 clock-names = "fuse";
585                 resets = <&tegra_car 39>;
586                 reset-names = "fuse";
587         };
588
589         mc: memory-controller@0,70019000 {
590                 compatible = "nvidia,tegra124-mc";
591                 reg = <0x0 0x70019000 0x0 0x1000>;
592                 clocks = <&tegra_car TEGRA124_CLK_MC>;
593                 clock-names = "mc";
594
595                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
596
597                 #iommu-cells = <1>;
598         };
599
600         emc: emc@0,7001b000 {
601                 compatible = "nvidia,tegra124-emc";
602                 reg = <0x0 0x7001b000 0x0 0x1000>;
603
604                 nvidia,memory-controller = <&mc>;
605         };
606
607         sata@0,70020000 {
608                 compatible = "nvidia,tegra124-ahci";
609                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
610                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
611                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
612                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
613                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
614                          <&tegra_car TEGRA124_CLK_CML1>,
615                          <&tegra_car TEGRA124_CLK_PLL_E>;
616                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
617                 resets = <&tegra_car 124>,
618                          <&tegra_car 123>,
619                          <&tegra_car 129>;
620                 reset-names = "sata", "sata-oob", "sata-cold";
621                 status = "disabled";
622         };
623
624         hda@0,70030000 {
625                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
626                 reg = <0x0 0x70030000 0x0 0x10000>;
627                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
628                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
629                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
630                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
631                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
632                 resets = <&tegra_car 125>, /* hda */
633                          <&tegra_car 128>, /* hda2hdmi */
634                          <&tegra_car 111>; /* hda2codec_2x */
635                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
636                 status = "disabled";
637         };
638
639         usb@0,70090000 {
640                 compatible = "nvidia,tegra124-xusb";
641                 reg = <0x0 0x70090000 0x0 0x8000>,
642                       <0x0 0x70098000 0x0 0x1000>,
643                       <0x0 0x70099000 0x0 0x1000>;
644                 reg-names = "hcd", "fpci", "ipfs";
645
646                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
647                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
648
649                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
650                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
651                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
652                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
653                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
654                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
655                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
656                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
657                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
658                          <&tegra_car TEGRA124_CLK_CLK_M>,
659                          <&tegra_car TEGRA124_CLK_PLL_E>;
660                 clock-names = "xusb_host", "xusb_host_src",
661                               "xusb_falcon_src", "xusb_ss",
662                               "xusb_ss_div2", "xusb_ss_src",
663                               "xusb_hs_src", "xusb_fs_src",
664                               "pll_u_480m", "clk_m", "pll_e";
665                 resets = <&tegra_car 89>, <&tegra_car 156>,
666                          <&tegra_car 143>;
667                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
668
669                 nvidia,xusb-padctl = <&padctl>;
670
671                 status = "disabled";
672         };
673
674         padctl: padctl@0,7009f000 {
675                 compatible = "nvidia,tegra124-xusb-padctl";
676                 reg = <0x0 0x7009f000 0x0 0x1000>;
677                 resets = <&tegra_car 142>;
678                 reset-names = "padctl";
679
680                 pads {
681                         usb2 {
682                                 status = "disabled";
683
684                                 lanes {
685                                         usb2-0 {
686                                                 status = "disabled";
687                                                 #phy-cells = <0>;
688                                         };
689
690                                         usb2-1 {
691                                                 status = "disabled";
692                                                 #phy-cells = <0>;
693                                         };
694
695                                         usb2-2 {
696                                                 status = "disabled";
697                                                 #phy-cells = <0>;
698                                         };
699                                 };
700                         };
701
702                         ulpi {
703                                 status = "disabled";
704
705                                 lanes {
706                                         ulpi-0 {
707                                                 status = "disabled";
708                                                 #phy-cells = <0>;
709                                         };
710                                 };
711                         };
712
713                         hsic {
714                                 status = "disabled";
715
716                                 lanes {
717                                         hsic-0 {
718                                                 status = "disabled";
719                                                 #phy-cells = <0>;
720                                         };
721
722                                         hsic-1 {
723                                                 status = "disabled";
724                                                 #phy-cells = <0>;
725                                         };
726                                 };
727                         };
728
729                         pcie {
730                                 status = "disabled";
731
732                                 lanes {
733                                         pcie-0 {
734                                                 status = "disabled";
735                                                 #phy-cells = <0>;
736                                         };
737
738                                         pcie-1 {
739                                                 status = "disabled";
740                                                 #phy-cells = <0>;
741                                         };
742
743                                         pcie-2 {
744                                                 status = "disabled";
745                                                 #phy-cells = <0>;
746                                         };
747
748                                         pcie-3 {
749                                                 status = "disabled";
750                                                 #phy-cells = <0>;
751                                         };
752
753                                         pcie-4 {
754                                                 status = "disabled";
755                                                 #phy-cells = <0>;
756                                         };
757                                 };
758                         };
759
760                         sata {
761                                 status = "disabled";
762
763                                 lanes {
764                                         sata-0 {
765                                                 status = "disabled";
766                                                 #phy-cells = <0>;
767                                         };
768                                 };
769                         };
770                 };
771
772                 ports {
773                         usb2-0 {
774                                 status = "disabled";
775                         };
776
777                         usb2-1 {
778                                 status = "disabled";
779                         };
780
781                         usb2-2 {
782                                 status = "disabled";
783                         };
784
785                         ulpi-0 {
786                                 status = "disabled";
787                         };
788
789                         hsic-0 {
790                                 status = "disabled";
791                         };
792
793                         hsic-1 {
794                                 status = "disabled";
795                         };
796
797                         usb3-0 {
798                                 status = "disabled";
799                         };
800
801                         usb3-1 {
802                                 status = "disabled";
803                         };
804                 };
805         };
806
807         sdhci@0,700b0000 {
808                 compatible = "nvidia,tegra124-sdhci";
809                 reg = <0x0 0x700b0000 0x0 0x200>;
810                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
811                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
812                 resets = <&tegra_car 14>;
813                 reset-names = "sdhci";
814                 status = "disabled";
815         };
816
817         sdhci@0,700b0200 {
818                 compatible = "nvidia,tegra124-sdhci";
819                 reg = <0x0 0x700b0200 0x0 0x200>;
820                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
821                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
822                 resets = <&tegra_car 9>;
823                 reset-names = "sdhci";
824                 status = "disabled";
825         };
826
827         sdhci@0,700b0400 {
828                 compatible = "nvidia,tegra124-sdhci";
829                 reg = <0x0 0x700b0400 0x0 0x200>;
830                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
831                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
832                 resets = <&tegra_car 69>;
833                 reset-names = "sdhci";
834                 status = "disabled";
835         };
836
837         sdhci@0,700b0600 {
838                 compatible = "nvidia,tegra124-sdhci";
839                 reg = <0x0 0x700b0600 0x0 0x200>;
840                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
841                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
842                 resets = <&tegra_car 15>;
843                 reset-names = "sdhci";
844                 status = "disabled";
845         };
846
847         soctherm: thermal-sensor@0,700e2000 {
848                 compatible = "nvidia,tegra124-soctherm";
849                 reg = <0x0 0x700e2000 0x0 0x1000>;
850                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
851                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
852                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
853                 clock-names = "tsensor", "soctherm";
854                 resets = <&tegra_car 78>;
855                 reset-names = "soctherm";
856                 #thermal-sensor-cells = <1>;
857         };
858
859         dfll: clock@0,70110000 {
860                 compatible = "nvidia,tegra124-dfll";
861                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
862                       <0 0x70110000 0 0x100>, /* I2C output control */
863                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
864                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
865                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
866                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
867                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
868                          <&tegra_car TEGRA124_CLK_I2C5>;
869                 clock-names = "soc", "ref", "i2c";
870                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
871                 reset-names = "dvco";
872                 #clock-cells = <0>;
873                 clock-output-names = "dfllCPU_out";
874                 nvidia,sample-rate = <12500>;
875                 nvidia,droop-ctrl = <0x00000f00>;
876                 nvidia,force-mode = <1>;
877                 nvidia,cf = <10>;
878                 nvidia,ci = <0>;
879                 nvidia,cg = <2>;
880                 status = "disabled";
881         };
882
883         ahub@0,70300000 {
884                 compatible = "nvidia,tegra124-ahub";
885                 reg = <0x0 0x70300000 0x0 0x200>,
886                       <0x0 0x70300800 0x0 0x800>,
887                       <0x0 0x70300200 0x0 0x600>;
888                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
889                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
890                          <&tegra_car TEGRA124_CLK_APBIF>;
891                 clock-names = "d_audio", "apbif";
892                 resets = <&tegra_car 106>, /* d_audio */
893                          <&tegra_car 107>, /* apbif */
894                          <&tegra_car 30>,  /* i2s0 */
895                          <&tegra_car 11>,  /* i2s1 */
896                          <&tegra_car 18>,  /* i2s2 */
897                          <&tegra_car 101>, /* i2s3 */
898                          <&tegra_car 102>, /* i2s4 */
899                          <&tegra_car 108>, /* dam0 */
900                          <&tegra_car 109>, /* dam1 */
901                          <&tegra_car 110>, /* dam2 */
902                          <&tegra_car 10>,  /* spdif */
903                          <&tegra_car 153>, /* amx */
904                          <&tegra_car 185>, /* amx1 */
905                          <&tegra_car 154>, /* adx */
906                          <&tegra_car 180>, /* adx1 */
907                          <&tegra_car 186>, /* afc0 */
908                          <&tegra_car 187>, /* afc1 */
909                          <&tegra_car 188>, /* afc2 */
910                          <&tegra_car 189>, /* afc3 */
911                          <&tegra_car 190>, /* afc4 */
912                          <&tegra_car 191>; /* afc5 */
913                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
914                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
915                               "spdif", "amx", "amx1", "adx", "adx1",
916                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
917                 dmas = <&apbdma 1>, <&apbdma 1>,
918                        <&apbdma 2>, <&apbdma 2>,
919                        <&apbdma 3>, <&apbdma 3>,
920                        <&apbdma 4>, <&apbdma 4>,
921                        <&apbdma 6>, <&apbdma 6>,
922                        <&apbdma 7>, <&apbdma 7>,
923                        <&apbdma 12>, <&apbdma 12>,
924                        <&apbdma 13>, <&apbdma 13>,
925                        <&apbdma 14>, <&apbdma 14>,
926                        <&apbdma 29>, <&apbdma 29>;
927                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
928                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
929                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
930                             "rx9", "tx9";
931                 ranges;
932                 #address-cells = <2>;
933                 #size-cells = <2>;
934
935                 tegra_i2s0: i2s@0,70301000 {
936                         compatible = "nvidia,tegra124-i2s";
937                         reg = <0x0 0x70301000 0x0 0x100>;
938                         nvidia,ahub-cif-ids = <4 4>;
939                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
940                         resets = <&tegra_car 30>;
941                         reset-names = "i2s";
942                         status = "disabled";
943                 };
944
945                 tegra_i2s1: i2s@0,70301100 {
946                         compatible = "nvidia,tegra124-i2s";
947                         reg = <0x0 0x70301100 0x0 0x100>;
948                         nvidia,ahub-cif-ids = <5 5>;
949                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
950                         resets = <&tegra_car 11>;
951                         reset-names = "i2s";
952                         status = "disabled";
953                 };
954
955                 tegra_i2s2: i2s@0,70301200 {
956                         compatible = "nvidia,tegra124-i2s";
957                         reg = <0x0 0x70301200 0x0 0x100>;
958                         nvidia,ahub-cif-ids = <6 6>;
959                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
960                         resets = <&tegra_car 18>;
961                         reset-names = "i2s";
962                         status = "disabled";
963                 };
964
965                 tegra_i2s3: i2s@0,70301300 {
966                         compatible = "nvidia,tegra124-i2s";
967                         reg = <0x0 0x70301300 0x0 0x100>;
968                         nvidia,ahub-cif-ids = <7 7>;
969                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
970                         resets = <&tegra_car 101>;
971                         reset-names = "i2s";
972                         status = "disabled";
973                 };
974
975                 tegra_i2s4: i2s@0,70301400 {
976                         compatible = "nvidia,tegra124-i2s";
977                         reg = <0x0 0x70301400 0x0 0x100>;
978                         nvidia,ahub-cif-ids = <8 8>;
979                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
980                         resets = <&tegra_car 102>;
981                         reset-names = "i2s";
982                         status = "disabled";
983                 };
984         };
985
986         usb@0,7d000000 {
987                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
988                 reg = <0x0 0x7d000000 0x0 0x4000>;
989                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
990                 phy_type = "utmi";
991                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
992                 resets = <&tegra_car 22>;
993                 reset-names = "usb";
994                 nvidia,phy = <&phy1>;
995                 status = "disabled";
996         };
997
998         phy1: usb-phy@0,7d000000 {
999                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1000                 reg = <0x0 0x7d000000 0x0 0x4000>,
1001                       <0x0 0x7d000000 0x0 0x4000>;
1002                 phy_type = "utmi";
1003                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1004                          <&tegra_car TEGRA124_CLK_PLL_U>,
1005                          <&tegra_car TEGRA124_CLK_USBD>;
1006                 clock-names = "reg", "pll_u", "utmi-pads";
1007                 resets = <&tegra_car 22>, <&tegra_car 22>;
1008                 reset-names = "usb", "utmi-pads";
1009                 nvidia,hssync-start-delay = <0>;
1010                 nvidia,idle-wait-delay = <17>;
1011                 nvidia,elastic-limit = <16>;
1012                 nvidia,term-range-adj = <6>;
1013                 nvidia,xcvr-setup = <9>;
1014                 nvidia,xcvr-lsfslew = <0>;
1015                 nvidia,xcvr-lsrslew = <3>;
1016                 nvidia,hssquelch-level = <2>;
1017                 nvidia,hsdiscon-level = <5>;
1018                 nvidia,xcvr-hsslew = <12>;
1019                 nvidia,has-utmi-pad-registers;
1020                 status = "disabled";
1021         };
1022
1023         usb@0,7d004000 {
1024                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1025                 reg = <0x0 0x7d004000 0x0 0x4000>;
1026                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1027                 phy_type = "utmi";
1028                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1029                 resets = <&tegra_car 58>;
1030                 reset-names = "usb";
1031                 nvidia,phy = <&phy2>;
1032                 status = "disabled";
1033         };
1034
1035         phy2: usb-phy@0,7d004000 {
1036                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1037                 reg = <0x0 0x7d004000 0x0 0x4000>,
1038                       <0x0 0x7d000000 0x0 0x4000>;
1039                 phy_type = "utmi";
1040                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1041                          <&tegra_car TEGRA124_CLK_PLL_U>,
1042                          <&tegra_car TEGRA124_CLK_USBD>;
1043                 clock-names = "reg", "pll_u", "utmi-pads";
1044                 resets = <&tegra_car 58>, <&tegra_car 22>;
1045                 reset-names = "usb", "utmi-pads";
1046                 nvidia,hssync-start-delay = <0>;
1047                 nvidia,idle-wait-delay = <17>;
1048                 nvidia,elastic-limit = <16>;
1049                 nvidia,term-range-adj = <6>;
1050                 nvidia,xcvr-setup = <9>;
1051                 nvidia,xcvr-lsfslew = <0>;
1052                 nvidia,xcvr-lsrslew = <3>;
1053                 nvidia,hssquelch-level = <2>;
1054                 nvidia,hsdiscon-level = <5>;
1055                 nvidia,xcvr-hsslew = <12>;
1056                 status = "disabled";
1057         };
1058
1059         usb@0,7d008000 {
1060                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1061                 reg = <0x0 0x7d008000 0x0 0x4000>;
1062                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1063                 phy_type = "utmi";
1064                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1065                 resets = <&tegra_car 59>;
1066                 reset-names = "usb";
1067                 nvidia,phy = <&phy3>;
1068                 status = "disabled";
1069         };
1070
1071         phy3: usb-phy@0,7d008000 {
1072                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1073                 reg = <0x0 0x7d008000 0x0 0x4000>,
1074                       <0x0 0x7d000000 0x0 0x4000>;
1075                 phy_type = "utmi";
1076                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1077                          <&tegra_car TEGRA124_CLK_PLL_U>,
1078                          <&tegra_car TEGRA124_CLK_USBD>;
1079                 clock-names = "reg", "pll_u", "utmi-pads";
1080                 resets = <&tegra_car 59>, <&tegra_car 22>;
1081                 reset-names = "usb", "utmi-pads";
1082                 nvidia,hssync-start-delay = <0>;
1083                 nvidia,idle-wait-delay = <17>;
1084                 nvidia,elastic-limit = <16>;
1085                 nvidia,term-range-adj = <6>;
1086                 nvidia,xcvr-setup = <9>;
1087                 nvidia,xcvr-lsfslew = <0>;
1088                 nvidia,xcvr-lsrslew = <3>;
1089                 nvidia,hssquelch-level = <2>;
1090                 nvidia,hsdiscon-level = <5>;
1091                 nvidia,xcvr-hsslew = <12>;
1092                 status = "disabled";
1093         };
1094
1095         cpus {
1096                 #address-cells = <1>;
1097                 #size-cells = <0>;
1098
1099                 cpu@0 {
1100                         device_type = "cpu";
1101                         compatible = "arm,cortex-a15";
1102                         reg = <0>;
1103
1104                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1105                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1106                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1107                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1108                                  <&dfll>;
1109                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1110                         /* FIXME: what's the actual transition time? */
1111                         clock-latency = <300000>;
1112                 };
1113
1114                 cpu@1 {
1115                         device_type = "cpu";
1116                         compatible = "arm,cortex-a15";
1117                         reg = <1>;
1118                 };
1119
1120                 cpu@2 {
1121                         device_type = "cpu";
1122                         compatible = "arm,cortex-a15";
1123                         reg = <2>;
1124                 };
1125
1126                 cpu@3 {
1127                         device_type = "cpu";
1128                         compatible = "arm,cortex-a15";
1129                         reg = <3>;
1130                 };
1131         };
1132
1133         pmu {
1134                 compatible = "arm,cortex-a15-pmu";
1135                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1136                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1137                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1138                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1139                 interrupt-affinity = <&{/cpus/cpu@0}>,
1140                                      <&{/cpus/cpu@1}>,
1141                                      <&{/cpus/cpu@2}>,
1142                                      <&{/cpus/cpu@3}>;
1143         };
1144
1145         thermal-zones {
1146                 cpu {
1147                         polling-delay-passive = <1000>;
1148                         polling-delay = <1000>;
1149
1150                         thermal-sensors =
1151                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1152                 };
1153
1154                 mem {
1155                         polling-delay-passive = <1000>;
1156                         polling-delay = <1000>;
1157
1158                         thermal-sensors =
1159                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1160                 };
1161
1162                 gpu {
1163                         polling-delay-passive = <1000>;
1164                         polling-delay = <1000>;
1165
1166                         thermal-sensors =
1167                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1168                 };
1169
1170                 pllx {
1171                         polling-delay-passive = <1000>;
1172                         polling-delay = <1000>;
1173
1174                         thermal-sensors =
1175                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1176                 };
1177         };
1178
1179         timer {
1180                 compatible = "arm,armv7-timer";
1181                 interrupts = <GIC_PPI 13
1182                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1183                              <GIC_PPI 14
1184                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1185                              <GIC_PPI 11
1186                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1187                              <GIC_PPI 10
1188                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1189                 interrupt-parent = <&gic>;
1190         };
1191 };