arch/arm/boot/dts/tegra124.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra124-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra124-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/tegra124-car.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9
  10 / {
  11         compatible = "nvidia,tegra124";
  12         interrupt-parent = <&lic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x0 0x80000000 0x0 0x0>;
  19         };
  20
  21         pcie@1003000 {
  22                 compatible = "nvidia,tegra124-pcie";
  23                 device_type = "pci";
  24                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  25                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  26                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  27                 reg-names = "pads", "afi", "cs";
  28                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  29                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  30                 interrupt-names = "intr", "msi";
  31
  32                 #interrupt-cells = <1>;
  33                 interrupt-map-mask = <0 0 0 0>;
  34                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  35
  36                 bus-range = <0x00 0xff>;
  37                 #address-cells = <3>;
  38                 #size-cells = <2>;
  39
  40                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  41                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  42                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  43                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  44                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  45
  46                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  47                          <&tegra_car TEGRA124_CLK_AFI>,
  48                          <&tegra_car TEGRA124_CLK_PLL_E>,
  49                          <&tegra_car TEGRA124_CLK_CML0>;
  50                 clock-names = "pex", "afi", "pll_e", "cml";
  51                 resets = <&tegra_car 70>,
  52                          <&tegra_car 72>,
  53                          <&tegra_car 74>;
  54                 reset-names = "pex", "afi", "pcie_x";
  55                 status = "disabled";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         bus-range = <0x00 0xff>;
  62                         status = "disabled";
  63
  64                         #address-cells = <3>;
  65                         #size-cells = <2>;
  66                         ranges;
  67
  68                         nvidia,num-lanes = <2>;
  69                 };
  70
  71                 pci@2,0 {
  72                         device_type = "pci";
  73                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  74                         reg = <0x001000 0 0 0 0>;
  75                         bus-range = <0x00 0xff>;
  76                         status = "disabled";
  77
  78                         #address-cells = <3>;
  79                         #size-cells = <2>;
  80                         ranges;
  81
  82                         nvidia,num-lanes = <1>;
  83                 };
  84         };
  85
  86         host1x@50000000 {
  87                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  88                 reg = <0x0 0x50000000 0x0 0x00034000>;
  89                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  90                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  91                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  92                 resets = <&tegra_car 28>;
  93                 reset-names = "host1x";
  94                 iommus = <&mc TEGRA_SWGROUP_HC>;
  95
  96                 #address-cells = <2>;
  97                 #size-cells = <2>;
  98
  99                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
 100
 101                 dc@54200000 {
 102                         compatible = "nvidia,tegra124-dc";
 103                         reg = <0x0 0x54200000 0x0 0x00040000>;
 104                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 106                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 107                         clock-names = "dc", "parent";
 108                         resets = <&tegra_car 27>;
 109                         reset-names = "dc";
 110
 111                         iommus = <&mc TEGRA_SWGROUP_DC>;
 112
 113                         nvidia,head = <0>;
 114                 };
 115
 116                 dc@54240000 {
 117                         compatible = "nvidia,tegra124-dc";
 118                         reg = <0x0 0x54240000 0x0 0x00040000>;
 119                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 121                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 122                         clock-names = "dc", "parent";
 123                         resets = <&tegra_car 26>;
 124                         reset-names = "dc";
 125
 126                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 127
 128                         nvidia,head = <1>;
 129                 };
 130
 131                 hdmi: hdmi@54280000 {
 132                         compatible = "nvidia,tegra124-hdmi";
 133                         reg = <0x0 0x54280000 0x0 0x00040000>;
 134                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 136                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 137                         clock-names = "hdmi", "parent";
 138                         resets = <&tegra_car 51>;
 139                         reset-names = "hdmi";
 140                         status = "disabled";
 141                 };
 142
 143                 vic@54340000 {
 144                         compatible = "nvidia,tegra124-vic";
 145                         reg = <0x0 0x54340000 0x0 0x00040000>;
 146                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&tegra_car TEGRA124_CLK_VIC03>;
 148                         clock-names = "vic";
 149                         resets = <&tegra_car 178>;
 150                         reset-names = "vic";
 151
 152                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 153                 };
 154
 155                 sor@54540000 {
 156                         compatible = "nvidia,tegra124-sor";
 157                         reg = <0x0 0x54540000 0x0 0x00040000>;
 158                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 160                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 161                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 162                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 163                         clock-names = "sor", "parent", "dp", "safe";
 164                         resets = <&tegra_car 182>;
 165                         reset-names = "sor";
 166                         status = "disabled";
 167                 };
 168
 169                 dpaux: dpaux@545c0000 {
 170                         compatible = "nvidia,tegra124-dpaux";
 171                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 172                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 173                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 174                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 175                         clock-names = "dpaux", "parent";
 176                         resets = <&tegra_car 181>;
 177                         reset-names = "dpaux";
 178                         status = "disabled";
 179                 };
 180         };
 181
 182         gic: interrupt-controller@50041000 {
 183                 compatible = "arm,cortex-a15-gic";
 184                 #interrupt-cells = <3>;
 185                 interrupt-controller;
 186                 reg = <0x0 0x50041000 0x0 0x1000>,
 187                       <0x0 0x50042000 0x0 0x1000>,
 188                       <0x0 0x50044000 0x0 0x2000>,
 189                       <0x0 0x50046000 0x0 0x2000>;
 190                 interrupts = <GIC_PPI 9
 191                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 192                 interrupt-parent = <&gic>;
 193         };
 194
 195         /*
 196          * Please keep the following 0, notation in place as a former mainline
 197          * U-Boot version was looking for that particular notation in order to
 198          * perform required fix-ups on that GPU node.
 199          */
 200         gpu@0,57000000 {
 201                 compatible = "nvidia,gk20a";
 202                 reg = <0x0 0x57000000 0x0 0x01000000>,
 203                       <0x0 0x58000000 0x0 0x01000000>;
 204                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 206                 interrupt-names = "stall", "nonstall";
 207                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 208                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 209                 clock-names = "gpu", "pwr";
 210                 resets = <&tegra_car 184>;
 211                 reset-names = "gpu";
 212
 213                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 214
 215                 status = "disabled";
 216         };
 217
 218         lic: interrupt-controller@60004000 {
 219                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 220                 reg = <0x0 0x60004000 0x0 0x100>,
 221                       <0x0 0x60004100 0x0 0x100>,
 222                       <0x0 0x60004200 0x0 0x100>,
 223                       <0x0 0x60004300 0x0 0x100>,
 224                       <0x0 0x60004400 0x0 0x100>;
 225                 interrupt-controller;
 226                 #interrupt-cells = <3>;
 227                 interrupt-parent = <&gic>;
 228         };
 229
 230         timer@60005000 {
 231                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 232                 reg = <0x0 0x60005000 0x0 0x400>;
 233                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 240         };
 241
 242         tegra_car: clock@60006000 {
 243                 compatible = "nvidia,tegra124-car";
 244                 reg = <0x0 0x60006000 0x0 0x1000>;
 245                 #clock-cells = <1>;
 246                 #reset-cells = <1>;
 247                 nvidia,external-memory-controller = <&emc>;
 248         };
 249
 250         flow-controller@60007000 {
 251                 compatible = "nvidia,tegra124-flowctrl";
 252                 reg = <0x0 0x60007000 0x0 0x1000>;
 253         };
 254
 255         actmon@6000c800 {
 256                 compatible = "nvidia,tegra124-actmon";
 257                 reg = <0x0 0x6000c800 0x0 0x400>;
 258                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 260                          <&tegra_car TEGRA124_CLK_EMC>;
 261                 clock-names = "actmon", "emc";
 262                 resets = <&tegra_car 119>;
 263                 reset-names = "actmon";
 264         };
 265
 266         gpio: gpio@6000d000 {
 267                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 268                 reg = <0x0 0x6000d000 0x0 0x1000>;
 269                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 277                 #gpio-cells = <2>;
 278                 gpio-controller;
 279                 #interrupt-cells = <2>;
 280                 interrupt-controller;
 281                 /*
 282                 gpio-ranges = <&pinmux 0 0 251>;
 283                 */
 284         };
 285
 286         apbdma: dma@60020000 {
 287                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 288                 reg = <0x0 0x60020000 0x0 0x1400>;
 289                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 321                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 322                 resets = <&tegra_car 34>;
 323                 reset-names = "dma";
 324                 #dma-cells = <1>;
 325         };
 326
 327         apbmisc@70000800 {
 328                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 329                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 330                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 331         };
 332
 333         pinmux: pinmux@70000868 {
 334                 compatible = "nvidia,tegra124-pinmux";
 335                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 336                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 337                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 338         };
 339
 340         /*
 341          * There are two serial driver i.e. 8250 based simple serial
 342          * driver and APB DMA based serial driver for higher baudrate
 343          * and performace. To enable the 8250 based driver, the compatible
 344          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 345          * the APB DMA based serial driver, the compatible is
 346          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 347          */
 348         uarta: serial@70006000 {
 349                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 350                 reg = <0x0 0x70006000 0x0 0x40>;
 351                 reg-shift = <2>;
 352                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 354                 resets = <&tegra_car 6>;
 355                 reset-names = "serial";
 356                 dmas = <&apbdma 8>, <&apbdma 8>;
 357                 dma-names = "rx", "tx";
 358                 status = "disabled";
 359         };
 360
 361         uartb: serial@70006040 {
 362                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 363                 reg = <0x0 0x70006040 0x0 0x40>;
 364                 reg-shift = <2>;
 365                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 366                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 367                 resets = <&tegra_car 7>;
 368                 reset-names = "serial";
 369                 dmas = <&apbdma 9>, <&apbdma 9>;
 370                 dma-names = "rx", "tx";
 371                 status = "disabled";
 372         };
 373
 374         uartc: serial@70006200 {
 375                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 376                 reg = <0x0 0x70006200 0x0 0x40>;
 377                 reg-shift = <2>;
 378                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 380                 resets = <&tegra_car 55>;
 381                 reset-names = "serial";
 382                 dmas = <&apbdma 10>, <&apbdma 10>;
 383                 dma-names = "rx", "tx";
 384                 status = "disabled";
 385         };
 386
 387         uartd: serial@70006300 {
 388                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 389                 reg = <0x0 0x70006300 0x0 0x40>;
 390                 reg-shift = <2>;
 391                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 393                 resets = <&tegra_car 65>;
 394                 reset-names = "serial";
 395                 dmas = <&apbdma 19>, <&apbdma 19>;
 396                 dma-names = "rx", "tx";
 397                 status = "disabled";
 398         };
 399
 400         pwm: pwm@7000a000 {
 401                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 402                 reg = <0x0 0x7000a000 0x0 0x100>;
 403                 #pwm-cells = <2>;
 404                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 405                 resets = <&tegra_car 17>;
 406                 reset-names = "pwm";
 407                 status = "disabled";
 408         };
 409
 410         i2c@7000c000 {
 411                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 412                 reg = <0x0 0x7000c000 0x0 0x100>;
 413                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 417                 clock-names = "div-clk";
 418                 resets = <&tegra_car 12>;
 419                 reset-names = "i2c";
 420                 dmas = <&apbdma 21>, <&apbdma 21>;
 421                 dma-names = "rx", "tx";
 422                 status = "disabled";
 423         };
 424
 425         i2c@7000c400 {
 426                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 427                 reg = <0x0 0x7000c400 0x0 0x100>;
 428                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 432                 clock-names = "div-clk";
 433                 resets = <&tegra_car 54>;
 434                 reset-names = "i2c";
 435                 dmas = <&apbdma 22>, <&apbdma 22>;
 436                 dma-names = "rx", "tx";
 437                 status = "disabled";
 438         };
 439
 440         i2c@7000c500 {
 441                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 442                 reg = <0x0 0x7000c500 0x0 0x100>;
 443                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 447                 clock-names = "div-clk";
 448                 resets = <&tegra_car 67>;
 449                 reset-names = "i2c";
 450                 dmas = <&apbdma 23>, <&apbdma 23>;
 451                 dma-names = "rx", "tx";
 452                 status = "disabled";
 453         };
 454
 455         i2c@7000c700 {
 456                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 457                 reg = <0x0 0x7000c700 0x0 0x100>;
 458                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 462                 clock-names = "div-clk";
 463                 resets = <&tegra_car 103>;
 464                 reset-names = "i2c";
 465                 dmas = <&apbdma 26>, <&apbdma 26>;
 466                 dma-names = "rx", "tx";
 467                 status = "disabled";
 468         };
 469
 470         i2c@7000d000 {
 471                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 472                 reg = <0x0 0x7000d000 0x0 0x100>;
 473                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 477                 clock-names = "div-clk";
 478                 resets = <&tegra_car 47>;
 479                 reset-names = "i2c";
 480                 dmas = <&apbdma 24>, <&apbdma 24>;
 481                 dma-names = "rx", "tx";
 482                 status = "disabled";
 483         };
 484
 485         i2c@7000d100 {
 486                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 487                 reg = <0x0 0x7000d100 0x0 0x100>;
 488                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 492                 clock-names = "div-clk";
 493                 resets = <&tegra_car 166>;
 494                 reset-names = "i2c";
 495                 dmas = <&apbdma 30>, <&apbdma 30>;
 496                 dma-names = "rx", "tx";
 497                 status = "disabled";
 498         };
 499
 500         spi@7000d400 {
 501                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 502                 reg = <0x0 0x7000d400 0x0 0x200>;
 503                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 507                 clock-names = "spi";
 508                 resets = <&tegra_car 41>;
 509                 reset-names = "spi";
 510                 dmas = <&apbdma 15>, <&apbdma 15>;
 511                 dma-names = "rx", "tx";
 512                 status = "disabled";
 513         };
 514
 515         spi@7000d600 {
 516                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 517                 reg = <0x0 0x7000d600 0x0 0x200>;
 518                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 522                 clock-names = "spi";
 523                 resets = <&tegra_car 44>;
 524                 reset-names = "spi";
 525                 dmas = <&apbdma 16>, <&apbdma 16>;
 526                 dma-names = "rx", "tx";
 527                 status = "disabled";
 528         };
 529
 530         spi@7000d800 {
 531                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 532                 reg = <0x0 0x7000d800 0x0 0x200>;
 533                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 537                 clock-names = "spi";
 538                 resets = <&tegra_car 46>;
 539                 reset-names = "spi";
 540                 dmas = <&apbdma 17>, <&apbdma 17>;
 541                 dma-names = "rx", "tx";
 542                 status = "disabled";
 543         };
 544
 545         spi@7000da00 {
 546                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 547                 reg = <0x0 0x7000da00 0x0 0x200>;
 548                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 552                 clock-names = "spi";
 553                 resets = <&tegra_car 68>;
 554                 reset-names = "spi";
 555                 dmas = <&apbdma 18>, <&apbdma 18>;
 556                 dma-names = "rx", "tx";
 557                 status = "disabled";
 558         };
 559
 560         spi@7000dc00 {
 561                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 562                 reg = <0x0 0x7000dc00 0x0 0x200>;
 563                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 567                 clock-names = "spi";
 568                 resets = <&tegra_car 104>;
 569                 reset-names = "spi";
 570                 dmas = <&apbdma 27>, <&apbdma 27>;
 571                 dma-names = "rx", "tx";
 572                 status = "disabled";
 573         };
 574
 575         spi@7000de00 {
 576                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 577                 reg = <0x0 0x7000de00 0x0 0x200>;
 578                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 582                 clock-names = "spi";
 583                 resets = <&tegra_car 105>;
 584                 reset-names = "spi";
 585                 dmas = <&apbdma 28>, <&apbdma 28>;
 586                 dma-names = "rx", "tx";
 587                 status = "disabled";
 588         };
 589
 590         rtc@7000e000 {
 591                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 592                 reg = <0x0 0x7000e000 0x0 0x100>;
 593                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 594                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 595         };
 596
 597         pmc@7000e400 {
 598                 compatible = "nvidia,tegra124-pmc";
 599                 reg = <0x0 0x7000e400 0x0 0x400>;
 600                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 601                 clock-names = "pclk", "clk32k_in";
 602         };
 603
 604         fuse@7000f800 {
 605                 compatible = "nvidia,tegra124-efuse";
 606                 reg = <0x0 0x7000f800 0x0 0x400>;
 607                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 608                 clock-names = "fuse";
 609                 resets = <&tegra_car 39>;
 610                 reset-names = "fuse";
 611         };
 612
 613         mc: memory-controller@70019000 {
 614                 compatible = "nvidia,tegra124-mc";
 615                 reg = <0x0 0x70019000 0x0 0x1000>;
 616                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 617                 clock-names = "mc";
 618
 619                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 620
 621                 #iommu-cells = <1>;
 622         };
 623
 624         emc: emc@7001b000 {
 625                 compatible = "nvidia,tegra124-emc";
 626                 reg = <0x0 0x7001b000 0x0 0x1000>;
 627
 628                 nvidia,memory-controller = <&mc>;
 629         };
 630
 631         sata@70020000 {
 632                 compatible = "nvidia,tegra124-ahci";
 633                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 634                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
 635                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 636                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 637                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
 638                          <&tegra_car TEGRA124_CLK_CML1>,
 639                          <&tegra_car TEGRA124_CLK_PLL_E>;
 640                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 641                 resets = <&tegra_car 124>,
 642                          <&tegra_car 123>,
 643                          <&tegra_car 129>;
 644                 reset-names = "sata", "sata-oob", "sata-cold";
 645                 status = "disabled";
 646         };
 647
 648         hda@70030000 {
 649                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 650                 reg = <0x0 0x70030000 0x0 0x10000>;
 651                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 653                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 654                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 655                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 656                 resets = <&tegra_car 125>, /* hda */
 657                          <&tegra_car 128>, /* hda2hdmi */
 658                          <&tegra_car 111>; /* hda2codec_2x */
 659                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 660                 status = "disabled";
 661         };
 662
 663         usb@70090000 {
 664                 compatible = "nvidia,tegra124-xusb";
 665                 reg = <0x0 0x70090000 0x0 0x8000>,
 666                       <0x0 0x70098000 0x0 0x1000>,
 667                       <0x0 0x70099000 0x0 0x1000>;
 668                 reg-names = "hcd", "fpci", "ipfs";
 669
 670                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 671                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 672
 673                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
 674                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
 675                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
 676                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
 677                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
 678                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
 679                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
 680                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
 681                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
 682                          <&tegra_car TEGRA124_CLK_CLK_M>,
 683                          <&tegra_car TEGRA124_CLK_PLL_E>;
 684                 clock-names = "xusb_host", "xusb_host_src",
 685                               "xusb_falcon_src", "xusb_ss",
 686                               "xusb_ss_div2", "xusb_ss_src",
 687                               "xusb_hs_src", "xusb_fs_src",
 688                               "pll_u_480m", "clk_m", "pll_e";
 689                 resets = <&tegra_car 89>, <&tegra_car 156>,
 690                          <&tegra_car 143>;
 691                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 692
 693                 nvidia,xusb-padctl = <&padctl>;
 694
 695                 status = "disabled";
 696         };
 697
 698         padctl: padctl@7009f000 {
 699                 compatible = "nvidia,tegra124-xusb-padctl";
 700                 reg = <0x0 0x7009f000 0x0 0x1000>;
 701                 resets = <&tegra_car 142>;
 702                 reset-names = "padctl";
 703
 704                 pads {
 705                         usb2 {
 706                                 status = "disabled";
 707
 708                                 lanes {
 709                                         usb2-0 {
 710                                                 status = "disabled";
 711                                                 #phy-cells = <0>;
 712                                         };
 713
 714                                         usb2-1 {
 715                                                 status = "disabled";
 716                                                 #phy-cells = <0>;
 717                                         };
 718
 719                                         usb2-2 {
 720                                                 status = "disabled";
 721                                                 #phy-cells = <0>;
 722                                         };
 723                                 };
 724                         };
 725
 726                         ulpi {
 727                                 status = "disabled";
 728
 729                                 lanes {
 730                                         ulpi-0 {
 731                                                 status = "disabled";
 732                                                 #phy-cells = <0>;
 733                                         };
 734                                 };
 735                         };
 736
 737                         hsic {
 738                                 status = "disabled";
 739
 740                                 lanes {
 741                                         hsic-0 {
 742                                                 status = "disabled";
 743                                                 #phy-cells = <0>;
 744                                         };
 745
 746                                         hsic-1 {
 747                                                 status = "disabled";
 748                                                 #phy-cells = <0>;
 749                                         };
 750                                 };
 751                         };
 752
 753                         pcie {
 754                                 status = "disabled";
 755
 756                                 lanes {
 757                                         pcie-0 {
 758                                                 status = "disabled";
 759                                                 #phy-cells = <0>;
 760                                         };
 761
 762                                         pcie-1 {
 763                                                 status = "disabled";
 764                                                 #phy-cells = <0>;
 765                                         };
 766
 767                                         pcie-2 {
 768                                                 status = "disabled";
 769                                                 #phy-cells = <0>;
 770                                         };
 771
 772                                         pcie-3 {
 773                                                 status = "disabled";
 774                                                 #phy-cells = <0>;
 775                                         };
 776
 777                                         pcie-4 {
 778                                                 status = "disabled";
 779                                                 #phy-cells = <0>;
 780                                         };
 781                                 };
 782                         };
 783
 784                         sata {
 785                                 status = "disabled";
 786
 787                                 lanes {
 788                                         sata-0 {
 789                                                 status = "disabled";
 790                                                 #phy-cells = <0>;
 791                                         };
 792                                 };
 793                         };
 794                 };
 795
 796                 ports {
 797                         usb2-0 {
 798                                 status = "disabled";
 799                         };
 800
 801                         usb2-1 {
 802                                 status = "disabled";
 803                         };
 804
 805                         usb2-2 {
 806                                 status = "disabled";
 807                         };
 808
 809                         ulpi-0 {
 810                                 status = "disabled";
 811                         };
 812
 813                         hsic-0 {
 814                                 status = "disabled";
 815                         };
 816
 817                         hsic-1 {
 818                                 status = "disabled";
 819                         };
 820
 821                         usb3-0 {
 822                                 status = "disabled";
 823                         };
 824
 825                         usb3-1 {
 826                                 status = "disabled";
 827                         };
 828                 };
 829         };
 830
 831         sdhci@700b0000 {
 832                 compatible = "nvidia,tegra124-sdhci";
 833                 reg = <0x0 0x700b0000 0x0 0x200>;
 834                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 835                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 836                 resets = <&tegra_car 14>;
 837                 reset-names = "sdhci";
 838                 status = "disabled";
 839         };
 840
 841         sdhci@700b0200 {
 842                 compatible = "nvidia,tegra124-sdhci";
 843                 reg = <0x0 0x700b0200 0x0 0x200>;
 844                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 845                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 846                 resets = <&tegra_car 9>;
 847                 reset-names = "sdhci";
 848                 status = "disabled";
 849         };
 850
 851         sdhci@700b0400 {
 852                 compatible = "nvidia,tegra124-sdhci";
 853                 reg = <0x0 0x700b0400 0x0 0x200>;
 854                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 855                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 856                 resets = <&tegra_car 69>;
 857                 reset-names = "sdhci";
 858                 status = "disabled";
 859         };
 860
 861         sdhci@700b0600 {
 862                 compatible = "nvidia,tegra124-sdhci";
 863                 reg = <0x0 0x700b0600 0x0 0x200>;
 864                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 865                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 866                 resets = <&tegra_car 15>;
 867                 reset-names = "sdhci";
 868                 status = "disabled";
 869         };
 870
 871         cec@70015000 {
 872                 compatible = "nvidia,tegra124-cec";
 873                 reg = <0x0 0x70015000 0x0 0x00001000>;
 874                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 875                 clocks = <&tegra_car TEGRA124_CLK_CEC>;
 876                 clock-names = "cec";
 877                 status = "disabled";
 878                 hdmi-phandle = <&hdmi>;
 879         };
 880
 881         soctherm: thermal-sensor@700e2000 {
 882                 compatible = "nvidia,tegra124-soctherm";
 883                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
 884                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
 885                 reg-names = "soctherm-reg", "car-reg";
 886                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 887                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 888                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 889                 clock-names = "tsensor", "soctherm";
 890                 resets = <&tegra_car 78>;
 891                 reset-names = "soctherm";
 892                 #thermal-sensor-cells = <1>;
 893
 894                 throttle-cfgs {
 895                         throttle_heavy: heavy {
 896                                 nvidia,priority = <100>;
 897                                 nvidia,cpu-throt-percent = <85>;
 898
 899                                 #cooling-cells = <2>;
 900                         };
 901                 };
 902         };
 903
 904         dfll: clock@70110000 {
 905                 compatible = "nvidia,tegra124-dfll";
 906                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 907                       <0 0x70110000 0 0x100>, /* I2C output control */
 908                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 909                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 910                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 911                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 912                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 913                          <&tegra_car TEGRA124_CLK_I2C5>;
 914                 clock-names = "soc", "ref", "i2c";
 915                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 916                 reset-names = "dvco";
 917                 #clock-cells = <0>;
 918                 clock-output-names = "dfllCPU_out";
 919                 nvidia,sample-rate = <12500>;
 920                 nvidia,droop-ctrl = <0x00000f00>;
 921                 nvidia,force-mode = <1>;
 922                 nvidia,cf = <10>;
 923                 nvidia,ci = <0>;
 924                 nvidia,cg = <2>;
 925                 status = "disabled";
 926         };
 927
 928         ahub@70300000 {
 929                 compatible = "nvidia,tegra124-ahub";
 930                 reg = <0x0 0x70300000 0x0 0x200>,
 931                       <0x0 0x70300800 0x0 0x800>,
 932                       <0x0 0x70300200 0x0 0x600>;
 933                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 934                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 935                          <&tegra_car TEGRA124_CLK_APBIF>;
 936                 clock-names = "d_audio", "apbif";
 937                 resets = <&tegra_car 106>, /* d_audio */
 938                          <&tegra_car 107>, /* apbif */
 939                          <&tegra_car 30>,  /* i2s0 */
 940                          <&tegra_car 11>,  /* i2s1 */
 941                          <&tegra_car 18>,  /* i2s2 */
 942                          <&tegra_car 101>, /* i2s3 */
 943                          <&tegra_car 102>, /* i2s4 */
 944                          <&tegra_car 108>, /* dam0 */
 945                          <&tegra_car 109>, /* dam1 */
 946                          <&tegra_car 110>, /* dam2 */
 947                          <&tegra_car 10>,  /* spdif */
 948                          <&tegra_car 153>, /* amx */
 949                          <&tegra_car 185>, /* amx1 */
 950                          <&tegra_car 154>, /* adx */
 951                          <&tegra_car 180>, /* adx1 */
 952                          <&tegra_car 186>, /* afc0 */
 953                          <&tegra_car 187>, /* afc1 */
 954                          <&tegra_car 188>, /* afc2 */
 955                          <&tegra_car 189>, /* afc3 */
 956                          <&tegra_car 190>, /* afc4 */
 957                          <&tegra_car 191>; /* afc5 */
 958                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 959                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 960                               "spdif", "amx", "amx1", "adx", "adx1",
 961                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 962                 dmas = <&apbdma 1>, <&apbdma 1>,
 963                        <&apbdma 2>, <&apbdma 2>,
 964                        <&apbdma 3>, <&apbdma 3>,
 965                        <&apbdma 4>, <&apbdma 4>,
 966                        <&apbdma 6>, <&apbdma 6>,
 967                        <&apbdma 7>, <&apbdma 7>,
 968                        <&apbdma 12>, <&apbdma 12>,
 969                        <&apbdma 13>, <&apbdma 13>,
 970                        <&apbdma 14>, <&apbdma 14>,
 971                        <&apbdma 29>, <&apbdma 29>;
 972                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 973                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 974                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 975                             "rx9", "tx9";
 976                 ranges;
 977                 #address-cells = <2>;
 978                 #size-cells = <2>;
 979
 980                 tegra_i2s0: i2s@70301000 {
 981                         compatible = "nvidia,tegra124-i2s";
 982                         reg = <0x0 0x70301000 0x0 0x100>;
 983                         nvidia,ahub-cif-ids = <4 4>;
 984                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 985                         resets = <&tegra_car 30>;
 986                         reset-names = "i2s";
 987                         status = "disabled";
 988                 };
 989
 990                 tegra_i2s1: i2s@70301100 {
 991                         compatible = "nvidia,tegra124-i2s";
 992                         reg = <0x0 0x70301100 0x0 0x100>;
 993                         nvidia,ahub-cif-ids = <5 5>;
 994                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 995                         resets = <&tegra_car 11>;
 996                         reset-names = "i2s";
 997                         status = "disabled";
 998                 };
 999
1000                 tegra_i2s2: i2s@70301200 {
1001                         compatible = "nvidia,tegra124-i2s";
1002                         reg = <0x0 0x70301200 0x0 0x100>;
1003                         nvidia,ahub-cif-ids = <6 6>;
1004                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1005                         resets = <&tegra_car 18>;
1006                         reset-names = "i2s";
1007                         status = "disabled";
1008                 };
1009
1010                 tegra_i2s3: i2s@70301300 {
1011                         compatible = "nvidia,tegra124-i2s";
1012                         reg = <0x0 0x70301300 0x0 0x100>;
1013                         nvidia,ahub-cif-ids = <7 7>;
1014                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1015                         resets = <&tegra_car 101>;
1016                         reset-names = "i2s";
1017                         status = "disabled";
1018                 };
1019
1020                 tegra_i2s4: i2s@70301400 {
1021                         compatible = "nvidia,tegra124-i2s";
1022                         reg = <0x0 0x70301400 0x0 0x100>;
1023                         nvidia,ahub-cif-ids = <8 8>;
1024                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1025                         resets = <&tegra_car 102>;
1026                         reset-names = "i2s";
1027                         status = "disabled";
1028                 };
1029         };
1030
1031         usb@7d000000 {
1032                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1033                 reg = <0x0 0x7d000000 0x0 0x4000>;
1034                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1035                 phy_type = "utmi";
1036                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1037                 resets = <&tegra_car 22>;
1038                 reset-names = "usb";
1039                 nvidia,phy = <&phy1>;
1040                 status = "disabled";
1041         };
1042
1043         phy1: usb-phy@7d000000 {
1044                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1045                 reg = <0x0 0x7d000000 0x0 0x4000>,
1046                       <0x0 0x7d000000 0x0 0x4000>;
1047                 phy_type = "utmi";
1048                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1049                          <&tegra_car TEGRA124_CLK_PLL_U>,
1050                          <&tegra_car TEGRA124_CLK_USBD>;
1051                 clock-names = "reg", "pll_u", "utmi-pads";
1052                 resets = <&tegra_car 22>, <&tegra_car 22>;
1053                 reset-names = "usb", "utmi-pads";
1054                 nvidia,hssync-start-delay = <0>;
1055                 nvidia,idle-wait-delay = <17>;
1056                 nvidia,elastic-limit = <16>;
1057                 nvidia,term-range-adj = <6>;
1058                 nvidia,xcvr-setup = <9>;
1059                 nvidia,xcvr-lsfslew = <0>;
1060                 nvidia,xcvr-lsrslew = <3>;
1061                 nvidia,hssquelch-level = <2>;
1062                 nvidia,hsdiscon-level = <5>;
1063                 nvidia,xcvr-hsslew = <12>;
1064                 nvidia,has-utmi-pad-registers;
1065                 status = "disabled";
1066         };
1067
1068         usb@7d004000 {
1069                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1070                 reg = <0x0 0x7d004000 0x0 0x4000>;
1071                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1072                 phy_type = "utmi";
1073                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1074                 resets = <&tegra_car 58>;
1075                 reset-names = "usb";
1076                 nvidia,phy = <&phy2>;
1077                 status = "disabled";
1078         };
1079
1080         phy2: usb-phy@7d004000 {
1081                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1082                 reg = <0x0 0x7d004000 0x0 0x4000>,
1083                       <0x0 0x7d000000 0x0 0x4000>;
1084                 phy_type = "utmi";
1085                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1086                          <&tegra_car TEGRA124_CLK_PLL_U>,
1087                          <&tegra_car TEGRA124_CLK_USBD>;
1088                 clock-names = "reg", "pll_u", "utmi-pads";
1089                 resets = <&tegra_car 58>, <&tegra_car 22>;
1090                 reset-names = "usb", "utmi-pads";
1091                 nvidia,hssync-start-delay = <0>;
1092                 nvidia,idle-wait-delay = <17>;
1093                 nvidia,elastic-limit = <16>;
1094                 nvidia,term-range-adj = <6>;
1095                 nvidia,xcvr-setup = <9>;
1096                 nvidia,xcvr-lsfslew = <0>;
1097                 nvidia,xcvr-lsrslew = <3>;
1098                 nvidia,hssquelch-level = <2>;
1099                 nvidia,hsdiscon-level = <5>;
1100                 nvidia,xcvr-hsslew = <12>;
1101                 status = "disabled";
1102         };
1103
1104         usb@7d008000 {
1105                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1106                 reg = <0x0 0x7d008000 0x0 0x4000>;
1107                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1108                 phy_type = "utmi";
1109                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1110                 resets = <&tegra_car 59>;
1111                 reset-names = "usb";
1112                 nvidia,phy = <&phy3>;
1113                 status = "disabled";
1114         };
1115
1116         phy3: usb-phy@7d008000 {
1117                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1118                 reg = <0x0 0x7d008000 0x0 0x4000>,
1119                       <0x0 0x7d000000 0x0 0x4000>;
1120                 phy_type = "utmi";
1121                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1122                          <&tegra_car TEGRA124_CLK_PLL_U>,
1123                          <&tegra_car TEGRA124_CLK_USBD>;
1124                 clock-names = "reg", "pll_u", "utmi-pads";
1125                 resets = <&tegra_car 59>, <&tegra_car 22>;
1126                 reset-names = "usb", "utmi-pads";
1127                 nvidia,hssync-start-delay = <0>;
1128                 nvidia,idle-wait-delay = <17>;
1129                 nvidia,elastic-limit = <16>;
1130                 nvidia,term-range-adj = <6>;
1131                 nvidia,xcvr-setup = <9>;
1132                 nvidia,xcvr-lsfslew = <0>;
1133                 nvidia,xcvr-lsrslew = <3>;
1134                 nvidia,hssquelch-level = <2>;
1135                 nvidia,hsdiscon-level = <5>;
1136                 nvidia,xcvr-hsslew = <12>;
1137                 status = "disabled";
1138         };
1139
1140         cpus {
1141                 #address-cells = <1>;
1142                 #size-cells = <0>;
1143
1144                 cpu@0 {
1145                         device_type = "cpu";
1146                         compatible = "arm,cortex-a15";
1147                         reg = <0>;
1148
1149                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1150                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1151                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1152                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1153                                  <&dfll>;
1154                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1155                         /* FIXME: what's the actual transition time? */
1156                         clock-latency = <300000>;
1157                 };
1158
1159                 cpu@1 {
1160                         device_type = "cpu";
1161                         compatible = "arm,cortex-a15";
1162                         reg = <1>;
1163                 };
1164
1165                 cpu@2 {
1166                         device_type = "cpu";
1167                         compatible = "arm,cortex-a15";
1168                         reg = <2>;
1169                 };
1170
1171                 cpu@3 {
1172                         device_type = "cpu";
1173                         compatible = "arm,cortex-a15";
1174                         reg = <3>;
1175                 };
1176         };
1177
1178         pmu {
1179                 compatible = "arm,cortex-a15-pmu";
1180                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1181                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1182                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1183                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1184                 interrupt-affinity = <&{/cpus/cpu@0}>,
1185                                      <&{/cpus/cpu@1}>,
1186                                      <&{/cpus/cpu@2}>,
1187                                      <&{/cpus/cpu@3}>;
1188         };
1189
1190         thermal-zones {
1191                 cpu {
1192                         polling-delay-passive = <1000>;
1193                         polling-delay = <1000>;
1194
1195                         thermal-sensors =
1196                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1197
1198                         trips {
1199                                 cpu-shutdown-trip {
1200                                         temperature = <103000>;
1201                                         hysteresis = <0>;
1202                                         type = "critical";
1203                                 };
1204                                 cpu_throttle_trip: throttle-trip {
1205                                         temperature = <100000>;
1206                                         hysteresis = <1000>;
1207                                         type = "hot";
1208                                 };
1209                         };
1210
1211                         cooling-maps {
1212                                 map0 {
1213                                         trip = <&cpu_throttle_trip>;
1214                                         cooling-device = <&throttle_heavy 1 1>;
1215                                 };
1216                         };
1217                 };
1218
1219                 mem {
1220                         polling-delay-passive = <1000>;
1221                         polling-delay = <1000>;
1222
1223                         thermal-sensors =
1224                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1225
1226                         trips {
1227                                 mem-shutdown-trip {
1228                                         temperature = <103000>;
1229                                         hysteresis = <0>;
1230                                         type = "critical";
1231                                 };
1232                         };
1233
1234                         cooling-maps {
1235                                 /*
1236                                  * There are currently no cooling maps,
1237                                  * because there are no cooling devices.
1238                                  */
1239                         };
1240                 };
1241
1242                 gpu {
1243                         polling-delay-passive = <1000>;
1244                         polling-delay = <1000>;
1245
1246                         thermal-sensors =
1247                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1248
1249                         trips {
1250                                 gpu-shutdown-trip {
1251                                         temperature = <101000>;
1252                                         hysteresis = <0>;
1253                                         type = "critical";
1254                                 };
1255                                 gpu_throttle_trip: throttle-trip {
1256                                         temperature = <99000>;
1257                                         hysteresis = <1000>;
1258                                         type = "hot";
1259                                 };
1260                         };
1261
1262                         cooling-maps {
1263                                 map0 {
1264                                         trip = <&gpu_throttle_trip>;
1265                                         cooling-device = <&throttle_heavy 1 1>;
1266                                 };
1267                         };
1268                 };
1269
1270                 pllx {
1271                         polling-delay-passive = <1000>;
1272                         polling-delay = <1000>;
1273
1274                         thermal-sensors =
1275                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1276
1277                         trips {
1278                                 pllx-shutdown-trip {
1279                                         temperature = <103000>;
1280                                         hysteresis = <0>;
1281                                         type = "critical";
1282                                 };
1283                         };
1284
1285                         cooling-maps {
1286                                 /*
1287                                  * There are currently no cooling maps,
1288                                  * because there are no cooling devices.
1289                                  */
1290                         };
1291                 };
1292         };
1293
1294         timer {
1295                 compatible = "arm,armv7-timer";
1296                 interrupts = <GIC_PPI 13
1297                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1298                              <GIC_PPI 14
1299                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1300                              <GIC_PPI 11
1301                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1302                              <GIC_PPI 10
1303                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1304                 interrupt-parent = <&gic>;
1305         };
1306 };