arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         compatible = "nvidia,tegra124";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         pcie-controller@0,01003000 {
  16                 compatible = "nvidia,tegra124-pcie";
  17                 device_type = "pci";
  18                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  19                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  20                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  21                 reg-names = "pads", "afi", "cs";
  22                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  23                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  24                 interrupt-names = "intr", "msi";
  25
  26                 #interrupt-cells = <1>;
  27                 interrupt-map-mask = <0 0 0 0>;
  28                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  29
  30                 bus-range = <0x00 0xff>;
  31                 #address-cells = <3>;
  32                 #size-cells = <2>;
  33
  34                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  35                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  36                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  37                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  38                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  39
  40                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  41                          <&tegra_car TEGRA124_CLK_AFI>,
  42                          <&tegra_car TEGRA124_CLK_PLL_E>,
  43                          <&tegra_car TEGRA124_CLK_CML0>;
  44                 clock-names = "pex", "afi", "pll_e", "cml";
  45                 resets = <&tegra_car 70>,
  46                          <&tegra_car 72>,
  47                          <&tegra_car 74>;
  48                 reset-names = "pex", "afi", "pcie_x";
  49                 status = "disabled";
  50
  51                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  52                 phy-names = "pcie";
  53
  54                 pci@1,0 {
  55                         device_type = "pci";
  56                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  57                         reg = <0x000800 0 0 0 0>;
  58                         status = "disabled";
  59
  60                         #address-cells = <3>;
  61                         #size-cells = <2>;
  62                         ranges;
  63
  64                         nvidia,num-lanes = <2>;
  65                 };
  66
  67                 pci@2,0 {
  68                         device_type = "pci";
  69                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  70                         reg = <0x001000 0 0 0 0>;
  71                         status = "disabled";
  72
  73                         #address-cells = <3>;
  74                         #size-cells = <2>;
  75                         ranges;
  76
  77                         nvidia,num-lanes = <1>;
  78                 };
  79         };
  80
  81         host1x@0,50000000 {
  82                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  83                 reg = <0x0 0x50000000 0x0 0x00034000>;
  84                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  85                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  86                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  87                 resets = <&tegra_car 28>;
  88                 reset-names = "host1x";
  89
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92
  93                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  94
  95                 dc@0,54200000 {
  96                         compatible = "nvidia,tegra124-dc";
  97                         reg = <0x0 0x54200000 0x0 0x00040000>;
  98                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  99                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 100                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 101                         clock-names = "dc", "parent";
 102                         resets = <&tegra_car 27>;
 103                         reset-names = "dc";
 104
 105                         nvidia,head = <0>;
 106                 };
 107
 108                 dc@0,54240000 {
 109                         compatible = "nvidia,tegra124-dc";
 110                         reg = <0x0 0x54240000 0x0 0x00040000>;
 111                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 113                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 114                         clock-names = "dc", "parent";
 115                         resets = <&tegra_car 26>;
 116                         reset-names = "dc";
 117
 118                         nvidia,head = <1>;
 119                 };
 120
 121                 hdmi@0,54280000 {
 122                         compatible = "nvidia,tegra124-hdmi";
 123                         reg = <0x0 0x54280000 0x0 0x00040000>;
 124                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 125                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 126                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 127                         clock-names = "hdmi", "parent";
 128                         resets = <&tegra_car 51>;
 129                         reset-names = "hdmi";
 130                         status = "disabled";
 131                 };
 132
 133                 sor@0,54540000 {
 134                         compatible = "nvidia,tegra124-sor";
 135                         reg = <0x0 0x54540000 0x0 0x00040000>;
 136                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 138                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 139                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 140                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 141                         clock-names = "sor", "parent", "dp", "safe";
 142                         resets = <&tegra_car 182>;
 143                         reset-names = "sor";
 144                         status = "disabled";
 145                 };
 146
 147                 dpaux: dpaux@0,545c0000 {
 148                         compatible = "nvidia,tegra124-dpaux";
 149                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 150                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 151                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 152                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 153                         clock-names = "dpaux", "parent";
 154                         resets = <&tegra_car 181>;
 155                         reset-names = "dpaux";
 156                         status = "disabled";
 157                 };
 158         };
 159
 160         gic: interrupt-controller@0,50041000 {
 161                 compatible = "arm,cortex-a15-gic";
 162                 #interrupt-cells = <3>;
 163                 interrupt-controller;
 164                 reg = <0x0 0x50041000 0x0 0x1000>,
 165                       <0x0 0x50042000 0x0 0x1000>,
 166                       <0x0 0x50044000 0x0 0x2000>,
 167                       <0x0 0x50046000 0x0 0x2000>;
 168                 interrupts = <GIC_PPI 9
 169                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 170         };
 171
 172         gpu@0,57000000 {
 173                 compatible = "nvidia,gk20a";
 174                 reg = <0x0 0x57000000 0x0 0x01000000>,
 175                       <0x0 0x58000000 0x0 0x01000000>;
 176                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 178                 interrupt-names = "stall", "nonstall";
 179                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 180                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 181                 clock-names = "gpu", "pwr";
 182                 resets = <&tegra_car 184>;
 183                 reset-names = "gpu";
 184                 status = "disabled";
 185         };
 186
 187         timer@0,60005000 {
 188                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 189                 reg = <0x0 0x60005000 0x0 0x400>;
 190                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 197         };
 198
 199         tegra_car: clock@0,60006000 {
 200                 compatible = "nvidia,tegra124-car";
 201                 reg = <0x0 0x60006000 0x0 0x1000>;
 202                 #clock-cells = <1>;
 203                 #reset-cells = <1>;
 204         };
 205
 206         flow-controller@0,60007000 {
 207                 compatible = "nvidia,tegra124-flowctrl";
 208                 reg = <0x0 0x60007000 0x0 0x1000>;
 209         };
 210
 211         gpio: gpio@0,6000d000 {
 212                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 213                 reg = <0x0 0x6000d000 0x0 0x1000>;
 214                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 222                 #gpio-cells = <2>;
 223                 gpio-controller;
 224                 #interrupt-cells = <2>;
 225                 interrupt-controller;
 226         };
 227
 228         apbdma: dma@0,60020000 {
 229                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 230                 reg = <0x0 0x60020000 0x0 0x1400>;
 231                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 263                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 264                 resets = <&tegra_car 34>;
 265                 reset-names = "dma";
 266                 #dma-cells = <1>;
 267         };
 268
 269         apbmisc@0,70000800 {
 270                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 271                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 272                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 273         };
 274
 275         pinmux: pinmux@0,70000868 {
 276                 compatible = "nvidia,tegra124-pinmux";
 277                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 278                       <0x0 0x70003000 0x0 0x434>; /* Mux registers */
 279         };
 280
 281         /*
 282          * There are two serial driver i.e. 8250 based simple serial
 283          * driver and APB DMA based serial driver for higher baudrate
 284          * and performace. To enable the 8250 based driver, the compatible
 285          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 286          * the APB DMA based serial driver, the comptible is
 287          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 288          */
 289         serial@0,70006000 {
 290                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 291                 reg = <0x0 0x70006000 0x0 0x40>;
 292                 reg-shift = <2>;
 293                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 295                 resets = <&tegra_car 6>;
 296                 reset-names = "serial";
 297                 dmas = <&apbdma 8>, <&apbdma 8>;
 298                 dma-names = "rx", "tx";
 299                 status = "disabled";
 300         };
 301
 302         serial@0,70006040 {
 303                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 304                 reg = <0x0 0x70006040 0x0 0x40>;
 305                 reg-shift = <2>;
 306                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 308                 resets = <&tegra_car 7>;
 309                 reset-names = "serial";
 310                 dmas = <&apbdma 9>, <&apbdma 9>;
 311                 dma-names = "rx", "tx";
 312                 status = "disabled";
 313         };
 314
 315         serial@0,70006200 {
 316                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 317                 reg = <0x0 0x70006200 0x0 0x40>;
 318                 reg-shift = <2>;
 319                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 321                 resets = <&tegra_car 55>;
 322                 reset-names = "serial";
 323                 dmas = <&apbdma 10>, <&apbdma 10>;
 324                 dma-names = "rx", "tx";
 325                 status = "disabled";
 326         };
 327
 328         serial@0,70006300 {
 329                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 330                 reg = <0x0 0x70006300 0x0 0x40>;
 331                 reg-shift = <2>;
 332                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 334                 resets = <&tegra_car 65>;
 335                 reset-names = "serial";
 336                 dmas = <&apbdma 19>, <&apbdma 19>;
 337                 dma-names = "rx", "tx";
 338                 status = "disabled";
 339         };
 340
 341         pwm: pwm@0,7000a000 {
 342                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 343                 reg = <0x0 0x7000a000 0x0 0x100>;
 344                 #pwm-cells = <2>;
 345                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 346                 resets = <&tegra_car 17>;
 347                 reset-names = "pwm";
 348                 status = "disabled";
 349         };
 350
 351         i2c@0,7000c000 {
 352                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 353                 reg = <0x0 0x7000c000 0x0 0x100>;
 354                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 358                 clock-names = "div-clk";
 359                 resets = <&tegra_car 12>;
 360                 reset-names = "i2c";
 361                 dmas = <&apbdma 21>, <&apbdma 21>;
 362                 dma-names = "rx", "tx";
 363                 status = "disabled";
 364         };
 365
 366         i2c@0,7000c400 {
 367                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 368                 reg = <0x0 0x7000c400 0x0 0x100>;
 369                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 373                 clock-names = "div-clk";
 374                 resets = <&tegra_car 54>;
 375                 reset-names = "i2c";
 376                 dmas = <&apbdma 22>, <&apbdma 22>;
 377                 dma-names = "rx", "tx";
 378                 status = "disabled";
 379         };
 380
 381         i2c@0,7000c500 {
 382                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 383                 reg = <0x0 0x7000c500 0x0 0x100>;
 384                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 388                 clock-names = "div-clk";
 389                 resets = <&tegra_car 67>;
 390                 reset-names = "i2c";
 391                 dmas = <&apbdma 23>, <&apbdma 23>;
 392                 dma-names = "rx", "tx";
 393                 status = "disabled";
 394         };
 395
 396         i2c@0,7000c700 {
 397                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 398                 reg = <0x0 0x7000c700 0x0 0x100>;
 399                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 403                 clock-names = "div-clk";
 404                 resets = <&tegra_car 103>;
 405                 reset-names = "i2c";
 406                 dmas = <&apbdma 26>, <&apbdma 26>;
 407                 dma-names = "rx", "tx";
 408                 status = "disabled";
 409         };
 410
 411         i2c@0,7000d000 {
 412                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 413                 reg = <0x0 0x7000d000 0x0 0x100>;
 414                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 418                 clock-names = "div-clk";
 419                 resets = <&tegra_car 47>;
 420                 reset-names = "i2c";
 421                 dmas = <&apbdma 24>, <&apbdma 24>;
 422                 dma-names = "rx", "tx";
 423                 status = "disabled";
 424         };
 425
 426         i2c@0,7000d100 {
 427                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 428                 reg = <0x0 0x7000d100 0x0 0x100>;
 429                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 433                 clock-names = "div-clk";
 434                 resets = <&tegra_car 166>;
 435                 reset-names = "i2c";
 436                 dmas = <&apbdma 30>, <&apbdma 30>;
 437                 dma-names = "rx", "tx";
 438                 status = "disabled";
 439         };
 440
 441         spi@0,7000d400 {
 442                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 443                 reg = <0x0 0x7000d400 0x0 0x200>;
 444                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 448                 clock-names = "spi";
 449                 resets = <&tegra_car 41>;
 450                 reset-names = "spi";
 451                 dmas = <&apbdma 15>, <&apbdma 15>;
 452                 dma-names = "rx", "tx";
 453                 status = "disabled";
 454         };
 455
 456         spi@0,7000d600 {
 457                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 458                 reg = <0x0 0x7000d600 0x0 0x200>;
 459                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 463                 clock-names = "spi";
 464                 resets = <&tegra_car 44>;
 465                 reset-names = "spi";
 466                 dmas = <&apbdma 16>, <&apbdma 16>;
 467                 dma-names = "rx", "tx";
 468                 status = "disabled";
 469         };
 470
 471         spi@0,7000d800 {
 472                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 473                 reg = <0x0 0x7000d800 0x0 0x200>;
 474                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 478                 clock-names = "spi";
 479                 resets = <&tegra_car 46>;
 480                 reset-names = "spi";
 481                 dmas = <&apbdma 17>, <&apbdma 17>;
 482                 dma-names = "rx", "tx";
 483                 status = "disabled";
 484         };
 485
 486         spi@0,7000da00 {
 487                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 488                 reg = <0x0 0x7000da00 0x0 0x200>;
 489                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 493                 clock-names = "spi";
 494                 resets = <&tegra_car 68>;
 495                 reset-names = "spi";
 496                 dmas = <&apbdma 18>, <&apbdma 18>;
 497                 dma-names = "rx", "tx";
 498                 status = "disabled";
 499         };
 500
 501         spi@0,7000dc00 {
 502                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 503                 reg = <0x0 0x7000dc00 0x0 0x200>;
 504                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 508                 clock-names = "spi";
 509                 resets = <&tegra_car 104>;
 510                 reset-names = "spi";
 511                 dmas = <&apbdma 27>, <&apbdma 27>;
 512                 dma-names = "rx", "tx";
 513                 status = "disabled";
 514         };
 515
 516         spi@0,7000de00 {
 517                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 518                 reg = <0x0 0x7000de00 0x0 0x200>;
 519                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 523                 clock-names = "spi";
 524                 resets = <&tegra_car 105>;
 525                 reset-names = "spi";
 526                 dmas = <&apbdma 28>, <&apbdma 28>;
 527                 dma-names = "rx", "tx";
 528                 status = "disabled";
 529         };
 530
 531         rtc@0,7000e000 {
 532                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 533                 reg = <0x0 0x7000e000 0x0 0x100>;
 534                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 535                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 536         };
 537
 538         pmc@0,7000e400 {
 539                 compatible = "nvidia,tegra124-pmc";
 540                 reg = <0x0 0x7000e400 0x0 0x400>;
 541                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 542                 clock-names = "pclk", "clk32k_in";
 543         };
 544
 545         fuse@0,7000f800 {
 546                 compatible = "nvidia,tegra124-efuse";
 547                 reg = <0x0 0x7000f800 0x0 0x400>;
 548                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 549                 clock-names = "fuse";
 550                 resets = <&tegra_car 39>;
 551                 reset-names = "fuse";
 552         };
 553
 554         sata@0,70020000 {
 555                 compatible = "nvidia,tegra124-ahci";
 556
 557                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 558                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 559
 560                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 561
 562                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 563                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 564                         <&tegra_car TEGRA124_CLK_CML1>,
 565                         <&tegra_car TEGRA124_CLK_PLL_E>;
 566                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 567
 568                 resets = <&tegra_car 124>,
 569                         <&tegra_car 123>,
 570                         <&tegra_car 129>;
 571                 reset-names = "sata", "sata-oob", "sata-cold";
 572
 573                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 574                 phy-names = "sata-phy";
 575
 576                 status = "disabled";
 577         };
 578
 579         hda@0,70030000 {
 580                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 581                 reg = <0x0 0x70030000 0x0 0x10000>;
 582                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 583                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 584                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 585                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 586                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 587                 resets = <&tegra_car 125>, /* hda */
 588                          <&tegra_car 128>, /* hda2hdmi */
 589                          <&tegra_car 111>; /* hda2codec_2x */
 590                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 591                 status = "disabled";
 592         };
 593
 594         padctl: padctl@0,7009f000 {
 595                 compatible = "nvidia,tegra124-xusb-padctl";
 596                 reg = <0x0 0x7009f000 0x0 0x1000>;
 597                 resets = <&tegra_car 142>;
 598                 reset-names = "padctl";
 599
 600                 #phy-cells = <1>;
 601         };
 602
 603         sdhci@0,700b0000 {
 604                 compatible = "nvidia,tegra124-sdhci";
 605                 reg = <0x0 0x700b0000 0x0 0x200>;
 606                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 607                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 608                 resets = <&tegra_car 14>;
 609                 reset-names = "sdhci";
 610                 status = "disabled";
 611         };
 612
 613         sdhci@0,700b0200 {
 614                 compatible = "nvidia,tegra124-sdhci";
 615                 reg = <0x0 0x700b0200 0x0 0x200>;
 616                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 618                 resets = <&tegra_car 9>;
 619                 reset-names = "sdhci";
 620                 status = "disabled";
 621         };
 622
 623         sdhci@0,700b0400 {
 624                 compatible = "nvidia,tegra124-sdhci";
 625                 reg = <0x0 0x700b0400 0x0 0x200>;
 626                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 627                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 628                 resets = <&tegra_car 69>;
 629                 reset-names = "sdhci";
 630                 status = "disabled";
 631         };
 632
 633         sdhci@0,700b0600 {
 634                 compatible = "nvidia,tegra124-sdhci";
 635                 reg = <0x0 0x700b0600 0x0 0x200>;
 636                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 638                 resets = <&tegra_car 15>;
 639                 reset-names = "sdhci";
 640                 status = "disabled";
 641         };
 642
 643         ahub@0,70300000 {
 644                 compatible = "nvidia,tegra124-ahub";
 645                 reg = <0x0 0x70300000 0x0 0x200>,
 646                       <0x0 0x70300800 0x0 0x800>,
 647                       <0x0 0x70300200 0x0 0x600>;
 648                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 650                          <&tegra_car TEGRA124_CLK_APBIF>;
 651                 clock-names = "d_audio", "apbif";
 652                 resets = <&tegra_car 106>, /* d_audio */
 653                          <&tegra_car 107>, /* apbif */
 654                          <&tegra_car 30>,  /* i2s0 */
 655                          <&tegra_car 11>,  /* i2s1 */
 656                          <&tegra_car 18>,  /* i2s2 */
 657                          <&tegra_car 101>, /* i2s3 */
 658                          <&tegra_car 102>, /* i2s4 */
 659                          <&tegra_car 108>, /* dam0 */
 660                          <&tegra_car 109>, /* dam1 */
 661                          <&tegra_car 110>, /* dam2 */
 662                          <&tegra_car 10>,  /* spdif */
 663                          <&tegra_car 153>, /* amx */
 664                          <&tegra_car 185>, /* amx1 */
 665                          <&tegra_car 154>, /* adx */
 666                          <&tegra_car 180>, /* adx1 */
 667                          <&tegra_car 186>, /* afc0 */
 668                          <&tegra_car 187>, /* afc1 */
 669                          <&tegra_car 188>, /* afc2 */
 670                          <&tegra_car 189>, /* afc3 */
 671                          <&tegra_car 190>, /* afc4 */
 672                          <&tegra_car 191>; /* afc5 */
 673                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 674                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 675                               "spdif", "amx", "amx1", "adx", "adx1",
 676                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 677                 dmas = <&apbdma 1>, <&apbdma 1>,
 678                        <&apbdma 2>, <&apbdma 2>,
 679                        <&apbdma 3>, <&apbdma 3>,
 680                        <&apbdma 4>, <&apbdma 4>,
 681                        <&apbdma 6>, <&apbdma 6>,
 682                        <&apbdma 7>, <&apbdma 7>,
 683                        <&apbdma 12>, <&apbdma 12>,
 684                        <&apbdma 13>, <&apbdma 13>,
 685                        <&apbdma 14>, <&apbdma 14>,
 686                        <&apbdma 29>, <&apbdma 29>;
 687                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 688                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 689                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 690                             "rx9", "tx9";
 691                 ranges;
 692                 #address-cells = <2>;
 693                 #size-cells = <2>;
 694
 695                 tegra_i2s0: i2s@0,70301000 {
 696                         compatible = "nvidia,tegra124-i2s";
 697                         reg = <0x0 0x70301000 0x0 0x100>;
 698                         nvidia,ahub-cif-ids = <4 4>;
 699                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 700                         resets = <&tegra_car 30>;
 701                         reset-names = "i2s";
 702                         status = "disabled";
 703                 };
 704
 705                 tegra_i2s1: i2s@0,70301100 {
 706                         compatible = "nvidia,tegra124-i2s";
 707                         reg = <0x0 0x70301100 0x0 0x100>;
 708                         nvidia,ahub-cif-ids = <5 5>;
 709                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 710                         resets = <&tegra_car 11>;
 711                         reset-names = "i2s";
 712                         status = "disabled";
 713                 };
 714
 715                 tegra_i2s2: i2s@0,70301200 {
 716                         compatible = "nvidia,tegra124-i2s";
 717                         reg = <0x0 0x70301200 0x0 0x100>;
 718                         nvidia,ahub-cif-ids = <6 6>;
 719                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 720                         resets = <&tegra_car 18>;
 721                         reset-names = "i2s";
 722                         status = "disabled";
 723                 };
 724
 725                 tegra_i2s3: i2s@0,70301300 {
 726                         compatible = "nvidia,tegra124-i2s";
 727                         reg = <0x0 0x70301300 0x0 0x100>;
 728                         nvidia,ahub-cif-ids = <7 7>;
 729                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 730                         resets = <&tegra_car 101>;
 731                         reset-names = "i2s";
 732                         status = "disabled";
 733                 };
 734
 735                 tegra_i2s4: i2s@0,70301400 {
 736                         compatible = "nvidia,tegra124-i2s";
 737                         reg = <0x0 0x70301400 0x0 0x100>;
 738                         nvidia,ahub-cif-ids = <8 8>;
 739                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 740                         resets = <&tegra_car 102>;
 741                         reset-names = "i2s";
 742                         status = "disabled";
 743                 };
 744         };
 745
 746         usb@0,7d000000 {
 747                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 748                 reg = <0x0 0x7d000000 0x0 0x4000>;
 749                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 750                 phy_type = "utmi";
 751                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 752                 resets = <&tegra_car 22>;
 753                 reset-names = "usb";
 754                 nvidia,phy = <&phy1>;
 755                 status = "disabled";
 756         };
 757
 758         phy1: usb-phy@0,7d000000 {
 759                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 760                 reg = <0x0 0x7d000000 0x0 0x4000>,
 761                       <0x0 0x7d000000 0x0 0x4000>;
 762                 phy_type = "utmi";
 763                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 764                          <&tegra_car TEGRA124_CLK_PLL_U>,
 765                          <&tegra_car TEGRA124_CLK_USBD>;
 766                 clock-names = "reg", "pll_u", "utmi-pads";
 767                 resets = <&tegra_car 59>, <&tegra_car 22>;
 768                 reset-names = "usb", "utmi-pads";
 769                 nvidia,hssync-start-delay = <0>;
 770                 nvidia,idle-wait-delay = <17>;
 771                 nvidia,elastic-limit = <16>;
 772                 nvidia,term-range-adj = <6>;
 773                 nvidia,xcvr-setup = <9>;
 774                 nvidia,xcvr-lsfslew = <0>;
 775                 nvidia,xcvr-lsrslew = <3>;
 776                 nvidia,hssquelch-level = <2>;
 777                 nvidia,hsdiscon-level = <5>;
 778                 nvidia,xcvr-hsslew = <12>;
 779                 status = "disabled";
 780         };
 781
 782         usb@0,7d004000 {
 783                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 784                 reg = <0x0 0x7d004000 0x0 0x4000>;
 785                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 786                 phy_type = "utmi";
 787                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 788                 resets = <&tegra_car 58>;
 789                 reset-names = "usb";
 790                 nvidia,phy = <&phy2>;
 791                 status = "disabled";
 792         };
 793
 794         phy2: usb-phy@0,7d004000 {
 795                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 796                 reg = <0x0 0x7d004000 0x0 0x4000>,
 797                       <0x0 0x7d000000 0x0 0x4000>;
 798                 phy_type = "utmi";
 799                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 800                          <&tegra_car TEGRA124_CLK_PLL_U>,
 801                          <&tegra_car TEGRA124_CLK_USBD>;
 802                 clock-names = "reg", "pll_u", "utmi-pads";
 803                 resets = <&tegra_car 22>, <&tegra_car 22>;
 804                 reset-names = "usb", "utmi-pads";
 805                 nvidia,hssync-start-delay = <0>;
 806                 nvidia,idle-wait-delay = <17>;
 807                 nvidia,elastic-limit = <16>;
 808                 nvidia,term-range-adj = <6>;
 809                 nvidia,xcvr-setup = <9>;
 810                 nvidia,xcvr-lsfslew = <0>;
 811                 nvidia,xcvr-lsrslew = <3>;
 812                 nvidia,hssquelch-level = <2>;
 813                 nvidia,hsdiscon-level = <5>;
 814                 nvidia,xcvr-hsslew = <12>;
 815                 nvidia,has-utmi-pad-registers;
 816                 status = "disabled";
 817         };
 818
 819         usb@0,7d008000 {
 820                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 821                 reg = <0x0 0x7d008000 0x0 0x4000>;
 822                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 823                 phy_type = "utmi";
 824                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 825                 resets = <&tegra_car 59>;
 826                 reset-names = "usb";
 827                 nvidia,phy = <&phy3>;
 828                 status = "disabled";
 829         };
 830
 831         phy3: usb-phy@0,7d008000 {
 832                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 833                 reg = <0x0 0x7d008000 0x0 0x4000>,
 834                       <0x0 0x7d000000 0x0 0x4000>;
 835                 phy_type = "utmi";
 836                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 837                          <&tegra_car TEGRA124_CLK_PLL_U>,
 838                          <&tegra_car TEGRA124_CLK_USBD>;
 839                 clock-names = "reg", "pll_u", "utmi-pads";
 840                 resets = <&tegra_car 58>, <&tegra_car 22>;
 841                 reset-names = "usb", "utmi-pads";
 842                 nvidia,hssync-start-delay = <0>;
 843                 nvidia,idle-wait-delay = <17>;
 844                 nvidia,elastic-limit = <16>;
 845                 nvidia,term-range-adj = <6>;
 846                 nvidia,xcvr-setup = <9>;
 847                 nvidia,xcvr-lsfslew = <0>;
 848                 nvidia,xcvr-lsrslew = <3>;
 849                 nvidia,hssquelch-level = <2>;
 850                 nvidia,hsdiscon-level = <5>;
 851                 nvidia,xcvr-hsslew = <12>;
 852                 status = "disabled";
 853         };
 854
 855         cpus {
 856                 #address-cells = <1>;
 857                 #size-cells = <0>;
 858
 859                 cpu@0 {
 860                         device_type = "cpu";
 861                         compatible = "arm,cortex-a15";
 862                         reg = <0>;
 863                 };
 864
 865                 cpu@1 {
 866                         device_type = "cpu";
 867                         compatible = "arm,cortex-a15";
 868                         reg = <1>;
 869                 };
 870
 871                 cpu@2 {
 872                         device_type = "cpu";
 873                         compatible = "arm,cortex-a15";
 874                         reg = <2>;
 875                 };
 876
 877                 cpu@3 {
 878                         device_type = "cpu";
 879                         compatible = "arm,cortex-a15";
 880                         reg = <3>;
 881                 };
 882         };
 883
 884         timer {
 885                 compatible = "arm,armv7-timer";
 886                 interrupts = <GIC_PPI 13
 887                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 888                              <GIC_PPI 14
 889                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 890                              <GIC_PPI 11
 891                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 892                              <GIC_PPI 10
 893                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 894         };
 895 };