arch/arm/boot/dts/tegra114.dtsi

   1 #include <dt-bindings/clock/tegra114-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra114";
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17         };
  18
  19         host1x@50000000 {
  20                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  21                 reg = <0x50000000 0x00028000>;
  22                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  23                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  24                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  25                 resets = <&tegra_car 28>;
  26                 reset-names = "host1x";
  27
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 ranges = <0x54000000 0x54000000 0x01000000>;
  32
  33                 gr2d@54140000 {
  34                         compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
  35                         reg = <0x54140000 0x00040000>;
  36                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  37                         clocks = <&tegra_car TEGRA114_CLK_GR2D>;
  38                         resets = <&tegra_car 21>;
  39                         reset-names = "2d";
  40                 };
  41
  42                 gr3d@54180000 {
  43                         compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
  44                         reg = <0x54180000 0x00040000>;
  45                         clocks = <&tegra_car TEGRA114_CLK_GR3D>;
  46                         resets = <&tegra_car 24>;
  47                         reset-names = "3d";
  48                 };
  49
  50                 dc@54200000 {
  51                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  52                         reg = <0x54200000 0x00040000>;
  53                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  55                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  56                         clock-names = "dc", "parent";
  57                         resets = <&tegra_car 27>;
  58                         reset-names = "dc";
  59
  60                         nvidia,head = <0>;
  61
  62                         rgb {
  63                                 status = "disabled";
  64                         };
  65                 };
  66
  67                 dc@54240000 {
  68                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  69                         reg = <0x54240000 0x00040000>;
  70                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  72                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  73                         clock-names = "dc", "parent";
  74                         resets = <&tegra_car 26>;
  75                         reset-names = "dc";
  76
  77                         nvidia,head = <1>;
  78
  79                         rgb {
  80                                 status = "disabled";
  81                         };
  82                 };
  83
  84                 hdmi@54280000 {
  85                         compatible = "nvidia,tegra114-hdmi";
  86                         reg = <0x54280000 0x00040000>;
  87                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  88                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  89                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  90                         clock-names = "hdmi", "parent";
  91                         resets = <&tegra_car 51>;
  92                         reset-names = "hdmi";
  93                         status = "disabled";
  94                 };
  95
  96                 dsi@54300000 {
  97                         compatible = "nvidia,tegra114-dsi";
  98                         reg = <0x54300000 0x00040000>;
  99                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
 100                                  <&tegra_car TEGRA114_CLK_DSIALP>,
 101                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
 102                         clock-names = "dsi", "lp", "parent";
 103                         resets = <&tegra_car 48>;
 104                         reset-names = "dsi";
 105                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
 106                         status = "disabled";
 107
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                 };
 111
 112                 dsi@54400000 {
 113                         compatible = "nvidia,tegra114-dsi";
 114                         reg = <0x54400000 0x00040000>;
 115                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
 116                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
 117                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 118                         clock-names = "dsi", "lp", "parent";
 119                         resets = <&tegra_car 82>;
 120                         reset-names = "dsi";
 121                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 122                         status = "disabled";
 123
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                 };
 127         };
 128
 129         gic: interrupt-controller@50041000 {
 130                 compatible = "arm,cortex-a15-gic";
 131                 #interrupt-cells = <3>;
 132                 interrupt-controller;
 133                 reg = <0x50041000 0x1000>,
 134                       <0x50042000 0x1000>,
 135                       <0x50044000 0x2000>,
 136                       <0x50046000 0x2000>;
 137                 interrupts = <GIC_PPI 9
 138                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 139         };
 140
 141         timer@60005000 {
 142                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 143                 reg = <0x60005000 0x400>;
 144                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 151         };
 152
 153         tegra_car: clock@60006000 {
 154                 compatible = "nvidia,tegra114-car";
 155                 reg = <0x60006000 0x1000>;
 156                 #clock-cells = <1>;
 157                 #reset-cells = <1>;
 158         };
 159
 160         apbdma: dma@6000a000 {
 161                 compatible = "nvidia,tegra114-apbdma";
 162                 reg = <0x6000a000 0x1400>;
 163                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 196                 resets = <&tegra_car 34>;
 197                 reset-names = "dma";
 198                 #dma-cells = <1>;
 199         };
 200
 201         ahb: ahb@6000c004 {
 202                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 203                 reg = <0x6000c004 0x14c>;
 204         };
 205
 206         gpio: gpio@6000d000 {
 207                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 208                 reg = <0x6000d000 0x1000>;
 209                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 217                 #gpio-cells = <2>;
 218                 gpio-controller;
 219                 #interrupt-cells = <2>;
 220                 interrupt-controller;
 221         };
 222
 223         pinmux: pinmux@70000868 {
 224                 compatible = "nvidia,tegra114-pinmux";
 225                 reg = <0x70000868 0x148         /* Pad control registers */
 226                        0x70003000 0x40c>;       /* Mux registers */
 227         };
 228
 229         /*
 230          * There are two serial driver i.e. 8250 based simple serial
 231          * driver and APB DMA based serial driver for higher baudrate
 232          * and performace. To enable the 8250 based driver, the compatible
 233          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 234          * the APB DMA based serial driver, the comptible is
 235          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 236          */
 237         uarta: serial@70006000 {
 238                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 239                 reg = <0x70006000 0x40>;
 240                 reg-shift = <2>;
 241                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 242                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 243                 resets = <&tegra_car 6>;
 244                 reset-names = "serial";
 245                 dmas = <&apbdma 8>, <&apbdma 8>;
 246                 dma-names = "rx", "tx";
 247                 status = "disabled";
 248         };
 249
 250         uartb: serial@70006040 {
 251                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 252                 reg = <0x70006040 0x40>;
 253                 reg-shift = <2>;
 254                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 256                 resets = <&tegra_car 7>;
 257                 reset-names = "serial";
 258                 dmas = <&apbdma 9>, <&apbdma 9>;
 259                 dma-names = "rx", "tx";
 260                 status = "disabled";
 261         };
 262
 263         uartc: serial@70006200 {
 264                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 265                 reg = <0x70006200 0x100>;
 266                 reg-shift = <2>;
 267                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 269                 resets = <&tegra_car 55>;
 270                 reset-names = "serial";
 271                 dmas = <&apbdma 10>, <&apbdma 10>;
 272                 dma-names = "rx", "tx";
 273                 status = "disabled";
 274         };
 275
 276         uartd: serial@70006300 {
 277                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 278                 reg = <0x70006300 0x100>;
 279                 reg-shift = <2>;
 280                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 282                 resets = <&tegra_car 65>;
 283                 reset-names = "serial";
 284                 dmas = <&apbdma 19>, <&apbdma 19>;
 285                 dma-names = "rx", "tx";
 286                 status = "disabled";
 287         };
 288
 289         pwm: pwm@7000a000 {
 290                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 291                 reg = <0x7000a000 0x100>;
 292                 #pwm-cells = <2>;
 293                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 294                 resets = <&tegra_car 17>;
 295                 reset-names = "pwm";
 296                 status = "disabled";
 297         };
 298
 299         i2c@7000c000 {
 300                 compatible = "nvidia,tegra114-i2c";
 301                 reg = <0x7000c000 0x100>;
 302                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 306                 clock-names = "div-clk";
 307                 resets = <&tegra_car 12>;
 308                 reset-names = "i2c";
 309                 dmas = <&apbdma 21>, <&apbdma 21>;
 310                 dma-names = "rx", "tx";
 311                 status = "disabled";
 312         };
 313
 314         i2c@7000c400 {
 315                 compatible = "nvidia,tegra114-i2c";
 316                 reg = <0x7000c400 0x100>;
 317                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 321                 clock-names = "div-clk";
 322                 resets = <&tegra_car 54>;
 323                 reset-names = "i2c";
 324                 dmas = <&apbdma 22>, <&apbdma 22>;
 325                 dma-names = "rx", "tx";
 326                 status = "disabled";
 327         };
 328
 329         i2c@7000c500 {
 330                 compatible = "nvidia,tegra114-i2c";
 331                 reg = <0x7000c500 0x100>;
 332                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 336                 clock-names = "div-clk";
 337                 resets = <&tegra_car 67>;
 338                 reset-names = "i2c";
 339                 dmas = <&apbdma 23>, <&apbdma 23>;
 340                 dma-names = "rx", "tx";
 341                 status = "disabled";
 342         };
 343
 344         i2c@7000c700 {
 345                 compatible = "nvidia,tegra114-i2c";
 346                 reg = <0x7000c700 0x100>;
 347                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 351                 clock-names = "div-clk";
 352                 resets = <&tegra_car 103>;
 353                 reset-names = "i2c";
 354                 dmas = <&apbdma 26>, <&apbdma 26>;
 355                 dma-names = "rx", "tx";
 356                 status = "disabled";
 357         };
 358
 359         i2c@7000d000 {
 360                 compatible = "nvidia,tegra114-i2c";
 361                 reg = <0x7000d000 0x100>;
 362                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 363                 #address-cells = <1>;
 364                 #size-cells = <0>;
 365                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 366                 clock-names = "div-clk";
 367                 resets = <&tegra_car 47>;
 368                 reset-names = "i2c";
 369                 dmas = <&apbdma 24>, <&apbdma 24>;
 370                 dma-names = "rx", "tx";
 371                 status = "disabled";
 372         };
 373
 374         spi@7000d400 {
 375                 compatible = "nvidia,tegra114-spi";
 376                 reg = <0x7000d400 0x200>;
 377                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 381                 clock-names = "spi";
 382                 resets = <&tegra_car 41>;
 383                 reset-names = "spi";
 384                 dmas = <&apbdma 15>, <&apbdma 15>;
 385                 dma-names = "rx", "tx";
 386                 status = "disabled";
 387         };
 388
 389         spi@7000d600 {
 390                 compatible = "nvidia,tegra114-spi";
 391                 reg = <0x7000d600 0x200>;
 392                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 396                 clock-names = "spi";
 397                 resets = <&tegra_car 44>;
 398                 reset-names = "spi";
 399                 dmas = <&apbdma 16>, <&apbdma 16>;
 400                 dma-names = "rx", "tx";
 401                 status = "disabled";
 402         };
 403
 404         spi@7000d800 {
 405                 compatible = "nvidia,tegra114-spi";
 406                 reg = <0x7000d800 0x200>;
 407                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 411                 clock-names = "spi";
 412                 resets = <&tegra_car 46>;
 413                 reset-names = "spi";
 414                 dmas = <&apbdma 17>, <&apbdma 17>;
 415                 dma-names = "rx", "tx";
 416                 status = "disabled";
 417         };
 418
 419         spi@7000da00 {
 420                 compatible = "nvidia,tegra114-spi";
 421                 reg = <0x7000da00 0x200>;
 422                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 426                 clock-names = "spi";
 427                 resets = <&tegra_car 68>;
 428                 reset-names = "spi";
 429                 dmas = <&apbdma 18>, <&apbdma 18>;
 430                 dma-names = "rx", "tx";
 431                 status = "disabled";
 432         };
 433
 434         spi@7000dc00 {
 435                 compatible = "nvidia,tegra114-spi";
 436                 reg = <0x7000dc00 0x200>;
 437                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 441                 clock-names = "spi";
 442                 resets = <&tegra_car 104>;
 443                 reset-names = "spi";
 444                 dmas = <&apbdma 27>, <&apbdma 27>;
 445                 dma-names = "rx", "tx";
 446                 status = "disabled";
 447         };
 448
 449         spi@7000de00 {
 450                 compatible = "nvidia,tegra114-spi";
 451                 reg = <0x7000de00 0x200>;
 452                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 456                 clock-names = "spi";
 457                 resets = <&tegra_car 105>;
 458                 reset-names = "spi";
 459                 dmas = <&apbdma 28>, <&apbdma 28>;
 460                 dma-names = "rx", "tx";
 461                 status = "disabled";
 462         };
 463
 464         rtc@7000e000 {
 465                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 466                 reg = <0x7000e000 0x100>;
 467                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 469         };
 470
 471         kbc@7000e200 {
 472                 compatible = "nvidia,tegra114-kbc";
 473                 reg = <0x7000e200 0x100>;
 474                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 475                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 476                 resets = <&tegra_car 36>;
 477                 reset-names = "kbc";
 478                 status = "disabled";
 479         };
 480
 481         pmc@7000e400 {
 482                 compatible = "nvidia,tegra114-pmc";
 483                 reg = <0x7000e400 0x400>;
 484                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 485                 clock-names = "pclk", "clk32k_in";
 486         };
 487
 488         iommu@70019010 {
 489                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 490                 reg = <0x70019010 0x02c
 491                        0x700191f0 0x010
 492                        0x70019228 0x074>;
 493                 nvidia,#asids = <4>;
 494                 dma-window = <0 0x40000000>;
 495                 nvidia,swgroups = <0x18659fe>;
 496                 nvidia,ahb = <&ahb>;
 497         };
 498
 499         ahub@70080000 {
 500                 compatible = "nvidia,tegra114-ahub";
 501                 reg = <0x70080000 0x200>,
 502                       <0x70080200 0x100>,
 503                       <0x70081000 0x200>;
 504                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 506                          <&tegra_car TEGRA114_CLK_APBIF>;
 507                 clock-names = "d_audio", "apbif";
 508                 resets = <&tegra_car 106>, /* d_audio */
 509                          <&tegra_car 107>, /* apbif */
 510                          <&tegra_car 30>,  /* i2s0 */
 511                          <&tegra_car 11>,  /* i2s1 */
 512                          <&tegra_car 18>,  /* i2s2 */
 513                          <&tegra_car 101>, /* i2s3 */
 514                          <&tegra_car 102>, /* i2s4 */
 515                          <&tegra_car 108>, /* dam0 */
 516                          <&tegra_car 109>, /* dam1 */
 517                          <&tegra_car 110>, /* dam2 */
 518                          <&tegra_car 10>,  /* spdif */
 519                          <&tegra_car 153>, /* amx */
 520                          <&tegra_car 154>; /* adx */
 521                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 522                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 523                               "spdif", "amx", "adx";
 524                 dmas = <&apbdma 1>, <&apbdma 1>,
 525                        <&apbdma 2>, <&apbdma 2>,
 526                        <&apbdma 3>, <&apbdma 3>,
 527                        <&apbdma 4>, <&apbdma 4>,
 528                        <&apbdma 6>, <&apbdma 6>,
 529                        <&apbdma 7>, <&apbdma 7>,
 530                        <&apbdma 12>, <&apbdma 12>,
 531                        <&apbdma 13>, <&apbdma 13>,
 532                        <&apbdma 14>, <&apbdma 14>,
 533                        <&apbdma 29>, <&apbdma 29>;
 534                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 535                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 536                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 537                             "rx9", "tx9";
 538                 ranges;
 539                 #address-cells = <1>;
 540                 #size-cells = <1>;
 541
 542                 tegra_i2s0: i2s@70080300 {
 543                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 544                         reg = <0x70080300 0x100>;
 545                         nvidia,ahub-cif-ids = <4 4>;
 546                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 547                         resets = <&tegra_car 30>;
 548                         reset-names = "i2s";
 549                         status = "disabled";
 550                 };
 551
 552                 tegra_i2s1: i2s@70080400 {
 553                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 554                         reg = <0x70080400 0x100>;
 555                         nvidia,ahub-cif-ids = <5 5>;
 556                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 557                         resets = <&tegra_car 11>;
 558                         reset-names = "i2s";
 559                         status = "disabled";
 560                 };
 561
 562                 tegra_i2s2: i2s@70080500 {
 563                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 564                         reg = <0x70080500 0x100>;
 565                         nvidia,ahub-cif-ids = <6 6>;
 566                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 567                         resets = <&tegra_car 18>;
 568                         reset-names = "i2s";
 569                         status = "disabled";
 570                 };
 571
 572                 tegra_i2s3: i2s@70080600 {
 573                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 574                         reg = <0x70080600 0x100>;
 575                         nvidia,ahub-cif-ids = <7 7>;
 576                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 577                         resets = <&tegra_car 101>;
 578                         reset-names = "i2s";
 579                         status = "disabled";
 580                 };
 581
 582                 tegra_i2s4: i2s@70080700 {
 583                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 584                         reg = <0x70080700 0x100>;
 585                         nvidia,ahub-cif-ids = <8 8>;
 586                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 587                         resets = <&tegra_car 102>;
 588                         reset-names = "i2s";
 589                         status = "disabled";
 590                 };
 591         };
 592
 593         mipi: mipi@700e3000 {
 594                 compatible = "nvidia,tegra114-mipi";
 595                 reg = <0x700e3000 0x100>;
 596                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 597                 #nvidia,mipi-calibrate-cells = <1>;
 598         };
 599
 600         sdhci@78000000 {
 601                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 602                 reg = <0x78000000 0x200>;
 603                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 604                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 605                 resets = <&tegra_car 14>;
 606                 reset-names = "sdhci";
 607                 status = "disabled";
 608         };
 609
 610         sdhci@78000200 {
 611                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 612                 reg = <0x78000200 0x200>;
 613                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 615                 resets = <&tegra_car 9>;
 616                 reset-names = "sdhci";
 617                 status = "disabled";
 618         };
 619
 620         sdhci@78000400 {
 621                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 622                 reg = <0x78000400 0x200>;
 623                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 625                 resets = <&tegra_car 69>;
 626                 reset-names = "sdhci";
 627                 status = "disabled";
 628         };
 629
 630         sdhci@78000600 {
 631                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 632                 reg = <0x78000600 0x200>;
 633                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 635                 resets = <&tegra_car 15>;
 636                 reset-names = "sdhci";
 637                 status = "disabled";
 638         };
 639
 640         usb@7d000000 {
 641                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 642                 reg = <0x7d000000 0x4000>;
 643                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 644                 phy_type = "utmi";
 645                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 646                 resets = <&tegra_car 22>;
 647                 reset-names = "usb";
 648                 nvidia,phy = <&phy1>;
 649                 status = "disabled";
 650         };
 651
 652         phy1: usb-phy@7d000000 {
 653                 compatible = "nvidia,tegra30-usb-phy";
 654                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 655                 phy_type = "utmi";
 656                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 657                          <&tegra_car TEGRA114_CLK_PLL_U>,
 658                          <&tegra_car TEGRA114_CLK_USBD>;
 659                 clock-names = "reg", "pll_u", "utmi-pads";
 660                 nvidia,hssync-start-delay = <0>;
 661                 nvidia,idle-wait-delay = <17>;
 662                 nvidia,elastic-limit = <16>;
 663                 nvidia,term-range-adj = <6>;
 664                 nvidia,xcvr-setup = <9>;
 665                 nvidia,xcvr-lsfslew = <0>;
 666                 nvidia,xcvr-lsrslew = <3>;
 667                 nvidia,hssquelch-level = <2>;
 668                 nvidia,hsdiscon-level = <5>;
 669                 nvidia,xcvr-hsslew = <12>;
 670                 status = "disabled";
 671         };
 672
 673         usb@7d008000 {
 674                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 675                 reg = <0x7d008000 0x4000>;
 676                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 677                 phy_type = "utmi";
 678                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 679                 resets = <&tegra_car 59>;
 680                 reset-names = "usb";
 681                 nvidia,phy = <&phy3>;
 682                 status = "disabled";
 683         };
 684
 685         phy3: usb-phy@7d008000 {
 686                 compatible = "nvidia,tegra30-usb-phy";
 687                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 688                 phy_type = "utmi";
 689                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 690                          <&tegra_car TEGRA114_CLK_PLL_U>,
 691                          <&tegra_car TEGRA114_CLK_USBD>;
 692                 clock-names = "reg", "pll_u", "utmi-pads";
 693                 nvidia,hssync-start-delay = <0>;
 694                 nvidia,idle-wait-delay = <17>;
 695                 nvidia,elastic-limit = <16>;
 696                 nvidia,term-range-adj = <6>;
 697                 nvidia,xcvr-setup = <9>;
 698                 nvidia,xcvr-lsfslew = <0>;
 699                 nvidia,xcvr-lsrslew = <3>;
 700                 nvidia,hssquelch-level = <2>;
 701                 nvidia,hsdiscon-level = <5>;
 702                 nvidia,xcvr-hsslew = <12>;
 703                 status = "disabled";
 704         };
 705
 706         cpus {
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709
 710                 cpu@0 {
 711                         device_type = "cpu";
 712                         compatible = "arm,cortex-a15";
 713                         reg = <0>;
 714                 };
 715
 716                 cpu@1 {
 717                         device_type = "cpu";
 718                         compatible = "arm,cortex-a15";
 719                         reg = <1>;
 720                 };
 721
 722                 cpu@2 {
 723                         device_type = "cpu";
 724                         compatible = "arm,cortex-a15";
 725                         reg = <2>;
 726                 };
 727
 728                 cpu@3 {
 729                         device_type = "cpu";
 730                         compatible = "arm,cortex-a15";
 731                         reg = <3>;
 732                 };
 733         };
 734
 735         timer {
 736                 compatible = "arm,armv7-timer";
 737                 interrupts =
 738                         <GIC_PPI 13
 739                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 740                         <GIC_PPI 14
 741                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 742                         <GIC_PPI 11
 743                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 744                         <GIC_PPI 10
 745                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 746         };
 747 };