arch/arm/boot/dts/sunxi-h3-h5.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  46
  47 / {
  48         interrupt-parent = <&gic>;
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         clocks {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 ranges;
  56
  57                 osc24M: osc24M_clk {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <24000000>;
  61                         clock-output-names = "osc24M";
  62                 };
  63
  64                 osc32k: osc32k_clk {
  65                         #clock-cells = <0>;
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32768>;
  68                         clock-output-names = "osc32k";
  69                 };
  70
  71                 iosc: internal-osc-clk {
  72                         #clock-cells = <0>;
  73                         compatible = "fixed-clock";
  74                         clock-frequency = <16000000>;
  75                         clock-accuracy = <300000000>;
  76                         clock-output-names = "iosc";
  77                 };
  78         };
  79
  80         soc {
  81                 compatible = "simple-bus";
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 ranges;
  85
  86                 dma: dma-controller@01c02000 {
  87                         compatible = "allwinner,sun8i-h3-dma";
  88                         reg = <0x01c02000 0x1000>;
  89                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  90                         clocks = <&ccu CLK_BUS_DMA>;
  91                         resets = <&ccu RST_BUS_DMA>;
  92                         #dma-cells = <1>;
  93                 };
  94
  95                 mmc0: mmc@01c0f000 {
  96                         /* compatible and clocks are in per SoC .dtsi file */
  97                         reg = <0x01c0f000 0x1000>;
  98                         resets = <&ccu RST_BUS_MMC0>;
  99                         reset-names = "ahb";
 100                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 101                         status = "disabled";
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                 };
 105
 106                 mmc1: mmc@01c10000 {
 107                         /* compatible and clocks are in per SoC .dtsi file */
 108                         reg = <0x01c10000 0x1000>;
 109                         resets = <&ccu RST_BUS_MMC1>;
 110                         reset-names = "ahb";
 111                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 112                         status = "disabled";
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                 };
 116
 117                 mmc2: mmc@01c11000 {
 118                         /* compatible and clocks are in per SoC .dtsi file */
 119                         reg = <0x01c11000 0x1000>;
 120                         resets = <&ccu RST_BUS_MMC2>;
 121                         reset-names = "ahb";
 122                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 123                         status = "disabled";
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                 };
 127
 128                 usb_otg: usb@01c19000 {
 129                         compatible = "allwinner,sun8i-h3-musb";
 130                         reg = <0x01c19000 0x400>;
 131                         clocks = <&ccu CLK_BUS_OTG>;
 132                         resets = <&ccu RST_BUS_OTG>;
 133                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 134                         interrupt-names = "mc";
 135                         phys = <&usbphy 0>;
 136                         phy-names = "usb";
 137                         extcon = <&usbphy 0>;
 138                         status = "disabled";
 139                 };
 140
 141                 usbphy: phy@01c19400 {
 142                         compatible = "allwinner,sun8i-h3-usb-phy";
 143                         reg = <0x01c19400 0x2c>,
 144                               <0x01c1a800 0x4>,
 145                               <0x01c1b800 0x4>,
 146                               <0x01c1c800 0x4>,
 147                               <0x01c1d800 0x4>;
 148                         reg-names = "phy_ctrl",
 149                                     "pmu0",
 150                                     "pmu1",
 151                                     "pmu2",
 152                                     "pmu3";
 153                         clocks = <&ccu CLK_USB_PHY0>,
 154                                  <&ccu CLK_USB_PHY1>,
 155                                  <&ccu CLK_USB_PHY2>,
 156                                  <&ccu CLK_USB_PHY3>;
 157                         clock-names = "usb0_phy",
 158                                       "usb1_phy",
 159                                       "usb2_phy",
 160                                       "usb3_phy";
 161                         resets = <&ccu RST_USB_PHY0>,
 162                                  <&ccu RST_USB_PHY1>,
 163                                  <&ccu RST_USB_PHY2>,
 164                                  <&ccu RST_USB_PHY3>;
 165                         reset-names = "usb0_reset",
 166                                       "usb1_reset",
 167                                       "usb2_reset",
 168                                       "usb3_reset";
 169                         status = "disabled";
 170                         #phy-cells = <1>;
 171                 };
 172
 173                 ehci0: usb@01c1a000 {
 174                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 175                         reg = <0x01c1a000 0x100>;
 176                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 177                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 178                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 179                         status = "disabled";
 180                 };
 181
 182                 ohci0: usb@01c1a400 {
 183                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 184                         reg = <0x01c1a400 0x100>;
 185                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 186                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 187                                  <&ccu CLK_USB_OHCI0>;
 188                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 189                         status = "disabled";
 190                 };
 191
 192                 ehci1: usb@01c1b000 {
 193                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 194                         reg = <0x01c1b000 0x100>;
 195                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 197                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 198                         phys = <&usbphy 1>;
 199                         phy-names = "usb";
 200                         status = "disabled";
 201                 };
 202
 203                 ohci1: usb@01c1b400 {
 204                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 205                         reg = <0x01c1b400 0x100>;
 206                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 208                                  <&ccu CLK_USB_OHCI1>;
 209                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 210                         phys = <&usbphy 1>;
 211                         phy-names = "usb";
 212                         status = "disabled";
 213                 };
 214
 215                 ehci2: usb@01c1c000 {
 216                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 217                         reg = <0x01c1c000 0x100>;
 218                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 220                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 221                         phys = <&usbphy 2>;
 222                         phy-names = "usb";
 223                         status = "disabled";
 224                 };
 225
 226                 ohci2: usb@01c1c400 {
 227                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 228                         reg = <0x01c1c400 0x100>;
 229                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 230                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 231                                  <&ccu CLK_USB_OHCI2>;
 232                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 233                         phys = <&usbphy 2>;
 234                         phy-names = "usb";
 235                         status = "disabled";
 236                 };
 237
 238                 ehci3: usb@01c1d000 {
 239                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 240                         reg = <0x01c1d000 0x100>;
 241                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 243                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 244                         phys = <&usbphy 3>;
 245                         phy-names = "usb";
 246                         status = "disabled";
 247                 };
 248
 249                 ohci3: usb@01c1d400 {
 250                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 251                         reg = <0x01c1d400 0x100>;
 252                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 254                                  <&ccu CLK_USB_OHCI3>;
 255                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 256                         phys = <&usbphy 3>;
 257                         phy-names = "usb";
 258                         status = "disabled";
 259                 };
 260
 261                 ccu: clock@01c20000 {
 262                         /* compatible is in per SoC .dtsi file */
 263                         reg = <0x01c20000 0x400>;
 264                         clocks = <&osc24M>, <&osc32k>;
 265                         clock-names = "hosc", "losc";
 266                         #clock-cells = <1>;
 267                         #reset-cells = <1>;
 268                 };
 269
 270                 pio: pinctrl@01c20800 {
 271                         /* compatible is in per SoC .dtsi file */
 272                         reg = <0x01c20800 0x400>;
 273                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 276                         clock-names = "apb", "hosc", "losc";
 277                         gpio-controller;
 278                         #gpio-cells = <3>;
 279                         interrupt-controller;
 280                         #interrupt-cells = <3>;
 281
 282                         i2c0_pins: i2c0 {
 283                                 pins = "PA11", "PA12";
 284                                 function = "i2c0";
 285                         };
 286
 287                         i2c1_pins: i2c1 {
 288                                 pins = "PA18", "PA19";
 289                                 function = "i2c1";
 290                         };
 291
 292                         i2c2_pins: i2c2 {
 293                                 pins = "PE12", "PE13";
 294                                 function = "i2c2";
 295                         };
 296
 297                         mmc0_pins_a: mmc0@0 {
 298                                 pins = "PF0", "PF1", "PF2", "PF3",
 299                                        "PF4", "PF5";
 300                                 function = "mmc0";
 301                                 drive-strength = <30>;
 302                                 bias-pull-up;
 303                         };
 304
 305                         mmc0_cd_pin: mmc0_cd_pin@0 {
 306                                 pins = "PF6";
 307                                 function = "gpio_in";
 308                                 bias-pull-up;
 309                         };
 310
 311                         mmc1_pins_a: mmc1@0 {
 312                                 pins = "PG0", "PG1", "PG2", "PG3",
 313                                        "PG4", "PG5";
 314                                 function = "mmc1";
 315                                 drive-strength = <30>;
 316                                 bias-pull-up;
 317                         };
 318
 319                         mmc2_8bit_pins: mmc2_8bit {
 320                                 pins = "PC5", "PC6", "PC8",
 321                                        "PC9", "PC10", "PC11",
 322                                        "PC12", "PC13", "PC14",
 323                                        "PC15", "PC16";
 324                                 function = "mmc2";
 325                                 drive-strength = <30>;
 326                                 bias-pull-up;
 327                         };
 328
 329                         spdif_tx_pins_a: spdif@0 {
 330                                 pins = "PA17";
 331                                 function = "spdif";
 332                         };
 333
 334                         spi0_pins: spi0 {
 335                                 pins = "PC0", "PC1", "PC2", "PC3";
 336                                 function = "spi0";
 337                         };
 338
 339                         spi1_pins: spi1 {
 340                                 pins = "PA15", "PA16", "PA14", "PA13";
 341                                 function = "spi1";
 342                         };
 343
 344                         uart0_pins_a: uart0@0 {
 345                                 pins = "PA4", "PA5";
 346                                 function = "uart0";
 347                         };
 348
 349                         uart1_pins: uart1 {
 350                                 pins = "PG6", "PG7";
 351                                 function = "uart1";
 352                         };
 353
 354                         uart1_rts_cts_pins: uart1_rts_cts {
 355                                 pins = "PG8", "PG9";
 356                                 function = "uart1";
 357                         };
 358
 359                         uart2_pins: uart2 {
 360                                 pins = "PA0", "PA1";
 361                                 function = "uart2";
 362                         };
 363
 364                         uart3_pins: uart3 {
 365                                 pins = "PA13", "PA14";
 366                                 function = "uart3";
 367                         };
 368                 };
 369
 370                 timer@01c20c00 {
 371                         compatible = "allwinner,sun4i-a10-timer";
 372                         reg = <0x01c20c00 0xa0>;
 373                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 374                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&osc24M>;
 376                 };
 377
 378                 spi0: spi@01c68000 {
 379                         compatible = "allwinner,sun8i-h3-spi";
 380                         reg = <0x01c68000 0x1000>;
 381                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 383                         clock-names = "ahb", "mod";
 384                         dmas = <&dma 23>, <&dma 23>;
 385                         dma-names = "rx", "tx";
 386                         pinctrl-names = "default";
 387                         pinctrl-0 = <&spi0_pins>;
 388                         resets = <&ccu RST_BUS_SPI0>;
 389                         status = "disabled";
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                 };
 393
 394                 spi1: spi@01c69000 {
 395                         compatible = "allwinner,sun8i-h3-spi";
 396                         reg = <0x01c69000 0x1000>;
 397                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 399                         clock-names = "ahb", "mod";
 400                         dmas = <&dma 24>, <&dma 24>;
 401                         dma-names = "rx", "tx";
 402                         pinctrl-names = "default";
 403                         pinctrl-0 = <&spi1_pins>;
 404                         resets = <&ccu RST_BUS_SPI1>;
 405                         status = "disabled";
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                 };
 409
 410                 wdt0: watchdog@01c20ca0 {
 411                         compatible = "allwinner,sun6i-a31-wdt";
 412                         reg = <0x01c20ca0 0x20>;
 413                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 414                 };
 415
 416                 spdif: spdif@01c21000 {
 417                         #sound-dai-cells = <0>;
 418                         compatible = "allwinner,sun8i-h3-spdif";
 419                         reg = <0x01c21000 0x400>;
 420                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 422                         resets = <&ccu RST_BUS_SPDIF>;
 423                         clock-names = "apb", "spdif";
 424                         dmas = <&dma 2>;
 425                         dma-names = "tx";
 426                         status = "disabled";
 427                 };
 428
 429                 pwm: pwm@01c21400 {
 430                         compatible = "allwinner,sun8i-h3-pwm";
 431                         reg = <0x01c21400 0x8>;
 432                         clocks = <&osc24M>;
 433                         #pwm-cells = <3>;
 434                         status = "disabled";
 435                 };
 436
 437                 codec: codec@01c22c00 {
 438                         #sound-dai-cells = <0>;
 439                         compatible = "allwinner,sun8i-h3-codec";
 440                         reg = <0x01c22c00 0x400>;
 441                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 443                         clock-names = "apb", "codec";
 444                         resets = <&ccu RST_BUS_CODEC>;
 445                         dmas = <&dma 15>, <&dma 15>;
 446                         dma-names = "rx", "tx";
 447                         allwinner,codec-analog-controls = <&codec_analog>;
 448                         status = "disabled";
 449                 };
 450
 451                 uart0: serial@01c28000 {
 452                         compatible = "snps,dw-apb-uart";
 453                         reg = <0x01c28000 0x400>;
 454                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 455                         reg-shift = <2>;
 456                         reg-io-width = <4>;
 457                         clocks = <&ccu CLK_BUS_UART0>;
 458                         resets = <&ccu RST_BUS_UART0>;
 459                         dmas = <&dma 6>, <&dma 6>;
 460                         dma-names = "rx", "tx";
 461                         status = "disabled";
 462                 };
 463
 464                 uart1: serial@01c28400 {
 465                         compatible = "snps,dw-apb-uart";
 466                         reg = <0x01c28400 0x400>;
 467                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 468                         reg-shift = <2>;
 469                         reg-io-width = <4>;
 470                         clocks = <&ccu CLK_BUS_UART1>;
 471                         resets = <&ccu RST_BUS_UART1>;
 472                         dmas = <&dma 7>, <&dma 7>;
 473                         dma-names = "rx", "tx";
 474                         status = "disabled";
 475                 };
 476
 477                 uart2: serial@01c28800 {
 478                         compatible = "snps,dw-apb-uart";
 479                         reg = <0x01c28800 0x400>;
 480                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 481                         reg-shift = <2>;
 482                         reg-io-width = <4>;
 483                         clocks = <&ccu CLK_BUS_UART2>;
 484                         resets = <&ccu RST_BUS_UART2>;
 485                         dmas = <&dma 8>, <&dma 8>;
 486                         dma-names = "rx", "tx";
 487                         status = "disabled";
 488                 };
 489
 490                 uart3: serial@01c28c00 {
 491                         compatible = "snps,dw-apb-uart";
 492                         reg = <0x01c28c00 0x400>;
 493                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 494                         reg-shift = <2>;
 495                         reg-io-width = <4>;
 496                         clocks = <&ccu CLK_BUS_UART3>;
 497                         resets = <&ccu RST_BUS_UART3>;
 498                         dmas = <&dma 9>, <&dma 9>;
 499                         dma-names = "rx", "tx";
 500                         status = "disabled";
 501                 };
 502
 503                 i2c0: i2c@01c2ac00 {
 504                         compatible = "allwinner,sun6i-a31-i2c";
 505                         reg = <0x01c2ac00 0x400>;
 506                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&ccu CLK_BUS_I2C0>;
 508                         resets = <&ccu RST_BUS_I2C0>;
 509                         pinctrl-names = "default";
 510                         pinctrl-0 = <&i2c0_pins>;
 511                         status = "disabled";
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                 };
 515
 516                 i2c1: i2c@01c2b000 {
 517                         compatible = "allwinner,sun6i-a31-i2c";
 518                         reg = <0x01c2b000 0x400>;
 519                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&ccu CLK_BUS_I2C1>;
 521                         resets = <&ccu RST_BUS_I2C1>;
 522                         pinctrl-names = "default";
 523                         pinctrl-0 = <&i2c1_pins>;
 524                         status = "disabled";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                 };
 528
 529                 i2c2: i2c@01c2b400 {
 530                         compatible = "allwinner,sun6i-a31-i2c";
 531                         reg = <0x01c2b000 0x400>;
 532                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&ccu CLK_BUS_I2C2>;
 534                         resets = <&ccu RST_BUS_I2C2>;
 535                         pinctrl-names = "default";
 536                         pinctrl-0 = <&i2c2_pins>;
 537                         status = "disabled";
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                 };
 541
 542                 gic: interrupt-controller@01c81000 {
 543                         compatible = "arm,gic-400";
 544                         reg = <0x01c81000 0x1000>,
 545                               <0x01c82000 0x2000>,
 546                               <0x01c84000 0x2000>,
 547                               <0x01c86000 0x2000>;
 548                         interrupt-controller;
 549                         #interrupt-cells = <3>;
 550                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 551                 };
 552
 553                 rtc: rtc@01f00000 {
 554                         compatible = "allwinner,sun6i-a31-rtc";
 555                         reg = <0x01f00000 0x54>;
 556                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 558                 };
 559
 560                 r_ccu: clock@1f01400 {
 561                         compatible = "allwinner,sun50i-a64-r-ccu";
 562                         reg = <0x01f01400 0x100>;
 563                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
 564                         clock-names = "hosc", "losc", "iosc";
 565                         #clock-cells = <1>;
 566                         #reset-cells = <1>;
 567                 };
 568
 569                 codec_analog: codec-analog@01f015c0 {
 570                         compatible = "allwinner,sun8i-h3-codec-analog";
 571                         reg = <0x01f015c0 0x4>;
 572                 };
 573
 574                 ir: ir@01f02000 {
 575                         compatible = "allwinner,sun5i-a13-ir";
 576                         clocks = <&r_ccu 4>, <&r_ccu 11>;
 577                         clock-names = "apb", "ir";
 578                         resets = <&r_ccu 0>;
 579                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 580                         reg = <0x01f02000 0x40>;
 581                         status = "disabled";
 582                 };
 583
 584                 r_pio: pinctrl@01f02c00 {
 585                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 586                         reg = <0x01f02c00 0x400>;
 587                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
 589                         clock-names = "apb", "hosc", "losc";
 590                         gpio-controller;
 591                         #gpio-cells = <3>;
 592                         interrupt-controller;
 593                         #interrupt-cells = <3>;
 594
 595                         ir_pins_a: ir@0 {
 596                                 pins = "PL11";
 597                                 function = "s_cir_rx";
 598                         };
 599                 };
 600         };
 601 };