2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
57 interrupt-parent = <&gic>;
68 compatible = "arm,cortex-a7";
70 cci-control-port = <&cci_control0>;
71 clock-frequency = <12000000>;
72 enable-method = "allwinner,sun9i-a80-smp";
77 compatible = "arm,cortex-a7";
79 cci-control-port = <&cci_control0>;
80 clock-frequency = <12000000>;
81 enable-method = "allwinner,sun9i-a80-smp";
86 compatible = "arm,cortex-a7";
88 cci-control-port = <&cci_control0>;
89 clock-frequency = <12000000>;
90 enable-method = "allwinner,sun9i-a80-smp";
95 compatible = "arm,cortex-a7";
97 cci-control-port = <&cci_control0>;
98 clock-frequency = <12000000>;
99 enable-method = "allwinner,sun9i-a80-smp";
104 compatible = "arm,cortex-a15";
106 cci-control-port = <&cci_control1>;
107 clock-frequency = <18000000>;
108 enable-method = "allwinner,sun9i-a80-smp";
113 compatible = "arm,cortex-a15";
115 cci-control-port = <&cci_control1>;
116 clock-frequency = <18000000>;
117 enable-method = "allwinner,sun9i-a80-smp";
122 compatible = "arm,cortex-a15";
124 cci-control-port = <&cci_control1>;
125 clock-frequency = <18000000>;
126 enable-method = "allwinner,sun9i-a80-smp";
131 compatible = "arm,cortex-a15";
133 cci-control-port = <&cci_control1>;
134 clock-frequency = <18000000>;
135 enable-method = "allwinner,sun9i-a80-smp";
141 compatible = "arm,armv7-timer";
142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
146 clock-frequency = <24000000>;
147 arm,cpu-registers-not-fw-configured;
151 #address-cells = <1>;
154 * map 64 bit address range down to 32 bits,
155 * as the peripherals are all under 512MB.
157 ranges = <0 0 0 0x20000000>;
160 * This clock is actually configurable from the PRCM address
161 * space. The external 24M oscillator can be turned off, and
162 * the clock switched to an internal 16M RC oscillator. Under
163 * normal operation there's no reason to do this, and the
164 * default is to use the external good one, so just model this
165 * as a fixed clock. Also it is not entirely clear if the
166 * osc24M mux in the PRCM affects the entire clock tree, which
167 * would also throw all the PLL clock rates off, or just the
168 * downstream clocks in the PRCM.
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "osc24M";
178 * The 32k clock is from an external source, normally the
179 * AC100 codec/RTC chip. This serves as a placeholder for
180 * board dts files to specify the source.
184 compatible = "fixed-factor-clock";
187 clock-output-names = "osc32k";
191 * The following two are dummy clocks, placeholders
192 * used in the gmac_tx clock. The gmac driver will
193 * choose one parent depending on the PHY interface
194 * mode, using clk_set_rate auto-reparenting.
196 * The actual TX clock rate is not controlled by the
199 mii_phy_tx_clk: mii_phy_tx_clk {
201 compatible = "fixed-clock";
202 clock-frequency = <25000000>;
203 clock-output-names = "mii_phy_tx";
206 gmac_int_tx_clk: gmac_int_tx_clk {
208 compatible = "fixed-clock";
209 clock-frequency = <125000000>;
210 clock-output-names = "gmac_int_tx";
213 gmac_tx_clk: clk@800030 {
215 compatible = "allwinner,sun7i-a20-gmac-clk";
216 reg = <0x00800030 0x4>;
217 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
218 clock-output-names = "gmac_tx";
221 cpus_clk: clk@8001410 {
222 compatible = "allwinner,sun9i-a80-cpus-clk";
223 reg = <0x08001410 0x4>;
225 clocks = <&osc32k>, <&osc24M>,
226 <&ccu CLK_PLL_PERIPH0>,
227 <&ccu CLK_PLL_AUDIO>;
228 clock-output-names = "cpus";
232 compatible = "fixed-factor-clock";
236 clocks = <&cpus_clk>;
237 clock-output-names = "ahbs";
241 compatible = "allwinner,sun8i-a23-apb0-clk";
242 reg = <0x0800141c 0x4>;
245 clock-output-names = "apbs";
248 apbs_gates: clk@8001428 {
249 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
250 reg = <0x08001428 0x4>;
253 clock-indices = <0>, <1>,
260 clock-output-names = "apbs_pio", "apbs_ir",
261 "apbs_timer", "apbs_rsb",
262 "apbs_uart", "apbs_1wire",
263 "apbs_i2c0", "apbs_i2c1",
264 "apbs_ps2_0", "apbs_ps2_1",
265 "apbs_dma", "apbs_i2s0",
266 "apbs_i2s1", "apbs_twd";
269 r_1wire_clk: clk@8001450 {
270 reg = <0x08001450 0x4>;
272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 clocks = <&osc32k>, <&osc24M>;
274 clock-output-names = "r_1wire";
277 r_ir_clk: clk@8001454 {
278 reg = <0x08001454 0x4>;
280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 clocks = <&osc32k>, <&osc24M>;
282 clock-output-names = "r_ir";
287 compatible = "allwinner,sun9i-a80-display-engine";
288 allwinner,pipelines = <&fe0>, <&fe1>;
293 compatible = "simple-bus";
294 #address-cells = <1>;
297 * map 64 bit address range down to 32 bits,
298 * as the peripherals are all under 512MB.
300 ranges = <0 0 0 0x20000000>;
303 /* 256 KiB secure SRAM at 0x20000 */
304 compatible = "mmio-sram";
305 reg = <0x00020000 0x40000>;
307 #address-cells = <1>;
309 ranges = <0 0x00020000 0x40000>;
313 * This is checked by BROM to determine if
314 * cpu0 should jump to SMP entry vector
316 compatible = "allwinner,sun9i-a80-smp-sram";
321 gmac: ethernet@830000 {
322 compatible = "allwinner,sun7i-a20-gmac";
323 reg = <0x00830000 0x1054>;
324 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "macirq";
326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
327 clock-names = "stmmaceth", "allwinner_gmac_tx";
328 resets = <&ccu RST_BUS_GMAC>;
329 reset-names = "stmmaceth";
332 snps,force_sf_dma_mode;
336 compatible = "snps,dwmac-mdio";
337 #address-cells = <1>;
343 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
344 reg = <0x00a00000 0x100>;
345 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&usb_clocks CLK_BUS_HCI0>;
347 resets = <&usb_clocks RST_USB0_HCI>;
353 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
354 reg = <0x00a00400 0x100>;
355 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&usb_clocks CLK_BUS_HCI0>,
357 <&usb_clocks CLK_USB_OHCI0>;
358 resets = <&usb_clocks RST_USB0_HCI>;
363 usbphy1: phy@a00800 {
364 compatible = "allwinner,sun9i-a80-usb-phy";
365 reg = <0x00a00800 0x4>;
366 clocks = <&usb_clocks CLK_USB0_PHY>;
368 resets = <&usb_clocks RST_USB0_PHY>;
375 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
376 reg = <0x00a01000 0x100>;
377 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&usb_clocks CLK_BUS_HCI1>;
379 resets = <&usb_clocks RST_USB1_HCI>;
384 usbphy2: phy@a01800 {
385 compatible = "allwinner,sun9i-a80-usb-phy";
386 reg = <0x00a01800 0x4>;
387 clocks = <&usb_clocks CLK_USB1_HSIC>,
388 <&usb_clocks CLK_USB_HSIC>,
389 <&usb_clocks CLK_USB1_PHY>;
390 clock-names = "hsic_480M",
393 resets = <&usb_clocks RST_USB1_HSIC>,
394 <&usb_clocks RST_USB1_PHY>;
395 reset-names = "hsic",
399 /* usb1 is always used with HSIC */
404 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
405 reg = <0x00a02000 0x100>;
406 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&usb_clocks CLK_BUS_HCI2>;
408 resets = <&usb_clocks RST_USB2_HCI>;
414 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
415 reg = <0x00a02400 0x100>;
416 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&usb_clocks CLK_BUS_HCI2>,
418 <&usb_clocks CLK_USB_OHCI2>;
419 resets = <&usb_clocks RST_USB2_HCI>;
424 usbphy3: phy@a02800 {
425 compatible = "allwinner,sun9i-a80-usb-phy";
426 reg = <0x00a02800 0x4>;
427 clocks = <&usb_clocks CLK_USB2_HSIC>,
428 <&usb_clocks CLK_USB_HSIC>,
429 <&usb_clocks CLK_USB2_PHY>;
430 clock-names = "hsic_480M",
433 resets = <&usb_clocks RST_USB2_HSIC>,
434 <&usb_clocks RST_USB2_PHY>;
435 reset-names = "hsic",
441 usb_clocks: clock@a08000 {
442 compatible = "allwinner,sun9i-a80-usb-clks";
443 reg = <0x00a08000 0x8>;
444 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
445 clock-names = "bus", "hosc";
451 compatible = "allwinner,sun9i-a80-cpucfg";
452 reg = <0x01700000 0x100>;
456 compatible = "allwinner,sun9i-a80-mmc";
457 reg = <0x01c0f000 0x1000>;
458 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
459 <&ccu CLK_MMC0_OUTPUT>,
460 <&ccu CLK_MMC0_SAMPLE>;
461 clock-names = "ahb", "mmc", "output", "sample";
462 resets = <&mmc_config_clk 0>;
464 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
471 compatible = "allwinner,sun9i-a80-mmc";
472 reg = <0x01c10000 0x1000>;
473 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
474 <&ccu CLK_MMC1_OUTPUT>,
475 <&ccu CLK_MMC1_SAMPLE>;
476 clock-names = "ahb", "mmc", "output", "sample";
477 resets = <&mmc_config_clk 1>;
479 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
481 #address-cells = <1>;
486 compatible = "allwinner,sun9i-a80-mmc";
487 reg = <0x01c11000 0x1000>;
488 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
489 <&ccu CLK_MMC2_OUTPUT>,
490 <&ccu CLK_MMC2_SAMPLE>;
491 clock-names = "ahb", "mmc", "output", "sample";
492 resets = <&mmc_config_clk 2>;
494 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
496 #address-cells = <1>;
501 compatible = "allwinner,sun9i-a80-mmc";
502 reg = <0x01c12000 0x1000>;
503 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
504 <&ccu CLK_MMC3_OUTPUT>,
505 <&ccu CLK_MMC3_SAMPLE>;
506 clock-names = "ahb", "mmc", "output", "sample";
507 resets = <&mmc_config_clk 3>;
509 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
511 #address-cells = <1>;
515 mmc_config_clk: clk@1c13000 {
516 compatible = "allwinner,sun9i-a80-mmc-config-clk";
517 reg = <0x01c13000 0x10>;
518 clocks = <&ccu CLK_BUS_MMC>;
520 resets = <&ccu RST_BUS_MMC>;
524 clock-output-names = "mmc0_config", "mmc1_config",
525 "mmc2_config", "mmc3_config";
528 gic: interrupt-controller@1c41000 {
529 compatible = "arm,gic-400";
530 reg = <0x01c41000 0x1000>,
534 interrupt-controller;
535 #interrupt-cells = <3>;
536 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
540 compatible = "arm,cci-400";
541 #address-cells = <1>;
543 reg = <0x01c90000 0x1000>;
544 ranges = <0x0 0x01c90000 0x10000>;
546 cci_control0: slave-if@4000 {
547 compatible = "arm,cci-400-ctrl-if";
548 interface-type = "ace";
549 reg = <0x4000 0x1000>;
552 cci_control1: slave-if@5000 {
553 compatible = "arm,cci-400-ctrl-if";
554 interface-type = "ace";
555 reg = <0x5000 0x1000>;
559 compatible = "arm,cci-400-pmu,r1";
560 reg = <0x9000 0x5000>;
561 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
569 de_clocks: clock@3000000 {
570 compatible = "allwinner,sun9i-a80-de-clks";
571 reg = <0x03000000 0x30>;
572 clocks = <&ccu CLK_DE>,
578 resets = <&ccu RST_BUS_DE>;
583 fe0: display-frontend@3100000 {
584 compatible = "allwinner,sun9i-a80-display-frontend";
585 reg = <0x03100000 0x40000>;
586 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
588 <&de_clocks CLK_DRAM_FE0>;
589 clock-names = "ahb", "mod",
591 resets = <&de_clocks RST_FE0>;
594 #address-cells = <1>;
600 fe0_out_deu0: endpoint {
601 remote-endpoint = <&deu0_in_fe0>;
607 fe1: display-frontend@3140000 {
608 compatible = "allwinner,sun9i-a80-display-frontend";
609 reg = <0x03140000 0x40000>;
610 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
612 <&de_clocks CLK_DRAM_FE1>;
613 clock-names = "ahb", "mod",
615 resets = <&de_clocks RST_FE0>;
618 #address-cells = <1>;
624 fe1_out_deu1: endpoint {
625 remote-endpoint = <&deu1_in_fe1>;
631 be0: display-backend@3200000 {
632 compatible = "allwinner,sun9i-a80-display-backend";
633 reg = <0x03200000 0x40000>;
634 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
636 <&de_clocks CLK_DRAM_BE0>;
637 clock-names = "ahb", "mod",
639 resets = <&de_clocks RST_BE0>;
642 #address-cells = <1>;
646 #address-cells = <1>;
650 be0_in_deu0: endpoint@0 {
652 remote-endpoint = <&deu0_out_be0>;
655 be0_in_deu1: endpoint@1 {
657 remote-endpoint = <&deu1_out_be0>;
664 be0_out_drc0: endpoint {
665 remote-endpoint = <&drc0_in_be0>;
671 be1: display-backend@3240000 {
672 compatible = "allwinner,sun9i-a80-display-backend";
673 reg = <0x03240000 0x40000>;
674 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
676 <&de_clocks CLK_DRAM_BE1>;
677 clock-names = "ahb", "mod",
679 resets = <&de_clocks RST_BE1>;
682 #address-cells = <1>;
686 #address-cells = <1>;
690 be1_in_deu0: endpoint@0 {
692 remote-endpoint = <&deu0_out_be1>;
695 be1_in_deu1: endpoint@1 {
697 remote-endpoint = <&deu1_out_be1>;
704 be1_out_drc1: endpoint {
705 remote-endpoint = <&drc1_in_be1>;
712 compatible = "allwinner,sun9i-a80-deu";
713 reg = <0x03300000 0x40000>;
714 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&de_clocks CLK_BUS_DEU0>,
716 <&de_clocks CLK_IEP_DEU0>,
717 <&de_clocks CLK_DRAM_DEU0>;
721 resets = <&de_clocks RST_DEU0>;
724 #address-cells = <1>;
730 deu0_in_fe0: endpoint {
731 remote-endpoint = <&fe0_out_deu0>;
736 #address-cells = <1>;
740 deu0_out_be0: endpoint@0 {
742 remote-endpoint = <&be0_in_deu0>;
745 deu0_out_be1: endpoint@1 {
747 remote-endpoint = <&be1_in_deu0>;
754 compatible = "allwinner,sun9i-a80-deu";
755 reg = <0x03340000 0x40000>;
756 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&de_clocks CLK_BUS_DEU1>,
758 <&de_clocks CLK_IEP_DEU1>,
759 <&de_clocks CLK_DRAM_DEU1>;
763 resets = <&de_clocks RST_DEU1>;
766 #address-cells = <1>;
772 deu1_in_fe1: endpoint {
773 remote-endpoint = <&fe1_out_deu1>;
778 #address-cells = <1>;
782 deu1_out_be0: endpoint@0 {
784 remote-endpoint = <&be0_in_deu1>;
787 deu1_out_be1: endpoint@1 {
789 remote-endpoint = <&be1_in_deu1>;
796 compatible = "allwinner,sun9i-a80-drc";
797 reg = <0x03400000 0x40000>;
798 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&de_clocks CLK_BUS_DRC0>,
800 <&de_clocks CLK_IEP_DRC0>,
801 <&de_clocks CLK_DRAM_DRC0>;
805 resets = <&de_clocks RST_DRC0>;
808 #address-cells = <1>;
814 drc0_in_be0: endpoint {
815 remote-endpoint = <&be0_out_drc0>;
822 drc0_out_tcon0: endpoint {
823 remote-endpoint = <&tcon0_in_drc0>;
830 compatible = "allwinner,sun9i-a80-drc";
831 reg = <0x03440000 0x40000>;
832 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&de_clocks CLK_BUS_DRC1>,
834 <&de_clocks CLK_IEP_DRC1>,
835 <&de_clocks CLK_DRAM_DRC1>;
839 resets = <&de_clocks RST_DRC1>;
842 #address-cells = <1>;
848 drc1_in_be1: endpoint {
849 remote-endpoint = <&be1_out_drc1>;
856 drc1_out_tcon1: endpoint {
857 remote-endpoint = <&tcon1_in_drc1>;
863 tcon0: lcd-controller@3c00000 {
864 compatible = "allwinner,sun9i-a80-tcon-lcd";
865 reg = <0x03c00000 0x10000>;
866 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
868 clock-names = "ahb", "tcon-ch0";
869 resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
870 reset-names = "lcd", "edp";
871 clock-output-names = "tcon0-pixel-clock";
875 #address-cells = <1>;
881 tcon0_in_drc0: endpoint {
882 remote-endpoint = <&drc0_out_tcon0>;
892 tcon1: lcd-controller@3c10000 {
893 compatible = "allwinner,sun9i-a80-tcon-tv";
894 reg = <0x03c10000 0x10000>;
895 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
897 clock-names = "ahb", "tcon-ch1";
898 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
899 reset-names = "lcd", "edp";
902 #address-cells = <1>;
908 tcon1_in_drc1: endpoint {
909 remote-endpoint = <&drc1_out_tcon1>;
920 compatible = "allwinner,sun9i-a80-ccu";
921 reg = <0x06000000 0x800>;
922 clocks = <&osc24M>, <&osc32k>;
923 clock-names = "hosc", "losc";
929 compatible = "allwinner,sun4i-a10-timer";
930 reg = <0x06000c00 0xa0>;
931 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
941 wdt: watchdog@6000ca0 {
942 compatible = "allwinner,sun6i-a31-wdt";
943 reg = <0x06000ca0 0x20>;
944 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
947 pio: pinctrl@6000800 {
948 compatible = "allwinner,sun9i-a80-pinctrl";
949 reg = <0x06000800 0x400>;
950 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
956 clock-names = "apb", "hosc", "losc";
958 interrupt-controller;
959 #interrupt-cells = <3>;
962 gmac_rgmii_pins: gmac-rgmii-pins {
963 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
964 "PA7", "PA8", "PA9", "PA10", "PA12",
965 "PA13", "PA15", "PA16", "PA17";
968 * data lines in RGMII mode use DDR mode
969 * and need a higher signal drive strength
971 drive-strength = <40>;
974 i2c3_pins: i2c3-pins {
975 pins = "PG10", "PG11";
979 lcd0_rgb888_pins: lcd0-rgb888-pins {
980 pins = "PD0", "PD1", "PD2", "PD3",
981 "PD4", "PD5", "PD6", "PD7",
982 "PD8", "PD9", "PD10", "PD11",
983 "PD12", "PD13", "PD14", "PD15",
984 "PD16", "PD17", "PD18", "PD19",
985 "PD20", "PD21", "PD22", "PD23",
986 "PD24", "PD25", "PD26", "PD27";
990 mmc0_pins: mmc0-pins {
991 pins = "PF0", "PF1" ,"PF2", "PF3",
994 drive-strength = <30>;
998 mmc1_pins: mmc1-pins {
999 pins = "PG0", "PG1" ,"PG2", "PG3",
1002 drive-strength = <30>;
1006 mmc2_8bit_pins: mmc2-8bit-pins {
1007 pins = "PC6", "PC7", "PC8", "PC9",
1008 "PC10", "PC11", "PC12",
1009 "PC13", "PC14", "PC15",
1012 drive-strength = <30>;
1016 uart0_ph_pins: uart0-ph-pins {
1017 pins = "PH12", "PH13";
1021 uart4_pins: uart4-pins {
1022 pins = "PG12", "PG13", "PG14", "PG15";
1027 uart0: serial@7000000 {
1028 compatible = "snps,dw-apb-uart";
1029 reg = <0x07000000 0x400>;
1030 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&ccu CLK_BUS_UART0>;
1034 resets = <&ccu RST_BUS_UART0>;
1035 status = "disabled";
1038 uart1: serial@7000400 {
1039 compatible = "snps,dw-apb-uart";
1040 reg = <0x07000400 0x400>;
1041 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&ccu CLK_BUS_UART1>;
1045 resets = <&ccu RST_BUS_UART1>;
1046 status = "disabled";
1049 uart2: serial@7000800 {
1050 compatible = "snps,dw-apb-uart";
1051 reg = <0x07000800 0x400>;
1052 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&ccu CLK_BUS_UART2>;
1056 resets = <&ccu RST_BUS_UART2>;
1057 status = "disabled";
1060 uart3: serial@7000c00 {
1061 compatible = "snps,dw-apb-uart";
1062 reg = <0x07000c00 0x400>;
1063 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&ccu CLK_BUS_UART3>;
1067 resets = <&ccu RST_BUS_UART3>;
1068 status = "disabled";
1071 uart4: serial@7001000 {
1072 compatible = "snps,dw-apb-uart";
1073 reg = <0x07001000 0x400>;
1074 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&ccu CLK_BUS_UART4>;
1078 resets = <&ccu RST_BUS_UART4>;
1079 status = "disabled";
1082 uart5: serial@7001400 {
1083 compatible = "snps,dw-apb-uart";
1084 reg = <0x07001400 0x400>;
1085 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&ccu CLK_BUS_UART5>;
1089 resets = <&ccu RST_BUS_UART5>;
1090 status = "disabled";
1094 compatible = "allwinner,sun6i-a31-i2c";
1095 reg = <0x07002800 0x400>;
1096 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&ccu CLK_BUS_I2C0>;
1098 resets = <&ccu RST_BUS_I2C0>;
1099 status = "disabled";
1100 #address-cells = <1>;
1105 compatible = "allwinner,sun6i-a31-i2c";
1106 reg = <0x07002c00 0x400>;
1107 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BUS_I2C1>;
1109 resets = <&ccu RST_BUS_I2C1>;
1110 status = "disabled";
1111 #address-cells = <1>;
1116 compatible = "allwinner,sun6i-a31-i2c";
1117 reg = <0x07003000 0x400>;
1118 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&ccu CLK_BUS_I2C2>;
1120 resets = <&ccu RST_BUS_I2C2>;
1121 status = "disabled";
1122 #address-cells = <1>;
1127 compatible = "allwinner,sun6i-a31-i2c";
1128 reg = <0x07003400 0x400>;
1129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&ccu CLK_BUS_I2C3>;
1131 resets = <&ccu RST_BUS_I2C3>;
1132 status = "disabled";
1133 #address-cells = <1>;
1138 compatible = "allwinner,sun6i-a31-i2c";
1139 reg = <0x07003800 0x400>;
1140 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&ccu CLK_BUS_I2C4>;
1142 resets = <&ccu RST_BUS_I2C4>;
1143 status = "disabled";
1144 #address-cells = <1>;
1148 r_wdt: watchdog@8001000 {
1149 compatible = "allwinner,sun6i-a31-wdt";
1150 reg = <0x08001000 0x20>;
1151 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1155 compatible = "allwinner,sun9i-a80-prcm";
1156 reg = <0x08001400 0x200>;
1159 apbs_rst: reset@80014b0 {
1160 reg = <0x080014b0 0x4>;
1161 compatible = "allwinner,sun6i-a31-clock-reset";
1165 nmi_intc: interrupt-controller@80015a0 {
1166 compatible = "allwinner,sun9i-a80-nmi";
1167 interrupt-controller;
1168 #interrupt-cells = <2>;
1169 reg = <0x080015a0 0xc>;
1170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1174 compatible = "allwinner,sun6i-a31-ir";
1175 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&r_ir_pins>;
1178 clocks = <&apbs_gates 1>, <&r_ir_clk>;
1179 clock-names = "apb", "ir";
1180 resets = <&apbs_rst 1>;
1181 reg = <0x08002000 0x40>;
1182 status = "disabled";
1185 r_uart: serial@8002800 {
1186 compatible = "snps,dw-apb-uart";
1187 reg = <0x08002800 0x400>;
1188 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&apbs_gates 4>;
1192 resets = <&apbs_rst 4>;
1193 status = "disabled";
1196 r_pio: pinctrl@8002c00 {
1197 compatible = "allwinner,sun9i-a80-r-pinctrl";
1198 reg = <0x08002c00 0x400>;
1199 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1202 clock-names = "apb", "hosc", "losc";
1203 resets = <&apbs_rst 0>;
1205 interrupt-controller;
1206 #interrupt-cells = <3>;
1209 r_ir_pins: r-ir-pins {
1211 function = "s_cir_rx";
1214 r_rsb_pins: r-rsb-pins {
1215 pins = "PN0", "PN1";
1217 drive-strength = <20>;
1222 r_rsb: rsb@8003400 {
1223 compatible = "allwinner,sun8i-a23-rsb";
1224 reg = <0x08003400 0x400>;
1225 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&apbs_gates 3>;
1227 clock-frequency = <3000000>;
1228 resets = <&apbs_rst 3>;
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&r_rsb_pins>;
1231 status = "disabled";
1232 #address-cells = <1>;