Merge tag 'drm-fixes-5.5-2019-12-12' of git://people.freedesktop.org/~agd5f/linux...
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun9i-a80.dtsi
1 /*
2  * Copyright 2014 Chen-Yu Tsai
3  *
4  * Chen-Yu Tsai <wens@csie.org>
5  *
6  * This file is dual-licensed: you can use it either under the terms
7  * of the GPL or the X11 license, at your option. Note that this dual
8  * licensing only applies to this file, and not this project as a
9  * whole.
10  *
11  *  a) This file is free software; you can redistribute it and/or
12  *     modify it under the terms of the GNU General Public License as
13  *     published by the Free Software Foundation; either version 2 of the
14  *     License, or (at your option) any later version.
15  *
16  *     This file is distributed in the hope that it will be useful,
17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *     GNU General Public License for more details.
20  *
21  * Or, alternatively,
22  *
23  *  b) Permission is hereby granted, free of charge, to any person
24  *     obtaining a copy of this software and associated documentation
25  *     files (the "Software"), to deal in the Software without
26  *     restriction, including without limitation the rights to use,
27  *     copy, modify, merge, publish, distribute, sublicense, and/or
28  *     sell copies of the Software, and to permit persons to whom the
29  *     Software is furnished to do so, subject to the following
30  *     conditions:
31  *
32  *     The above copyright notice and this permission notice shall be
33  *     included in all copies or substantial portions of the Software.
34  *
35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42  *     OTHER DEALINGS IN THE SOFTWARE.
43  */
44
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
53
54 / {
55         #address-cells = <2>;
56         #size-cells = <2>;
57         interrupt-parent = <&gic>;
58
59         aliases {
60                 ethernet0 = &gmac;
61         };
62
63         cpus {
64                 #address-cells = <1>;
65                 #size-cells = <0>;
66
67                 cpu0: cpu@0 {
68                         compatible = "arm,cortex-a7";
69                         device_type = "cpu";
70                         cci-control-port = <&cci_control0>;
71                         clock-frequency = <12000000>;
72                         enable-method = "allwinner,sun9i-a80-smp";
73                         reg = <0x0>;
74                 };
75
76                 cpu1: cpu@1 {
77                         compatible = "arm,cortex-a7";
78                         device_type = "cpu";
79                         cci-control-port = <&cci_control0>;
80                         clock-frequency = <12000000>;
81                         enable-method = "allwinner,sun9i-a80-smp";
82                         reg = <0x1>;
83                 };
84
85                 cpu2: cpu@2 {
86                         compatible = "arm,cortex-a7";
87                         device_type = "cpu";
88                         cci-control-port = <&cci_control0>;
89                         clock-frequency = <12000000>;
90                         enable-method = "allwinner,sun9i-a80-smp";
91                         reg = <0x2>;
92                 };
93
94                 cpu3: cpu@3 {
95                         compatible = "arm,cortex-a7";
96                         device_type = "cpu";
97                         cci-control-port = <&cci_control0>;
98                         clock-frequency = <12000000>;
99                         enable-method = "allwinner,sun9i-a80-smp";
100                         reg = <0x3>;
101                 };
102
103                 cpu4: cpu@100 {
104                         compatible = "arm,cortex-a15";
105                         device_type = "cpu";
106                         cci-control-port = <&cci_control1>;
107                         clock-frequency = <18000000>;
108                         enable-method = "allwinner,sun9i-a80-smp";
109                         reg = <0x100>;
110                 };
111
112                 cpu5: cpu@101 {
113                         compatible = "arm,cortex-a15";
114                         device_type = "cpu";
115                         cci-control-port = <&cci_control1>;
116                         clock-frequency = <18000000>;
117                         enable-method = "allwinner,sun9i-a80-smp";
118                         reg = <0x101>;
119                 };
120
121                 cpu6: cpu@102 {
122                         compatible = "arm,cortex-a15";
123                         device_type = "cpu";
124                         cci-control-port = <&cci_control1>;
125                         clock-frequency = <18000000>;
126                         enable-method = "allwinner,sun9i-a80-smp";
127                         reg = <0x102>;
128                 };
129
130                 cpu7: cpu@103 {
131                         compatible = "arm,cortex-a15";
132                         device_type = "cpu";
133                         cci-control-port = <&cci_control1>;
134                         clock-frequency = <18000000>;
135                         enable-method = "allwinner,sun9i-a80-smp";
136                         reg = <0x103>;
137                 };
138         };
139
140         timer {
141                 compatible = "arm,armv7-timer";
142                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
146                 clock-frequency = <24000000>;
147                 arm,cpu-registers-not-fw-configured;
148         };
149
150         clocks {
151                 #address-cells = <1>;
152                 #size-cells = <1>;
153                 /*
154                  * map 64 bit address range down to 32 bits,
155                  * as the peripherals are all under 512MB.
156                  */
157                 ranges = <0 0 0 0x20000000>;
158
159                 /*
160                  * This clock is actually configurable from the PRCM address
161                  * space. The external 24M oscillator can be turned off, and
162                  * the clock switched to an internal 16M RC oscillator. Under
163                  * normal operation there's no reason to do this, and the
164                  * default is to use the external good one, so just model this
165                  * as a fixed clock. Also it is not entirely clear if the
166                  * osc24M mux in the PRCM affects the entire clock tree, which
167                  * would also throw all the PLL clock rates off, or just the
168                  * downstream clocks in the PRCM.
169                  */
170                 osc24M: clk-24M {
171                         #clock-cells = <0>;
172                         compatible = "fixed-clock";
173                         clock-frequency = <24000000>;
174                         clock-output-names = "osc24M";
175                 };
176
177                 /*
178                  * The 32k clock is from an external source, normally the
179                  * AC100 codec/RTC chip. This serves as a placeholder for
180                  * board dts files to specify the source.
181                  */
182                 osc32k: clk-32k {
183                         #clock-cells = <0>;
184                         compatible = "fixed-factor-clock";
185                         clock-div = <1>;
186                         clock-mult = <1>;
187                         clock-output-names = "osc32k";
188                 };
189
190                 /*
191                  * The following two are dummy clocks, placeholders
192                  * used in the gmac_tx clock. The gmac driver will
193                  * choose one parent depending on the PHY interface
194                  * mode, using clk_set_rate auto-reparenting.
195                  *
196                  * The actual TX clock rate is not controlled by the
197                  * gmac_tx clock.
198                  */
199                 mii_phy_tx_clk: mii_phy_tx_clk {
200                         #clock-cells = <0>;
201                         compatible = "fixed-clock";
202                         clock-frequency = <25000000>;
203                         clock-output-names = "mii_phy_tx";
204                 };
205
206                 gmac_int_tx_clk: gmac_int_tx_clk {
207                         #clock-cells = <0>;
208                         compatible = "fixed-clock";
209                         clock-frequency = <125000000>;
210                         clock-output-names = "gmac_int_tx";
211                 };
212
213                 gmac_tx_clk: clk@800030 {
214                         #clock-cells = <0>;
215                         compatible = "allwinner,sun7i-a20-gmac-clk";
216                         reg = <0x00800030 0x4>;
217                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
218                         clock-output-names = "gmac_tx";
219                 };
220
221                 cpus_clk: clk@8001410 {
222                         compatible = "allwinner,sun9i-a80-cpus-clk";
223                         reg = <0x08001410 0x4>;
224                         #clock-cells = <0>;
225                         clocks = <&osc32k>, <&osc24M>,
226                                  <&ccu CLK_PLL_PERIPH0>,
227                                  <&ccu CLK_PLL_AUDIO>;
228                         clock-output-names = "cpus";
229                 };
230
231                 ahbs: clk-ahbs {
232                         compatible = "fixed-factor-clock";
233                         #clock-cells = <0>;
234                         clock-div = <1>;
235                         clock-mult = <1>;
236                         clocks = <&cpus_clk>;
237                         clock-output-names = "ahbs";
238                 };
239
240                 apbs: clk@800141c {
241                         compatible = "allwinner,sun8i-a23-apb0-clk";
242                         reg = <0x0800141c 0x4>;
243                         #clock-cells = <0>;
244                         clocks = <&ahbs>;
245                         clock-output-names = "apbs";
246                 };
247
248                 apbs_gates: clk@8001428 {
249                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
250                         reg = <0x08001428 0x4>;
251                         #clock-cells = <1>;
252                         clocks = <&apbs>;
253                         clock-indices = <0>, <1>,
254                                         <2>, <3>,
255                                         <4>, <5>,
256                                         <6>, <7>,
257                                         <12>, <13>,
258                                         <16>, <17>,
259                                         <18>, <20>;
260                         clock-output-names = "apbs_pio", "apbs_ir",
261                                         "apbs_timer", "apbs_rsb",
262                                         "apbs_uart", "apbs_1wire",
263                                         "apbs_i2c0", "apbs_i2c1",
264                                         "apbs_ps2_0", "apbs_ps2_1",
265                                         "apbs_dma", "apbs_i2s0",
266                                         "apbs_i2s1", "apbs_twd";
267                 };
268
269                 r_1wire_clk: clk@8001450 {
270                         reg = <0x08001450 0x4>;
271                         #clock-cells = <0>;
272                         compatible = "allwinner,sun4i-a10-mod0-clk";
273                         clocks = <&osc32k>, <&osc24M>;
274                         clock-output-names = "r_1wire";
275                 };
276
277                 r_ir_clk: clk@8001454 {
278                         reg = <0x08001454 0x4>;
279                         #clock-cells = <0>;
280                         compatible = "allwinner,sun4i-a10-mod0-clk";
281                         clocks = <&osc32k>, <&osc24M>;
282                         clock-output-names = "r_ir";
283                 };
284         };
285
286         de: display-engine {
287                 compatible = "allwinner,sun9i-a80-display-engine";
288                 allwinner,pipelines = <&fe0>, <&fe1>;
289                 status = "disabled";
290         };
291
292         soc@20000 {
293                 compatible = "simple-bus";
294                 #address-cells = <1>;
295                 #size-cells = <1>;
296                 /*
297                  * map 64 bit address range down to 32 bits,
298                  * as the peripherals are all under 512MB.
299                  */
300                 ranges = <0 0 0 0x20000000>;
301
302                 sram_b: sram@20000 {
303                         /* 256 KiB secure SRAM at 0x20000 */
304                         compatible = "mmio-sram";
305                         reg = <0x00020000 0x40000>;
306
307                         #address-cells = <1>;
308                         #size-cells = <1>;
309                         ranges = <0 0x00020000 0x40000>;
310
311                         smp-sram@1000 {
312                                 /*
313                                  * This is checked by BROM to determine if
314                                  * cpu0 should jump to SMP entry vector
315                                  */
316                                 compatible = "allwinner,sun9i-a80-smp-sram";
317                                 reg = <0x1000 0x8>;
318                         };
319                 };
320
321                 gmac: ethernet@830000 {
322                         compatible = "allwinner,sun7i-a20-gmac";
323                         reg = <0x00830000 0x1054>;
324                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
325                         interrupt-names = "macirq";
326                         clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
327                         clock-names = "stmmaceth", "allwinner_gmac_tx";
328                         resets = <&ccu RST_BUS_GMAC>;
329                         reset-names = "stmmaceth";
330                         snps,pbl = <2>;
331                         snps,fixed-burst;
332                         snps,force_sf_dma_mode;
333                         status = "disabled";
334
335                         mdio: mdio {
336                                 compatible = "snps,dwmac-mdio";
337                                 #address-cells = <1>;
338                                 #size-cells = <0>;
339                         };
340                 };
341
342                 ehci0: usb@a00000 {
343                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
344                         reg = <0x00a00000 0x100>;
345                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
346                         clocks = <&usb_clocks CLK_BUS_HCI0>;
347                         resets = <&usb_clocks RST_USB0_HCI>;
348                         phys = <&usbphy1>;
349                         phy-names = "usb";
350                         status = "disabled";
351                 };
352
353                 ohci0: usb@a00400 {
354                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
355                         reg = <0x00a00400 0x100>;
356                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
357                         clocks = <&usb_clocks CLK_BUS_HCI0>,
358                                  <&usb_clocks CLK_USB_OHCI0>;
359                         resets = <&usb_clocks RST_USB0_HCI>;
360                         phys = <&usbphy1>;
361                         phy-names = "usb";
362                         status = "disabled";
363                 };
364
365                 usbphy1: phy@a00800 {
366                         compatible = "allwinner,sun9i-a80-usb-phy";
367                         reg = <0x00a00800 0x4>;
368                         clocks = <&usb_clocks CLK_USB0_PHY>;
369                         clock-names = "phy";
370                         resets = <&usb_clocks RST_USB0_PHY>;
371                         reset-names = "phy";
372                         status = "disabled";
373                         #phy-cells = <0>;
374                 };
375
376                 ehci1: usb@a01000 {
377                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
378                         reg = <0x00a01000 0x100>;
379                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
380                         clocks = <&usb_clocks CLK_BUS_HCI1>;
381                         resets = <&usb_clocks RST_USB1_HCI>;
382                         phys = <&usbphy2>;
383                         phy-names = "usb";
384                         status = "disabled";
385                 };
386
387                 usbphy2: phy@a01800 {
388                         compatible = "allwinner,sun9i-a80-usb-phy";
389                         reg = <0x00a01800 0x4>;
390                         clocks = <&usb_clocks CLK_USB1_HSIC>,
391                                  <&usb_clocks CLK_USB_HSIC>,
392                                  <&usb_clocks CLK_USB1_PHY>;
393                         clock-names = "hsic_480M",
394                                       "hsic_12M",
395                                       "phy";
396                         resets = <&usb_clocks RST_USB1_HSIC>,
397                                  <&usb_clocks RST_USB1_PHY>;
398                         reset-names = "hsic",
399                                       "phy";
400                         status = "disabled";
401                         #phy-cells = <0>;
402                         /* usb1 is always used with HSIC */
403                         phy_type = "hsic";
404                 };
405
406                 ehci2: usb@a02000 {
407                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
408                         reg = <0x00a02000 0x100>;
409                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
410                         clocks = <&usb_clocks CLK_BUS_HCI2>;
411                         resets = <&usb_clocks RST_USB2_HCI>;
412                         phys = <&usbphy3>;
413                         phy-names = "usb";
414                         status = "disabled";
415                 };
416
417                 ohci2: usb@a02400 {
418                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
419                         reg = <0x00a02400 0x100>;
420                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
421                         clocks = <&usb_clocks CLK_BUS_HCI2>,
422                                  <&usb_clocks CLK_USB_OHCI2>;
423                         resets = <&usb_clocks RST_USB2_HCI>;
424                         phys = <&usbphy3>;
425                         phy-names = "usb";
426                         status = "disabled";
427                 };
428
429                 usbphy3: phy@a02800 {
430                         compatible = "allwinner,sun9i-a80-usb-phy";
431                         reg = <0x00a02800 0x4>;
432                         clocks = <&usb_clocks CLK_USB2_HSIC>,
433                                  <&usb_clocks CLK_USB_HSIC>,
434                                  <&usb_clocks CLK_USB2_PHY>;
435                         clock-names = "hsic_480M",
436                                       "hsic_12M",
437                                       "phy";
438                         resets = <&usb_clocks RST_USB2_HSIC>,
439                                  <&usb_clocks RST_USB2_PHY>;
440                         reset-names = "hsic",
441                                       "phy";
442                         status = "disabled";
443                         #phy-cells = <0>;
444                 };
445
446                 usb_clocks: clock@a08000 {
447                         compatible = "allwinner,sun9i-a80-usb-clks";
448                         reg = <0x00a08000 0x8>;
449                         clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
450                         clock-names = "bus", "hosc";
451                         #clock-cells = <1>;
452                         #reset-cells = <1>;
453                 };
454
455                 cpucfg@1700000 {
456                         compatible = "allwinner,sun9i-a80-cpucfg";
457                         reg = <0x01700000 0x100>;
458                 };
459
460                 crypto: crypto@1c02000 {
461                         compatible = "allwinner,sun9i-a80-crypto";
462                         reg = <0x01c02000 0x1000>;
463                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
464                         resets = <&ccu RST_BUS_SS>;
465                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
466                         clock-names = "bus", "mod";
467                 };
468
469                 mmc0: mmc@1c0f000 {
470                         compatible = "allwinner,sun9i-a80-mmc";
471                         reg = <0x01c0f000 0x1000>;
472                         clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
473                                  <&ccu CLK_MMC0_OUTPUT>,
474                                  <&ccu CLK_MMC0_SAMPLE>;
475                         clock-names = "ahb", "mmc", "output", "sample";
476                         resets = <&mmc_config_clk 0>;
477                         reset-names = "ahb";
478                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
479                         status = "disabled";
480                         #address-cells = <1>;
481                         #size-cells = <0>;
482                 };
483
484                 mmc1: mmc@1c10000 {
485                         compatible = "allwinner,sun9i-a80-mmc";
486                         reg = <0x01c10000 0x1000>;
487                         clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
488                                  <&ccu CLK_MMC1_OUTPUT>,
489                                  <&ccu CLK_MMC1_SAMPLE>;
490                         clock-names = "ahb", "mmc", "output", "sample";
491                         resets = <&mmc_config_clk 1>;
492                         reset-names = "ahb";
493                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
494                         status = "disabled";
495                         #address-cells = <1>;
496                         #size-cells = <0>;
497                 };
498
499                 mmc2: mmc@1c11000 {
500                         compatible = "allwinner,sun9i-a80-mmc";
501                         reg = <0x01c11000 0x1000>;
502                         clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
503                                  <&ccu CLK_MMC2_OUTPUT>,
504                                  <&ccu CLK_MMC2_SAMPLE>;
505                         clock-names = "ahb", "mmc", "output", "sample";
506                         resets = <&mmc_config_clk 2>;
507                         reset-names = "ahb";
508                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
509                         status = "disabled";
510                         #address-cells = <1>;
511                         #size-cells = <0>;
512                 };
513
514                 mmc3: mmc@1c12000 {
515                         compatible = "allwinner,sun9i-a80-mmc";
516                         reg = <0x01c12000 0x1000>;
517                         clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
518                                  <&ccu CLK_MMC3_OUTPUT>,
519                                  <&ccu CLK_MMC3_SAMPLE>;
520                         clock-names = "ahb", "mmc", "output", "sample";
521                         resets = <&mmc_config_clk 3>;
522                         reset-names = "ahb";
523                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
524                         status = "disabled";
525                         #address-cells = <1>;
526                         #size-cells = <0>;
527                 };
528
529                 mmc_config_clk: clk@1c13000 {
530                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
531                         reg = <0x01c13000 0x10>;
532                         clocks = <&ccu CLK_BUS_MMC>;
533                         clock-names = "ahb";
534                         resets = <&ccu RST_BUS_MMC>;
535                         reset-names = "ahb";
536                         #clock-cells = <1>;
537                         #reset-cells = <1>;
538                         clock-output-names = "mmc0_config", "mmc1_config",
539                                              "mmc2_config", "mmc3_config";
540                 };
541
542                 gic: interrupt-controller@1c41000 {
543                         compatible = "arm,gic-400";
544                         reg = <0x01c41000 0x1000>,
545                               <0x01c42000 0x2000>,
546                               <0x01c44000 0x2000>,
547                               <0x01c46000 0x2000>;
548                         interrupt-controller;
549                         #interrupt-cells = <3>;
550                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
551                 };
552
553                 cci: cci@1c90000 {
554                         compatible = "arm,cci-400";
555                         #address-cells = <1>;
556                         #size-cells = <1>;
557                         reg = <0x01c90000 0x1000>;
558                         ranges = <0x0 0x01c90000 0x10000>;
559
560                         cci_control0: slave-if@4000 {
561                                 compatible = "arm,cci-400-ctrl-if";
562                                 interface-type = "ace";
563                                 reg = <0x4000 0x1000>;
564                         };
565
566                         cci_control1: slave-if@5000 {
567                                 compatible = "arm,cci-400-ctrl-if";
568                                 interface-type = "ace";
569                                 reg = <0x5000 0x1000>;
570                         };
571
572                         pmu@9000 {
573                                  compatible = "arm,cci-400-pmu,r1";
574                                  reg = <0x9000 0x5000>;
575                                  interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
576                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
577                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
578                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
579                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
580                         };
581                 };
582
583                 de_clocks: clock@3000000 {
584                         compatible = "allwinner,sun9i-a80-de-clks";
585                         reg = <0x03000000 0x30>;
586                         clocks = <&ccu CLK_DE>,
587                                  <&ccu CLK_SDRAM>,
588                                  <&ccu CLK_BUS_DE>;
589                         clock-names = "mod",
590                                       "dram",
591                                       "bus";
592                         resets = <&ccu RST_BUS_DE>;
593                         #clock-cells = <1>;
594                         #reset-cells = <1>;
595                 };
596
597                 fe0: display-frontend@3100000 {
598                         compatible = "allwinner,sun9i-a80-display-frontend";
599                         reg = <0x03100000 0x40000>;
600                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
601                         clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
602                                  <&de_clocks CLK_DRAM_FE0>;
603                         clock-names = "ahb", "mod",
604                                       "ram";
605                         resets = <&de_clocks RST_FE0>;
606
607                         ports {
608                                 #address-cells = <1>;
609                                 #size-cells = <0>;
610
611                                 fe0_out: port@1 {
612                                         reg = <1>;
613
614                                         fe0_out_deu0: endpoint {
615                                                 remote-endpoint = <&deu0_in_fe0>;
616                                         };
617                                 };
618                         };
619                 };
620
621                 fe1: display-frontend@3140000 {
622                         compatible = "allwinner,sun9i-a80-display-frontend";
623                         reg = <0x03140000 0x40000>;
624                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
625                         clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
626                                  <&de_clocks CLK_DRAM_FE1>;
627                         clock-names = "ahb", "mod",
628                                       "ram";
629                         resets = <&de_clocks RST_FE0>;
630
631                         ports {
632                                 #address-cells = <1>;
633                                 #size-cells = <0>;
634
635                                 fe1_out: port@1 {
636                                         reg = <1>;
637
638                                         fe1_out_deu1: endpoint {
639                                                 remote-endpoint = <&deu1_in_fe1>;
640                                         };
641                                 };
642                         };
643                 };
644
645                 be0: display-backend@3200000 {
646                         compatible = "allwinner,sun9i-a80-display-backend";
647                         reg = <0x03200000 0x40000>;
648                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
649                         clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
650                                  <&de_clocks CLK_DRAM_BE0>;
651                         clock-names = "ahb", "mod",
652                                       "ram";
653                         resets = <&de_clocks RST_BE0>;
654
655                         ports {
656                                 #address-cells = <1>;
657                                 #size-cells = <0>;
658
659                                 be0_in: port@0 {
660                                         #address-cells = <1>;
661                                         #size-cells = <0>;
662                                         reg = <0>;
663
664                                         be0_in_deu0: endpoint@0 {
665                                                 reg = <0>;
666                                                 remote-endpoint = <&deu0_out_be0>;
667                                         };
668
669                                         be0_in_deu1: endpoint@1 {
670                                                 reg = <1>;
671                                                 remote-endpoint = <&deu1_out_be0>;
672                                         };
673                                 };
674
675                                 be0_out: port@1 {
676                                         reg = <1>;
677
678                                         be0_out_drc0: endpoint {
679                                                 remote-endpoint = <&drc0_in_be0>;
680                                         };
681                                 };
682                         };
683                 };
684
685                 be1: display-backend@3240000 {
686                         compatible = "allwinner,sun9i-a80-display-backend";
687                         reg = <0x03240000 0x40000>;
688                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
689                         clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
690                                  <&de_clocks CLK_DRAM_BE1>;
691                         clock-names = "ahb", "mod",
692                                       "ram";
693                         resets = <&de_clocks RST_BE1>;
694
695                         ports {
696                                 #address-cells = <1>;
697                                 #size-cells = <0>;
698
699                                 be1_in: port@0 {
700                                         #address-cells = <1>;
701                                         #size-cells = <0>;
702                                         reg = <0>;
703
704                                         be1_in_deu0: endpoint@0 {
705                                                 reg = <0>;
706                                                 remote-endpoint = <&deu0_out_be1>;
707                                         };
708
709                                         be1_in_deu1: endpoint@1 {
710                                                 reg = <1>;
711                                                 remote-endpoint = <&deu1_out_be1>;
712                                         };
713                                 };
714
715                                 be1_out: port@1 {
716                                         reg = <1>;
717
718                                         be1_out_drc1: endpoint {
719                                                 remote-endpoint = <&drc1_in_be1>;
720                                         };
721                                 };
722                         };
723                 };
724
725                 deu0: deu@3300000 {
726                         compatible = "allwinner,sun9i-a80-deu";
727                         reg = <0x03300000 0x40000>;
728                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
729                         clocks = <&de_clocks CLK_BUS_DEU0>,
730                                  <&de_clocks CLK_IEP_DEU0>,
731                                  <&de_clocks CLK_DRAM_DEU0>;
732                         clock-names = "ahb",
733                                       "mod",
734                                       "ram";
735                         resets = <&de_clocks RST_DEU0>;
736
737                         ports {
738                                 #address-cells = <1>;
739                                 #size-cells = <0>;
740
741                                 deu0_in: port@0 {
742                                         reg = <0>;
743
744                                         deu0_in_fe0: endpoint {
745                                                 remote-endpoint = <&fe0_out_deu0>;
746                                         };
747                                 };
748
749                                 deu0_out: port@1 {
750                                         #address-cells = <1>;
751                                         #size-cells = <0>;
752                                         reg = <1>;
753
754                                         deu0_out_be0: endpoint@0 {
755                                                 reg = <0>;
756                                                 remote-endpoint = <&be0_in_deu0>;
757                                         };
758
759                                         deu0_out_be1: endpoint@1 {
760                                                 reg = <1>;
761                                                 remote-endpoint = <&be1_in_deu0>;
762                                         };
763                                 };
764                         };
765                 };
766
767                 deu1: deu@3340000 {
768                         compatible = "allwinner,sun9i-a80-deu";
769                         reg = <0x03340000 0x40000>;
770                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
771                         clocks = <&de_clocks CLK_BUS_DEU1>,
772                                  <&de_clocks CLK_IEP_DEU1>,
773                                  <&de_clocks CLK_DRAM_DEU1>;
774                         clock-names = "ahb",
775                                       "mod",
776                                       "ram";
777                         resets = <&de_clocks RST_DEU1>;
778
779                         ports {
780                                 #address-cells = <1>;
781                                 #size-cells = <0>;
782
783                                 deu1_in: port@0 {
784                                         reg = <0>;
785
786                                         deu1_in_fe1: endpoint {
787                                                 remote-endpoint = <&fe1_out_deu1>;
788                                         };
789                                 };
790
791                                 deu1_out: port@1 {
792                                         #address-cells = <1>;
793                                         #size-cells = <0>;
794                                         reg = <1>;
795
796                                         deu1_out_be0: endpoint@0 {
797                                                 reg = <0>;
798                                                 remote-endpoint = <&be0_in_deu1>;
799                                         };
800
801                                         deu1_out_be1: endpoint@1 {
802                                                 reg = <1>;
803                                                 remote-endpoint = <&be1_in_deu1>;
804                                         };
805                                 };
806                         };
807                 };
808
809                 drc0: drc@3400000 {
810                         compatible = "allwinner,sun9i-a80-drc";
811                         reg = <0x03400000 0x40000>;
812                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
813                         clocks = <&de_clocks CLK_BUS_DRC0>,
814                                  <&de_clocks CLK_IEP_DRC0>,
815                                  <&de_clocks CLK_DRAM_DRC0>;
816                         clock-names = "ahb",
817                                       "mod",
818                                       "ram";
819                         resets = <&de_clocks RST_DRC0>;
820
821                         ports {
822                                 #address-cells = <1>;
823                                 #size-cells = <0>;
824
825                                 drc0_in: port@0 {
826                                         reg = <0>;
827
828                                         drc0_in_be0: endpoint {
829                                                 remote-endpoint = <&be0_out_drc0>;
830                                         };
831                                 };
832
833                                 drc0_out: port@1 {
834                                         reg = <1>;
835
836                                         drc0_out_tcon0: endpoint {
837                                                 remote-endpoint = <&tcon0_in_drc0>;
838                                         };
839                                 };
840                         };
841                 };
842
843                 drc1: drc@3440000 {
844                         compatible = "allwinner,sun9i-a80-drc";
845                         reg = <0x03440000 0x40000>;
846                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
847                         clocks = <&de_clocks CLK_BUS_DRC1>,
848                                  <&de_clocks CLK_IEP_DRC1>,
849                                  <&de_clocks CLK_DRAM_DRC1>;
850                         clock-names = "ahb",
851                                       "mod",
852                                       "ram";
853                         resets = <&de_clocks RST_DRC1>;
854
855                         ports {
856                                 #address-cells = <1>;
857                                 #size-cells = <0>;
858
859                                 drc1_in: port@0 {
860                                         reg = <0>;
861
862                                         drc1_in_be1: endpoint {
863                                                 remote-endpoint = <&be1_out_drc1>;
864                                         };
865                                 };
866
867                                 drc1_out: port@1 {
868                                         reg = <1>;
869
870                                         drc1_out_tcon1: endpoint {
871                                                 remote-endpoint = <&tcon1_in_drc1>;
872                                         };
873                                 };
874                         };
875                 };
876
877                 tcon0: lcd-controller@3c00000 {
878                         compatible = "allwinner,sun9i-a80-tcon-lcd";
879                         reg = <0x03c00000 0x10000>;
880                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
881                         clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
882                         clock-names = "ahb", "tcon-ch0";
883                         resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
884                         reset-names = "lcd", "edp";
885                         clock-output-names = "tcon0-pixel-clock";
886                         #clock-cells = <0>;
887
888                         ports {
889                                 #address-cells = <1>;
890                                 #size-cells = <0>;
891
892                                 tcon0_in: port@0 {
893                                         reg = <0>;
894
895                                         tcon0_in_drc0: endpoint {
896                                                 remote-endpoint = <&drc0_out_tcon0>;
897                                         };
898                                 };
899
900                                 tcon0_out: port@1 {
901                                         reg = <1>;
902                                 };
903                         };
904                 };
905
906                 tcon1: lcd-controller@3c10000 {
907                         compatible = "allwinner,sun9i-a80-tcon-tv";
908                         reg = <0x03c10000 0x10000>;
909                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
910                         clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
911                         clock-names = "ahb", "tcon-ch1";
912                         resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
913                         reset-names = "lcd", "edp";
914
915                         ports {
916                                 #address-cells = <1>;
917                                 #size-cells = <0>;
918
919                                 tcon1_in: port@0 {
920                                         reg = <0>;
921
922                                         tcon1_in_drc1: endpoint {
923                                                 remote-endpoint = <&drc1_out_tcon1>;
924                                         };
925                                 };
926
927                                 tcon1_out: port@1 {
928                                         reg = <1>;
929                                 };
930                         };
931                 };
932
933                 ccu: clock@6000000 {
934                         compatible = "allwinner,sun9i-a80-ccu";
935                         reg = <0x06000000 0x800>;
936                         clocks = <&osc24M>, <&osc32k>;
937                         clock-names = "hosc", "losc";
938                         #clock-cells = <1>;
939                         #reset-cells = <1>;
940                 };
941
942                 timer@6000c00 {
943                         compatible = "allwinner,sun4i-a10-timer";
944                         reg = <0x06000c00 0xa0>;
945                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
946                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
947                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
948                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
949                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
950                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
951
952                         clocks = <&osc24M>;
953                 };
954
955                 wdt: watchdog@6000ca0 {
956                         compatible = "allwinner,sun6i-a31-wdt";
957                         reg = <0x06000ca0 0x20>;
958                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
959                         clocks = <&osc24M>;
960                 };
961
962                 pio: pinctrl@6000800 {
963                         compatible = "allwinner,sun9i-a80-pinctrl";
964                         reg = <0x06000800 0x400>;
965                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
966                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
967                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
968                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
969                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
970                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
971                         clock-names = "apb", "hosc", "losc";
972                         gpio-controller;
973                         interrupt-controller;
974                         #interrupt-cells = <3>;
975                         #gpio-cells = <3>;
976
977                         gmac_rgmii_pins: gmac-rgmii-pins {
978                                 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
979                                        "PA7", "PA8", "PA9", "PA10", "PA12",
980                                        "PA13", "PA15", "PA16", "PA17";
981                                 function = "gmac";
982                                 /*
983                                  * data lines in RGMII mode use DDR mode
984                                  * and need a higher signal drive strength
985                                  */
986                                 drive-strength = <40>;
987                         };
988
989                         i2c3_pins: i2c3-pins {
990                                 pins = "PG10", "PG11";
991                                 function = "i2c3";
992                         };
993
994                         lcd0_rgb888_pins: lcd0-rgb888-pins {
995                                 pins = "PD0", "PD1", "PD2", "PD3",
996                                        "PD4", "PD5", "PD6", "PD7",
997                                        "PD8", "PD9", "PD10", "PD11",
998                                        "PD12", "PD13", "PD14", "PD15",
999                                        "PD16", "PD17", "PD18", "PD19",
1000                                        "PD20", "PD21", "PD22", "PD23",
1001                                        "PD24", "PD25", "PD26", "PD27";
1002                                 function = "lcd0";
1003                         };
1004
1005                         mmc0_pins: mmc0-pins {
1006                                 pins = "PF0", "PF1" ,"PF2", "PF3",
1007                                        "PF4", "PF5";
1008                                 function = "mmc0";
1009                                 drive-strength = <30>;
1010                                 bias-pull-up;
1011                         };
1012
1013                         mmc1_pins: mmc1-pins {
1014                                 pins = "PG0", "PG1" ,"PG2", "PG3",
1015                                                  "PG4", "PG5";
1016                                 function = "mmc1";
1017                                 drive-strength = <30>;
1018                                 bias-pull-up;
1019                         };
1020
1021                         mmc2_8bit_pins: mmc2-8bit-pins {
1022                                 pins = "PC6", "PC7", "PC8", "PC9",
1023                                        "PC10", "PC11", "PC12",
1024                                        "PC13", "PC14", "PC15",
1025                                        "PC16";
1026                                 function = "mmc2";
1027                                 drive-strength = <30>;
1028                                 bias-pull-up;
1029                         };
1030
1031                         uart0_ph_pins: uart0-ph-pins {
1032                                 pins = "PH12", "PH13";
1033                                 function = "uart0";
1034                         };
1035
1036                         uart4_pins: uart4-pins {
1037                                 pins = "PG12", "PG13", "PG14", "PG15";
1038                                 function = "uart4";
1039                         };
1040                 };
1041
1042                 uart0: serial@7000000 {
1043                         compatible = "snps,dw-apb-uart";
1044                         reg = <0x07000000 0x400>;
1045                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1046                         reg-shift = <2>;
1047                         reg-io-width = <4>;
1048                         clocks = <&ccu CLK_BUS_UART0>;
1049                         resets = <&ccu RST_BUS_UART0>;
1050                         status = "disabled";
1051                 };
1052
1053                 uart1: serial@7000400 {
1054                         compatible = "snps,dw-apb-uart";
1055                         reg = <0x07000400 0x400>;
1056                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1057                         reg-shift = <2>;
1058                         reg-io-width = <4>;
1059                         clocks = <&ccu CLK_BUS_UART1>;
1060                         resets = <&ccu RST_BUS_UART1>;
1061                         status = "disabled";
1062                 };
1063
1064                 uart2: serial@7000800 {
1065                         compatible = "snps,dw-apb-uart";
1066                         reg = <0x07000800 0x400>;
1067                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1068                         reg-shift = <2>;
1069                         reg-io-width = <4>;
1070                         clocks = <&ccu CLK_BUS_UART2>;
1071                         resets = <&ccu RST_BUS_UART2>;
1072                         status = "disabled";
1073                 };
1074
1075                 uart3: serial@7000c00 {
1076                         compatible = "snps,dw-apb-uart";
1077                         reg = <0x07000c00 0x400>;
1078                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1079                         reg-shift = <2>;
1080                         reg-io-width = <4>;
1081                         clocks = <&ccu CLK_BUS_UART3>;
1082                         resets = <&ccu RST_BUS_UART3>;
1083                         status = "disabled";
1084                 };
1085
1086                 uart4: serial@7001000 {
1087                         compatible = "snps,dw-apb-uart";
1088                         reg = <0x07001000 0x400>;
1089                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1090                         reg-shift = <2>;
1091                         reg-io-width = <4>;
1092                         clocks = <&ccu CLK_BUS_UART4>;
1093                         resets = <&ccu RST_BUS_UART4>;
1094                         status = "disabled";
1095                 };
1096
1097                 uart5: serial@7001400 {
1098                         compatible = "snps,dw-apb-uart";
1099                         reg = <0x07001400 0x400>;
1100                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1101                         reg-shift = <2>;
1102                         reg-io-width = <4>;
1103                         clocks = <&ccu CLK_BUS_UART5>;
1104                         resets = <&ccu RST_BUS_UART5>;
1105                         status = "disabled";
1106                 };
1107
1108                 i2c0: i2c@7002800 {
1109                         compatible = "allwinner,sun6i-a31-i2c";
1110                         reg = <0x07002800 0x400>;
1111                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1112                         clocks = <&ccu CLK_BUS_I2C0>;
1113                         resets = <&ccu RST_BUS_I2C0>;
1114                         status = "disabled";
1115                         #address-cells = <1>;
1116                         #size-cells = <0>;
1117                 };
1118
1119                 i2c1: i2c@7002c00 {
1120                         compatible = "allwinner,sun6i-a31-i2c";
1121                         reg = <0x07002c00 0x400>;
1122                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1123                         clocks = <&ccu CLK_BUS_I2C1>;
1124                         resets = <&ccu RST_BUS_I2C1>;
1125                         status = "disabled";
1126                         #address-cells = <1>;
1127                         #size-cells = <0>;
1128                 };
1129
1130                 i2c2: i2c@7003000 {
1131                         compatible = "allwinner,sun6i-a31-i2c";
1132                         reg = <0x07003000 0x400>;
1133                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1134                         clocks = <&ccu CLK_BUS_I2C2>;
1135                         resets = <&ccu RST_BUS_I2C2>;
1136                         status = "disabled";
1137                         #address-cells = <1>;
1138                         #size-cells = <0>;
1139                 };
1140
1141                 i2c3: i2c@7003400 {
1142                         compatible = "allwinner,sun6i-a31-i2c";
1143                         reg = <0x07003400 0x400>;
1144                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1145                         clocks = <&ccu CLK_BUS_I2C3>;
1146                         resets = <&ccu RST_BUS_I2C3>;
1147                         status = "disabled";
1148                         #address-cells = <1>;
1149                         #size-cells = <0>;
1150                 };
1151
1152                 i2c4: i2c@7003800 {
1153                         compatible = "allwinner,sun6i-a31-i2c";
1154                         reg = <0x07003800 0x400>;
1155                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1156                         clocks = <&ccu CLK_BUS_I2C4>;
1157                         resets = <&ccu RST_BUS_I2C4>;
1158                         status = "disabled";
1159                         #address-cells = <1>;
1160                         #size-cells = <0>;
1161                 };
1162
1163                 r_wdt: watchdog@8001000 {
1164                         compatible = "allwinner,sun6i-a31-wdt";
1165                         reg = <0x08001000 0x20>;
1166                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1167                         clocks = <&osc24M>;
1168                 };
1169
1170                 prcm@8001400 {
1171                         compatible = "allwinner,sun9i-a80-prcm";
1172                         reg = <0x08001400 0x200>;
1173                 };
1174
1175                 apbs_rst: reset@80014b0 {
1176                         reg = <0x080014b0 0x4>;
1177                         compatible = "allwinner,sun6i-a31-clock-reset";
1178                         #reset-cells = <1>;
1179                 };
1180
1181                 nmi_intc: interrupt-controller@80015a0 {
1182                         compatible = "allwinner,sun9i-a80-nmi";
1183                         interrupt-controller;
1184                         #interrupt-cells = <2>;
1185                         reg = <0x080015a0 0xc>;
1186                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1187                 };
1188
1189                 r_ir: ir@8002000 {
1190                         compatible = "allwinner,sun6i-a31-ir";
1191                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1192                         pinctrl-names = "default";
1193                         pinctrl-0 = <&r_ir_pins>;
1194                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
1195                         clock-names = "apb", "ir";
1196                         resets = <&apbs_rst 1>;
1197                         reg = <0x08002000 0x40>;
1198                         status = "disabled";
1199                 };
1200
1201                 r_uart: serial@8002800 {
1202                         compatible = "snps,dw-apb-uart";
1203                         reg = <0x08002800 0x400>;
1204                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1205                         reg-shift = <2>;
1206                         reg-io-width = <4>;
1207                         clocks = <&apbs_gates 4>;
1208                         resets = <&apbs_rst 4>;
1209                         status = "disabled";
1210                 };
1211
1212                 r_pio: pinctrl@8002c00 {
1213                         compatible = "allwinner,sun9i-a80-r-pinctrl";
1214                         reg = <0x08002c00 0x400>;
1215                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1217                         clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1218                         clock-names = "apb", "hosc", "losc";
1219                         resets = <&apbs_rst 0>;
1220                         gpio-controller;
1221                         interrupt-controller;
1222                         #interrupt-cells = <3>;
1223                         #gpio-cells = <3>;
1224
1225                         r_ir_pins: r-ir-pins {
1226                                 pins = "PL6";
1227                                 function = "s_cir_rx";
1228                         };
1229
1230                         r_rsb_pins: r-rsb-pins {
1231                                 pins = "PN0", "PN1";
1232                                 function = "s_rsb";
1233                                 drive-strength = <20>;
1234                                 bias-pull-up;
1235                         };
1236                 };
1237
1238                 r_rsb: rsb@8003400 {
1239                         compatible = "allwinner,sun8i-a23-rsb";
1240                         reg = <0x08003400 0x400>;
1241                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1242                         clocks = <&apbs_gates 3>;
1243                         clock-frequency = <3000000>;
1244                         resets = <&apbs_rst 3>;
1245                         pinctrl-names = "default";
1246                         pinctrl-0 = <&r_rsb_pins>;
1247                         status = "disabled";
1248                         #address-cells = <1>;
1249                         #size-cells = <0>;
1250                 };
1251         };
1252 };