arch/arm/boot/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "sunxi-h3-h5.dtsi"
  44
  45 / {
  46         cpu0_opp_table: opp_table0 {
  47                 compatible = "operating-points-v2";
  48                 opp-shared;
  49
  50                 opp@648000000 {
  51                         opp-hz = /bits/ 64 <648000000>;
  52                         opp-microvolt = <1040000 1040000 1300000>;
  53                         clock-latency-ns = <244144>; /* 8 32k periods */
  54                 };
  55
  56                 opp@816000000 {
  57                         opp-hz = /bits/ 64 <816000000>;
  58                         opp-microvolt = <1100000 1100000 1300000>;
  59                         clock-latency-ns = <244144>; /* 8 32k periods */
  60                 };
  61
  62                 opp@1008000000 {
  63                         opp-hz = /bits/ 64 <1008000000>;
  64                         opp-microvolt = <1200000 1200000 1300000>;
  65                         clock-latency-ns = <244144>; /* 8 32k periods */
  66                 };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         compatible = "arm,cortex-a7";
  75                         device_type = "cpu";
  76                         reg = <0>;
  77                         clocks = <&ccu CLK_CPUX>;
  78                         clock-names = "cpu";
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu@1 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 cpu@2 {
  91                         compatible = "arm,cortex-a7";
  92                         device_type = "cpu";
  93                         reg = <2>;
  94                         operating-points-v2 = <&cpu0_opp_table>;
  95                 };
  96
  97                 cpu@3 {
  98                         compatible = "arm,cortex-a7";
  99                         device_type = "cpu";
 100                         reg = <3>;
 101                         operating-points-v2 = <&cpu0_opp_table>;
 102                 };
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv7-timer";
 107                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 108                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 111         };
 112
 113         soc {
 114                 mali: gpu@1c40000 {
 115                         compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
 116                         reg = <0x01c40000 0x10000>;
 117                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 118                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 124                         interrupt-names = "gp",
 125                                           "gpmmu",
 126                                           "pp0",
 127                                           "ppmmu0",
 128                                           "pp1",
 129                                           "ppmmu1",
 130                                           "pmu";
 131                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 132                         clock-names = "bus", "core";
 133                         resets = <&ccu RST_BUS_GPU>;
 134
 135                         assigned-clocks = <&ccu CLK_GPU>;
 136                         assigned-clock-rates = <384000000>;
 137                 };
 138         };
 139 };
 140
 141 &ccu {
 142         compatible = "allwinner,sun8i-h3-ccu";
 143 };
 144
 145 &display_clocks {
 146         compatible = "allwinner,sun8i-h3-de2-clk";
 147 };
 148
 149 &mmc0 {
 150         compatible = "allwinner,sun7i-a20-mmc";
 151         clocks = <&ccu CLK_BUS_MMC0>,
 152                  <&ccu CLK_MMC0>,
 153                  <&ccu CLK_MMC0_OUTPUT>,
 154                  <&ccu CLK_MMC0_SAMPLE>;
 155         clock-names = "ahb",
 156                       "mmc",
 157                       "output",
 158                       "sample";
 159 };
 160
 161 &mmc1 {
 162         compatible = "allwinner,sun7i-a20-mmc";
 163         clocks = <&ccu CLK_BUS_MMC1>,
 164                  <&ccu CLK_MMC1>,
 165                  <&ccu CLK_MMC1_OUTPUT>,
 166                  <&ccu CLK_MMC1_SAMPLE>;
 167         clock-names = "ahb",
 168                       "mmc",
 169                       "output",
 170                       "sample";
 171 };
 172
 173 &mmc2 {
 174         compatible = "allwinner,sun7i-a20-mmc";
 175         clocks = <&ccu CLK_BUS_MMC2>,
 176                  <&ccu CLK_MMC2>,
 177                  <&ccu CLK_MMC2_OUTPUT>,
 178                  <&ccu CLK_MMC2_SAMPLE>;
 179         clock-names = "ahb",
 180                       "mmc",
 181                       "output",
 182                       "sample";
 183 };
 184
 185 &pio {
 186         compatible = "allwinner,sun8i-h3-pinctrl";
 187 };