arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-r-ccu.h>
  48
  49 / {
  50         interrupt-parent = <&gic>;
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         aliases {
  55         };
  56
  57         chosen {
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu@0 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0>;
  68                 };
  69
  70                 cpu@1 {
  71                         compatible = "arm,cortex-a7";
  72                         device_type = "cpu";
  73                         reg = <1>;
  74                 };
  75
  76                 cpu@2 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <2>;
  80                 };
  81
  82                 cpu@3 {
  83                         compatible = "arm,cortex-a7";
  84                         device_type = "cpu";
  85                         reg = <3>;
  86                 };
  87
  88                 cpu@100 {
  89                         compatible = "arm,cortex-a7";
  90                         device_type = "cpu";
  91                         reg = <0x100>;
  92                 };
  93
  94                 cpu@101 {
  95                         compatible = "arm,cortex-a7";
  96                         device_type = "cpu";
  97                         reg = <0x101>;
  98                 };
  99
 100                 cpu@102 {
 101                         compatible = "arm,cortex-a7";
 102                         device_type = "cpu";
 103                         reg = <0x102>;
 104                 };
 105
 106                 cpu@103 {
 107                         compatible = "arm,cortex-a7";
 108                         device_type = "cpu";
 109                         reg = <0x103>;
 110                 };
 111         };
 112
 113         timer {
 114                 compatible = "arm,armv7-timer";
 115                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 118                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 119         };
 120
 121         clocks {
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges;
 125
 126                 /* TODO: PRCM block has a mux for this. */
 127                 osc24M: osc24M_clk {
 128                         #clock-cells = <0>;
 129                         compatible = "fixed-clock";
 130                         clock-frequency = <24000000>;
 131                         clock-accuracy = <50000>;
 132                         clock-output-names = "osc24M";
 133                 };
 134
 135                 /*
 136                  * This is called "internal OSC" in some places.
 137                  * It is an internal RC-based oscillator.
 138                  * TODO: Its controls are in the PRCM block.
 139                  */
 140                 osc16M: osc16M_clk {
 141                         #clock-cells = <0>;
 142                         compatible = "fixed-clock";
 143                         clock-frequency = <16000000>;
 144                         clock-output-names = "osc16M";
 145                 };
 146
 147                 osc16Md512: osc16Md512_clk {
 148                         #clock-cells = <0>;
 149                         compatible = "fixed-factor-clock";
 150                         clock-div = <512>;
 151                         clock-mult = <1>;
 152                         clocks = <&osc16M>;
 153                         clock-output-names = "osc16M-d512";
 154                 };
 155         };
 156
 157         memory {
 158                 reg = <0x40000000 0x80000000>;
 159                 device_type = "memory";
 160         };
 161
 162         soc {
 163                 compatible = "simple-bus";
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166                 ranges;
 167
 168                 syscon: syscon@1c00000 {
 169                         compatible = "allwinner,sun8i-a83t-system-controller",
 170                                 "syscon";
 171                         reg = <0x01c00000 0x1000>;
 172                 };
 173
 174                 dma: dma-controller@1c02000 {
 175                         compatible = "allwinner,sun8i-a83t-dma";
 176                         reg = <0x01c02000 0x1000>;
 177                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 178                         clocks = <&ccu 21>;
 179                         resets = <&ccu 7>;
 180                         #dma-cells = <1>;
 181                 };
 182
 183                 ccu: clock@1c20000 {
 184                         compatible = "allwinner,sun8i-a83t-ccu";
 185                         reg = <0x01c20000 0x400>;
 186                         clocks = <&osc24M>, <&osc16Md512>;
 187                         clock-names = "hosc", "losc";
 188                         #clock-cells = <1>;
 189                         #reset-cells = <1>;
 190                 };
 191
 192                 pio: pinctrl@1c20800 {
 193                         compatible = "allwinner,sun8i-a83t-pinctrl";
 194                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 197                         reg = <0x01c20800 0x400>;
 198                         clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
 199                         clock-names = "apb", "hosc", "losc";
 200                         gpio-controller;
 201                         interrupt-controller;
 202                         #interrupt-cells = <3>;
 203                         #gpio-cells = <3>;
 204
 205                         mmc0_pins: mmc0-pins {
 206                                 pins = "PF0", "PF1", "PF2",
 207                                        "PF3", "PF4", "PF5";
 208                                 function = "mmc0";
 209                                 drive-strength = <30>;
 210                                 bias-pull-up;
 211                         };
 212
 213                         spdif_tx_pin: spdif-tx-pin {
 214                                 pins = "PE18";
 215                                 function = "spdif";
 216                         };
 217
 218                         uart0_pb_pins: uart0-pb-pins {
 219                                 pins = "PB9", "PB10";
 220                                 function = "uart0";
 221                         };
 222
 223                         uart0_pf_pins: uart0-pf-pins {
 224                                 pins = "PF2", "PF4";
 225                                 function = "uart0";
 226                         };
 227                 };
 228
 229                 timer@1c20c00 {
 230                         compatible = "allwinner,sun4i-a10-timer";
 231                         reg = <0x01c20c00 0xa0>;
 232                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 234                         clocks = <&osc24M>;
 235                 };
 236
 237                 watchdog@1c20ca0 {
 238                         compatible = "allwinner,sun6i-a31-wdt";
 239                         reg = <0x01c20ca0 0x20>;
 240                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&osc24M>;
 242                 };
 243
 244                 spdif: spdif@1c21000 {
 245                         #sound-dai-cells = <0>;
 246                         compatible = "allwinner,sun8i-a83t-spdif",
 247                                      "allwinner,sun8i-h3-spdif";
 248                         reg = <0x01c21000 0x400>;
 249                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&ccu 44>, <&ccu 76>;
 251                         resets = <&ccu 32>;
 252                         clock-names = "apb", "spdif";
 253                         dmas = <&dma 2>;
 254                         dma-names = "tx";
 255                         pinctrl-names = "default";
 256                         pinctrl-0 = <&spdif_tx_pin>;
 257                         status = "disabled";
 258                 };
 259
 260                 uart0: serial@01c28000 {
 261                         compatible = "snps,dw-apb-uart";
 262                         reg = <0x01c28000 0x400>;
 263                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 264                         reg-shift = <2>;
 265                         reg-io-width = <4>;
 266                         clocks = <&ccu 53>;
 267                         resets = <&ccu 40>;
 268                         status = "disabled";
 269                 };
 270
 271                 gic: interrupt-controller@1c81000 {
 272                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 273                         reg = <0x01c81000 0x1000>,
 274                               <0x01c82000 0x2000>,
 275                               <0x01c84000 0x2000>,
 276                               <0x01c86000 0x2000>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <3>;
 279                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 280                 };
 281
 282                 r_ccu: clock@1f01400 {
 283                         compatible = "allwinner,sun8i-a83t-r-ccu";
 284                         reg = <0x01f01400 0x400>;
 285                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
 286                                  <&ccu 6>;
 287                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 288                         #clock-cells = <1>;
 289                         #reset-cells = <1>;
 290                 };
 291
 292                 r_pio: pinctrl@1f02c00 {
 293                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
 294                         reg = <0x01f02c00 0x400>;
 295                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 296                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
 297                                  <&osc16Md512>;
 298                         clock-names = "apb", "hosc", "losc";
 299                         gpio-controller;
 300                         #gpio-cells = <3>;
 301                         interrupt-controller;
 302                         #interrupt-cells = <3>;
 303                 };
 304         };
 305 };